WO1995034030A3 - Flash memory based main memory - Google Patents

Flash memory based main memory Download PDF

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Publication number
WO1995034030A3
WO1995034030A3 PCT/US1995/007062 US9507062W WO9534030A3 WO 1995034030 A3 WO1995034030 A3 WO 1995034030A3 US 9507062 W US9507062 W US 9507062W WO 9534030 A3 WO9534030 A3 WO 9534030A3
Authority
WO
WIPO (PCT)
Prior art keywords
mode
flash memory
flash
read
dram
Prior art date
Application number
PCT/US1995/007062
Other languages
French (fr)
Other versions
WO1995034030A2 (en
Inventor
Duane R Mills
Brian Lyn Dipert
Sachidanandan Sambandan
Bruce Mccormick
Richard D Pashley
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to KR1019960706889A priority Critical patent/KR100281432B1/en
Priority to BR9507911A priority patent/BR9507911A/en
Priority to EP95922954A priority patent/EP0765498A4/en
Priority to AU27658/95A priority patent/AU2765895A/en
Publication of WO1995034030A2 publication Critical patent/WO1995034030A2/en
Publication of WO1995034030A3 publication Critical patent/WO1995034030A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A flash memory chip (320) that can be switched into four different read modes is described. Computer systems (100, 200, 300, 800, 1300, 1500) and hierarchies that exploit these modes are also described. In the first read mode, asynchronous flash mode, the flash memory (130) is read as a standard flash memory. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip (320) and a series of addresses belonging to a data burst are specified, one address per clock tick. In the third read mode, asynchronous DRAM (dynamic random access memory) mode, the flash memory (130) emulates DRAM. In the fourth read mode, synchronous DRAM mode, the features of the second and third modes are combined to yield a flash memory that emulates a synchronous DRAM.
PCT/US1995/007062 1994-06-03 1995-06-01 Flash memory based main memory WO1995034030A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019960706889A KR100281432B1 (en) 1994-06-03 1995-06-01 Main memory based on flash memory
BR9507911A BR9507911A (en) 1994-06-03 1995-06-01 Main memory based on flash memory
EP95922954A EP0765498A4 (en) 1994-06-03 1995-06-01 Flash memory based main memory
AU27658/95A AU2765895A (en) 1994-06-03 1995-06-01 Flash memory based main memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/253,499 US5696917A (en) 1994-06-03 1994-06-03 Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
US08/253,499 1994-06-03

Publications (2)

Publication Number Publication Date
WO1995034030A2 WO1995034030A2 (en) 1995-12-14
WO1995034030A3 true WO1995034030A3 (en) 1996-01-18

Family

ID=22960536

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/007062 WO1995034030A2 (en) 1994-06-03 1995-06-01 Flash memory based main memory

Country Status (7)

Country Link
US (4) US5696917A (en)
EP (1) EP0765498A4 (en)
KR (1) KR100281432B1 (en)
CN (2) CN1102772C (en)
AU (1) AU2765895A (en)
BR (1) BR9507911A (en)
WO (1) WO1995034030A2 (en)

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US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation

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