WO1996012297A2 - Simplified dual damascene process for multilevel metallization and interconnection structure - Google Patents
Simplified dual damascene process for multilevel metallization and interconnection structure Download PDFInfo
- Publication number
- WO1996012297A2 WO1996012297A2 PCT/US1995/012194 US9512194W WO9612297A2 WO 1996012297 A2 WO1996012297 A2 WO 1996012297A2 US 9512194 W US9512194 W US 9512194W WO 9612297 A2 WO9612297 A2 WO 9612297A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- opening
- forming
- recited
- etch stop
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
Definitions
- the present invention relates to a semiconductor device containing an interconnection structure comprising conductive wiring and conductive vias on a substrate, and to a dual damascene process for forming an interconnection structure.
- the invention has particular application in submicron circuit manufacturing.
- a traditional method for forming interconnection structures comprises the use of a subtractive etching or etch back step as the primary metal-patterning technique.
- One such traditional technique is illustrated in part in Figs. l(a)-l(b), wherein insulative layer 12, such as an oxide layer, is formed on semiconductor substrate 11, such as onocrystalline silicon, with conductive contacts/vias 13 formed in insulative layer 12.
- a metal layer 14, such as aluminum or tungsten, is deposited on insulating layer 12 and a photoresist pattern 15 formed on metal layer 14 corresponding to the wiring pattern. After etching, a dielectric layer 16 is applied to the resulting wiring pattern 14.
- the interconnection structure comprises conductive contacts/vias 13 and conductive wiring 14.
- a prior attempt to address the disadvantages attendant upon traditional etch back methods for providing interconnection structures comprises a single damascene wiring technique.
- Damascene an art which has been employed for centuries for the fabrication of jewelry, has recently been adapted for application in the semiconductor industry. Damascene basically involves the formation of a trench which is filled in with a metal.
- damascene differs from the traditional etch back methods of providing an interconnection structure by providing a trench which is filled in with metal followed by planarization; whereas, the traditional etch back technique involves building up a metal wiring layer and filling in the interwiring spaces with a dielectric material.
- FIG. 2(a)-2(e) A prior art single damascene technique is illustrated in Figs. 2(a)-2(e) wherein insulative layer 22 is deposited on semiconductor substrate 21.
- a photoresist pattern 23 is formed on insulative layer 22 and openings formed in insulative layer 22 by reactive ion etching (RIE) .
- RIE reactive ion etching
- a metal 24, such as tungsten is deposited within the openings and on insulative layer 22, as by chemical vapor deposition as shown in Fig. 2(d).
- hot aluminum 25 can be formed in the openings and on insulative layer 22 as shown in Fig. 2(e).
- the prior art single damascene technique results in a single conductive opening, e.g., a conductive via.
- the first layer comprises conductive vias 34 with conductive wiring 35 in second insulative layer 33.
- the single damascene technique offers the advantage of improved planarization; however, it is time consuming in requiring numerous processing steps. Undesirably, an interface exists between the conductive via and conductive wiring. Moreover, adequate planarized layers containing an interwiring spacing less than .35 ⁇ cannot be obtained.
- U.S. Patent No. 5,262,354 discloses a three-step method of forming electrically conductive vias and lines involving a damascene technique to create lines on a substrate.
- this patent discloses the advantages of chemical-mechanical polishing with an aluminum slurry in dilute nitric acid to planarize a dielectric surface.
- U.S. Patent No. 5,093,279 discloses a laser ablation damascene process for planarizing metal/polymer structures in the fabrication of both interlevel via metallization and circuitization layers in integrated circuit interconnects.
- the dual damascene technique involves the simultaneous formation of a conductive via and conductive wiring, thereby requiring fewer manipulative steps than the single damascene technique and eliminating the interface between the conductive via and conductive wiring which is necessarily formed by the single damascene technique.
- the dual damascene technique is illustrated in Figs. 4(a)-4(c), wherein insulative layer 42 is deposited on semiconductor substrate 41 and then patterned by conventional photolithographic techniques to form a first opening 43 which is about the size of the ultimate via. Subsequently, as shown in Fig. 4(b), photoresist layer 44 is deposited and patterned to form a second opening about the size of the ultimate trench.
- RIE reactive ion etching
- a conductive material such as aluminum, tungsten, copper or alloys thereof, with or without an adhesion/barrier layer, e.g. , titanium nitride or a titanium-tungsten alloy, under the conductive material, is provided to form conductive via 46 and conductive wiring 47 as shown in Fig. 4(c).
- This process is repeated to form a plurality of layers such as second conductive via 48 and second conductive interconnect wiring 49 also shown in Fig. 4(c).
- the resulting structure is characterized by an interface between the separately formed conductive patterns, i.e., between the first conductive wiring and second conductive via; however, no interface is formed between the conductive via and conductive wiring of each separately formed pattern.
- the dual damascene technique offers advantages vis-a-vis the traditional etch back technique and the single damascene technique, we have found that it also suffers from several disadvantages. We have found that it is extremely difficult to control the profile of the vias and trenches employing the dual damascene technique and, hence, difficult to control the depth and resistivity of the conductive wiring. Moreover, satisfactory planarized layers having an interwiring spacing of less than 0.35 micron cannot be attained with the above-described dual damascene technique.
- An object of the present invention is a highly integrated semiconductor device containing an interconnection structure of planarized layers having minimal interwiring spacing.
- Another object is an improved dual damascene method for forming an interconnection structure having improved control of the profile of conductive vias and conductive wiring.
- a further object of the invention is an improved dual damascene process having a reduced number of manipulative steps.
- a highly integrated semiconductor device having an interconnection structure comprising a plurality of planarized layers with conductive wiring, wherein the distance between conductive wires or interwiring spacing is less than about .35 ⁇ .
- a further aspect of the invention is a method of forming a conductive wiring and conductive via on a substrate, which method comprises forming a first insulative layer on the substrate and an etch stop layer on the first insulative layer. A second insulative layer is formed on the etch stop layer and a first opening of about the size of the ultimate via is formed in the second insulative layer. Using a mask, a trench is formed in the second insulative layer while simultaneously forming a via in the etch stop and in the first insulative layer. Subsequently, a conductive material is simultaneously deposited in and completely fills the via and trench, with the conductive via providing electrical connection between the conductive wiring and substrate.
- Another aspect of the invention is a method of forming a conductive wiring and a conductive via on a substrate, which method comprises forming a first insulative layer on a substrate and forming an etch stop layer on the first insulative layer.
- a second insulative layer is formed in the etch stop layer and a trench formed in the second insulative layer at a first location where the wiring is desired.
- a first opening is then formed in the etch stop layer and in the first insulative layer at a second location where the via is desired, with the first opening penetrating through the etch stop layer and the first insulative layer.
- a conductive material is simultaneously deposited in the first opening and in the trench completely filling the first opening and the trench, the trench forming the conductive wiring, the first opening forming the conductive via, the conductive via providing electrical connection between the conductive wiring and the substrate.
- Another aspect of the invention is a method of forming a conductive wiring and conductive via on a substrate, which method comprises forming an insulating layer on the substrate and forming a trench in the insulative layer at a first location where the wiring is desired. An etch stop layer is then formed in the insulative layer and a first opening formed inside the trench in the etch stop layer at a second location where the via is desired, but not in the insulative layer. A second opening of about the size of the first opening is formed under the first opening in the insulative layer at the second location where the via is desired using the etch stop layer as a hard mask.
- Still another object of the invention is a method of forming a conductive wiring and a conductive via on a substrate, which method comprises forming a first insulative layer on the substrate and forming an etch stop layer on the first insulative layer. A first opening is formed in the etch stop layer at a first location where the via is desired, the first opening penetrating through the etch stop layer. A second insulative layer is formed on the etch stop layer.
- a trench is formed in the second insulative layer at a second location where the wiring is desired and, simultaneously, a second opening is formed through the first opening and the first insulative layer.
- the trench and the second opening penetrates through the second insulative layer and the first insulative layer, respectively.
- a conductive material is then simultaneously deposited in the second opening and in the trench so that the conductive material completely fills the second opening and the trench, the trench forming the conductive wiring, the second opening forming the conductive via and the conductive via providing electrical connection between the conductive wiring and the substrate.
- FIGS. 1(a) and 1(b) are sequential cross-sectional views of a prior art semiconductor substrate showing formation of a conductive via and conductive wiring.
- Figs. 2(a) through 2(e) depict sequential cross- sectional views of a prior art structure formed by a single damascene technique.
- Fig. 3 depicts a prior art semiconductor substrate produced by repetition of a single damascene technique.
- Figs. 4(a) through 4(c) depict sequential cross- sectional views of a prior art structure formed by a dual damascene technique.
- Figs. 5(a) through 5(c) are sequential cross- sectional views of a semiconductor device having a conductive via and conductive wiring formed in accordance with one embodiment of the present invention.
- Figs. 6(a) through 6(c) are sequential cross- sectional views of a semiconductor device having a conductive via and conductive wiring formed in accordance with another aspect of the present invention.
- Figs. 7(a) and 7(b) are sequential cross-sectional views of a semiconductor device having a conductive via and conductive wiring formed in accordance with another embodiment of the present invention.
- Figs. 8(a) through 8(g) are sequential cross- sectional views of a semiconductor device having a conductive via and conductive wiring formed in accordance with another embodiment of the present invention.
- Fig. 9 is a cross-sectional view of a semiconductor device produced in accordance with the present invention.
- the present invention is directed to a semiconductor device comprising a substrate and a plurality of planarized layers vertically formed thereon, and an interconnection structure comprising conductive vias and conductive wiring, wherein the profiles of the conductive vias and conductive wiring are controlled with great accuracy to achieve minimal interwiring spacing as required by high density design rule.
- the interwiring spacing is less than about 0.35 ⁇ . It is particularly preferred to provide an interwiring spacing of from about 0.05 ⁇ to about 0.18 ⁇ , most preferably from about 0.05 ⁇ to about 0.10 ⁇ .
- a semiconductor device having such improved conductive via and conductive wiring profiles and minimal interwiring spacing is achieved by a process comprising a sequence of manipulative steps which include a dual damascene technique wherein vias and trenches are simultaneously filled with a conductive material.
- the various embodiments of the present invention comprises a dual damascene technique wherein the vias and trenches are simultaneously filled with conductive material conventionally employed in fabricating interconnection structures, such as aluminum, tungsten copper and alloys, with or without an adhesion/barrier layer.
- the conductive material is simultaneously deposited in the vias and trenches by techniques which are known in the art.
- metallization techniques such as various types of chemical vapor deposition (CVD) processes, including low pressure chemical vapor deposition (LPCVD), and plasma enhanced chemical vapor deposition (PECVD) may be employed.
- CVD chemical vapor deposition
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- Low melting point metals such as aluminum and aluminum-based alloys including aluminum-copper alloys, may be deposited by melting or sputtering.
- Polysilicon can also be employed as a conductive material in the interconnection pattern.
- planarization techniques such as conventional chemical-mechanical planarization techniques. See, for example, U.S. Patent Nos. 5,262,354 and 4,944,836, which are incorporated by reference herein in their entirety.
- the various embodiments of the present invention involve the formation of openings, such as vias and trenches, employing conventional photolithographic techniques including the use of photoresists, masks, etch recipes, and etching techniques as, for example, plasma etching and reactive ion etching.
- the various embodiments of the present invention also employ an etch stop layer, such as a nitride layer, preferably silicon nitride (Si 3 N 4 ).
- Etch stop layers are conventionally employed in the art of semiconductor manufacturing, as are their methods of deposition, e.g., CVD, or plating.
- the various embodiments of the present invention involve a conventional semiconductor substrate, such as monocrystalline silicon, and conventional insulative layers, such as oxide layers, e.g., layers of a silicon oxide, formed in a conventional manner, as by thermal oxidation of a deposited silicon layer, plasma enhanced CVD, thermal enhanced CVD and spin on techniques.
- a first embodiment of the present invention is sequentially schematically depicted in Figs. 5(a) through 5(c), wherein a first insulative layer 52 is deposited on a semiconductor substrate 51, and an etch stop layer 53 deposited on the first insulative layer 52.
- the etch stop layer can be any suitable conventional stop material selected consistent with the insulative layers.
- the etch stop_ layer can be made of silicon nitride, silicon oxynitride or undoped polysilicon.
- a second insulative layer 54 is deposited on the etch stop layer 53 and a first photoresist mask 55 formed on the second insulative layer.
- a first opening is formed in second insulative layer 54 but not penetrating etch stop layer 53 by a first etching process as shown in Fig. 5(a), preferably anisotropic etching, most preferably reactive ion etching.
- the size of the first opening is about the size of the ultimate via. As shown in Fig.
- a second photoresist mask 56 is formed on second insulative layer 54, a trench is formed in second insulative layer 54 to include the first opening by a second etching process while extending the first opening as shown in phantom lines. As shown in Fig. 5(c), the trench is formed in second insulative layer 54 while simultaneously extending the first opening through etch stop layer 53 and first insulative layer 52.
- the dual damascene metallization technique is then employed to simultaneously fill the via and trench with conductive material to form an interconnection wherein the conductive via provides electrical connection between the conductive wiring and substrate.
- the first etching process has a greater selectivity with respect to the etch stop layer than the second etching process.
- a greater selectivity with respect to the etch stop layer is meant that the insulative layer is etched at a greater rate than the etch stop layer.
- the second insulative layer 54 is planarized, preferably by chemical-mechanical polishing. This first embodiment provides improved control over the profiles of the via and trench by providing better control of their depth.
- FIG. 6(a) through 6(c) A second embodiment of the present invention is illustrated in Figs. 6(a) through 6(c) wherein first insulative layer 62 is deposited on semiconductor substrate 61, and an etch stop layer 63, preferably Si 3 N 4 , deposited on first insulative layer 62.
- a second insulative layer 64 is deposited on etch stop layer 63 and a trench formed in second insulative layer 64 at a first location where the wiring is desired.
- a first opening is formed in etch stop layer 63 and in first insulative layer 62 at a second location where the via is desired, the first opening penetrating through etch stop layer 63 and first insulative layer 62.
- the first and second insulative layers 62 and 64 are oxide layers or insulating materials which have a low dielectric constant.
- the etch stop layer 63 can be any suitable conventional stop material selected consistent with the insulative layers .
- the etch stop layer can be made of silicon nitride, silicon oxynitride or undoped polysilicon.
- the trench in the second insulative layer 64 can be formed by conventional techniques, as by forming a first patterned mask having an opening over second insulative layer 64 in registry with the first location followed by a first etching through second insulative layer 64 stopping at etch stop layer 63.
- the trench can be formed by any of various etching techniques, preferably plasma etching or reactive ion etching. The first mask is then removed.
- the first opening in the etch stop layer and in the first insulative layer can also be formed by conventional techniques as, for example, by forming a patterned photoresist layer 65 as shown in Fig. 6(b) which fills the trench in the second insulative layer 64, and etching a via shown by phantom lines.
- the via is formed by a second etching through etch stop layer 63 and through first insulative layer 62, and removing the photoresist layer 65.
- the thus formed via and trench are shown in Fig. 6(b).
- the second etching can also be plasma etching or reactive ion etching.
- the first etching technique preferably has a higher selectivity with respect to the etch stop layer than the second etching technique.
- the second insulative layer is planarized in a conventional manner, as by chemical- mechanical processing.
- the conductive material employed can be any conductive material conventionally employed in the semiconductor art for providing interconnection patterns, for example, aluminum, aluminum-based alloys and tungsten.
- the second embodiment involves a sequence of steps different from those of the first embodiment, primarily differing by first creating a trench in the second insulative layer and subsequently forming the via; whereas, in the first embodiment, the initially formed opening is about the size of the via and a trench is subsequently formed.
- the second embodiment offers the advantages of avoiding the occurrence of residual photoresist material at the bottom of the via and better control of the etching steps.
- the third embodiment of the present invention avoids the necessity of etching to the depth required in the second embodiment. As shown in Figs. 7(a) and 7(b), the third embodiment comprises forming insulative layer 72 on semiconductor substrate 71.
- a trench 74 is formed in insulative layer 72 at first location where the wiring is desired employing conventional photolithograph techniques.
- An etch stop layer 73 is then formed on insulative layer 72 including the trench.
- An opening is formed inside the trench penetrating through etch stop layer 73 stopping at insulative layer 72 at a second location where the via is desired.
- a second etching is then conducted using the etch stop layer as a hard mask to extend said opening completely through insulative layer 72.
- the etch stop layer 73 is removed and a conductive material is simultaneously deposited in the opening and in the trench so that the conductive material completely fills the opening and the trench, the trench forming the conductive wiring and the opening forming the conductive via, with the conductive via providing electrical contact connection between the conductive wiring and the substrate.
- the trench is formed by a conventional photolithographic technique, as by forming a first patterned mask having a first mask opening over insulative layer 72 in registry with the first location, etching exposed portions of insulative layer 72 through the first mask opening by first etching process to form the trench and removing the first patterned mask layer.
- etch stop layer 73 and insulative layer 72 can also be formed by conventional photolithographic techniques, as, for example, by forming a second mask pattern over etch stop layer 73 inside the trench with the second mask opening in registry with the second location and etching exposed portions of etch stop layer 73 by a second etching process.
- the thus patterned etch stop layer 73 then serves as a hard mask for etching through insulative layer 72 using a third etching process.
- the second and third etching process for penetrating etch stop layer 73 and insulative layer 72, respectively, can be conventional anisotropic techniques, such as plasma etching or reactive ion etching.
- the etch stop material can be any conventional etch stop material capable of serving as a hard mask, i.e., non-photoresist material, e.g., titanium nitride.
- the insulative layer is planarized as by chemical-mechanical polishing.
- the conductive material employed can be any conductive material conventionally employed in the semiconductor art to produce interconnection structures, such as aluminum, aluminum- based alloys, including aluminum-copper alloys, and tungsten.
- a fourth and most preferred embodiment of the present invention which is depicted in Figs. 8(a) through 8(g), is characterized by the advantageous simultaneously etching, in a single step, of the via and trench thereby minimizing the number of manipulative steps and etch recipes. As shown in Figs. 8(a) through 8(g), a first insulative layer 82 is formed on semiconductor substrate 81 " and an etch stop layer 83 formed on first insulative layer 82.
- a first opening 84 is then formed in etch stop layer 83 at a first location where the via is desired, the first opening 84 penetrating through etch stop layer 84 and stopping at first insulative layer 82.
- a second insulative layer 85 is then formed on etch stop layer 83.
- a trench 87 is formed in the second insulative layer 85 at a second location where the wiring is desired and, simultaneously therewith, a second opening 87 is formed through first opening 84 and in first insulative layer 82. The trench 87 and the second opening 87 penetrate through second insulative layer 85 and first insulative layer 82, respectively.
- a conductive material is simultaneously deposited in the second opening and in the trench so that the conductive material completely fills the second opening and the trench, the trench forming the conductive wiring and the second opening forming the conductive via, with the conductive via providing electrical connection between the conductive wiring and the substrate.
- the insulative layers can be an oxide material, such as a silicon oxide.
- the etch stop layer can be any suitable conventional stop material selected consistent with the insulative layers.
- the etch stop layer can be made of silicon nitride, silicon oxynitride or undoped polysilicon.
- the first opening 84 in etch stop layer 83 can be produced by a conventional photolithographic technique, as by forming a first patterned mask over etch stop layer 83 with a first mask opening in registry with the first location, etching the exposed portions of etch stop layer 83 through the mask opening to form first opening 84 and removing the first mask layer.
- a second patterned mask layer is formed over second insulative layer 85 in registry with the second location prior to simultaneously forming trench 87 in second insulative layer 85 and the second opening through the first opening and in first insulative layer 82.
- the second mask layer is removed, as by a conventional selective wet etching technique.
- the conductive material is simultaneously deposited in the second opening and in the trench.
- the simultaneous formation of the trench in the second insulative layer 85 and the via in first insulative layer 82 can be achieved by a conventional anisotropic etching technique, such as plasma etching and reactive ion etching.
- the second insulative layer containing the conductive wiring is planarized as by chemical-mechanical polishing.
- the conductive material can be a metal, preferably a metal selected from the group consisting of aluminum, aluminum- based alloys, and tungsten.
- a second aspect of the fourth embodiment comprises etching etch stop layer 83 so that first opening 84 is not formed completely through etch stop layer 83.
- etching etch stop layer 83 Upon anisotropic etching, a via having substantially vertical walls is formed.
- the fourth embodiment is characterized by the advantageous use of a single etching step to create both the via and trench with a single etch recipe, and obviating the necessity of stripping off etch stop material.
- An interconnection pattern can be produced employing the fourth embodiment wherein the interwiring spacing is reduced to below about .35 ⁇ , preferably to about .25 ⁇ .
- the improved dual damascene technique of the present invention enables the formation of interconnection structures wherein the interwiring spacings, i.e., the distance between conductive lines is minimized.
- an interconnection wiring pattern is shown comprising first insulative layer 92 on semiconductor substrate 91 and second insulative layer 93 on first insulative layer 92, with conductive vias 94 and conductive wiring or conductive lines 95.
- the interwiring spacing D between conductive lines 95 can be advantageously reduced in the present invention as required by high density design rule.
- the interwiring spacing is less than about 0.35 ⁇ .
- an interwiring spacing of from about 0.05 ⁇ to about 0.18 ⁇ , most preferably from about 0.05 ⁇ to about 0.10 ⁇ .
Abstract
A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. An embodiment comprises the simultaneous formation of a via and trench in a single etching step.
Description
SIMPLIFIED DUAL DAMASCENE PROCESS FOR MULTI-LEVEL METALLIZATION AND INTERCONNECTION STRUCTURE
Technical Field
The present invention relates to a semiconductor device containing an interconnection structure comprising conductive wiring and conductive vias on a substrate, and to a dual damascene process for forming an interconnection structure. The invention has particular application in submicron circuit manufacturing.
Background Art
The escalating requirements for density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology which is considered one of the most demanding aspects of ultra large scale integration technology. High density demands for ultra large scale integration semiconductor wiring require planarized layers with minimal spacing between conductive wiring lines.
A traditional method for forming interconnection structures comprises the use of a subtractive etching or etch back step as the primary metal-patterning technique. One such traditional technique is illustrated in part in Figs. l(a)-l(b), wherein insulative layer 12, such as an oxide layer, is formed on semiconductor substrate 11, such as onocrystalline silicon, with conductive contacts/vias 13 formed in insulative layer 12. A metal layer 14, such as aluminum or tungsten, is deposited on
insulating layer 12 and a photoresist pattern 15 formed on metal layer 14 corresponding to the wiring pattern. After etching, a dielectric layer 16 is applied to the resulting wiring pattern 14. The interconnection structure comprises conductive contacts/vias 13 and conductive wiring 14.
In employing such a traditional method, it is extremely difficult to form a planarized layer after filling in the spaces between the conductive wiring 14, as by chemical-mechanical polishing (CMP) planarization techniques. In addition, such a traditional technique often results in the formation of voids 17 as seen in Fig. 1(b) in the spacing between interconnection wirings 14. Additional difficulties include trapping of impurities or volatile materials in the interwiring spaces which may damage the device. Moreover, the traditional etch back approach leads to defects which, even if cosmetic, impose a competitive disadvantage in the commercial environment. Additional disadvantages of traditional etch back methods include poor metal step coverage, residual metal shorts leading to inconsistent manufacturability, low yields, uncertain reliability and poor ultra large scale integration extendability. Significantly, traditional etch back methods were unable to yield sufficiently planarized layers having interwiring spaces of less than 3.5 microns.
A prior attempt to address the disadvantages attendant upon traditional etch back methods for providing interconnection structures comprises a single damascene wiring technique. Damascene, an art which has been employed for centuries for the fabrication of jewelry, has recently been adapted for application in the semiconductor industry. Damascene basically involves the formation of a trench which is filled in with a metal. Thus, damascene differs from the traditional etch back
methods of providing an interconnection structure by providing a trench which is filled in with metal followed by planarization; whereas, the traditional etch back technique involves building up a metal wiring layer and filling in the interwiring spaces with a dielectric material.
A prior art single damascene technique is illustrated in Figs. 2(a)-2(e) wherein insulative layer 22 is deposited on semiconductor substrate 21. A photoresist pattern 23 is formed on insulative layer 22 and openings formed in insulative layer 22 by reactive ion etching (RIE) . Subsequently, a metal 24, such as tungsten, is deposited within the openings and on insulative layer 22, as by chemical vapor deposition as shown in Fig. 2(d). Alternatively, hot aluminum 25 can be formed in the openings and on insulative layer 22 as shown in Fig. 2(e). Thus, the prior art single damascene technique results in a single conductive opening, e.g., a conductive via. Upon planarization and repetition of the foregoing steps, as by depositing a second insulative layer 33, metal 35 and planarization, an interconnection structure is obtained as shown in Fig. 3. The first layer comprises conductive vias 34 with conductive wiring 35 in second insulative layer 33. The single damascene technique offers the advantage of improved planarization; however, it is time consuming in requiring numerous processing steps. Undesirably, an interface exists between the conductive via and conductive wiring. Moreover, adequate planarized layers containing an interwiring spacing less than .35 μ cannot be obtained.
An improvement in the single damascene process, called dual damascene, has recently been developed by IBM. See, for example, Joshi, "A New Damascene Structure for Sub icrometer Interconnect Wiring," IEEE Electron Letters, vol. 14, No. 3, March 1993, pages 129-132; and
Kaanta et al., "Dual Damascene: A ULSI Wiring Technology," June 11-12, 1991, VMIC Conference, IEEE, pages 144-152. The use of a damascene technique wherein the dielectric is planarized by chemical-mechanical polish is discussed in Kenny et al., "A Buried-Plate Trench Cell for a 64-Mb DRAM," 1992 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pages 14 and 15.
U.S. Patent No. 5,262,354 discloses a three-step method of forming electrically conductive vias and lines involving a damascene technique to create lines on a substrate. In addition, this patent discloses the advantages of chemical-mechanical polishing with an aluminum slurry in dilute nitric acid to planarize a dielectric surface. U.S. Patent No. 5,093,279 discloses a laser ablation damascene process for planarizing metal/polymer structures in the fabrication of both interlevel via metallization and circuitization layers in integrated circuit interconnects. The dual damascene technique involves the simultaneous formation of a conductive via and conductive wiring, thereby requiring fewer manipulative steps than the single damascene technique and eliminating the interface between the conductive via and conductive wiring which is necessarily formed by the single damascene technique. The dual damascene technique is illustrated in Figs. 4(a)-4(c), wherein insulative layer 42 is deposited on semiconductor substrate 41 and then patterned by conventional photolithographic techniques to form a first opening 43 which is about the size of the ultimate via. Subsequently, as shown in Fig. 4(b), photoresist layer 44 is deposited and patterned to form a second opening about the size of the ultimate trench. Anisotropic reactive ion etching (RIE) is then conducted which, in effect, duplicates the first and second openings in insulative layer 42, thereby forming a via
and trench. Subsequently, a conductive material such as aluminum, tungsten, copper or alloys thereof, with or without an adhesion/barrier layer, e.g. , titanium nitride or a titanium-tungsten alloy, under the conductive material, is provided to form conductive via 46 and conductive wiring 47 as shown in Fig. 4(c). This process is repeated to form a plurality of layers such as second conductive via 48 and second conductive interconnect wiring 49 also shown in Fig. 4(c). The resulting structure is characterized by an interface between the separately formed conductive patterns, i.e., between the first conductive wiring and second conductive via; however, no interface is formed between the conductive via and conductive wiring of each separately formed pattern.
Although the dual damascene technique offers advantages vis-a-vis the traditional etch back technique and the single damascene technique, we have found that it also suffers from several disadvantages. We have found that it is extremely difficult to control the profile of the vias and trenches employing the dual damascene technique and, hence, difficult to control the depth and resistivity of the conductive wiring. Moreover, satisfactory planarized layers having an interwiring spacing of less than 0.35 micron cannot be attained with the above-described dual damascene technique.
Disclosure of the Invention
An object of the present invention is a highly integrated semiconductor device containing an interconnection structure of planarized layers having minimal interwiring spacing.
Another object is an improved dual damascene method for forming an interconnection structure having improved control of the profile of conductive vias and conductive wiring.
A further object of the invention is an improved dual damascene process having a reduced number of manipulative steps.
Additional objects, advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects are achieved in part by a highly integrated semiconductor device having an interconnection structure comprising a plurality of planarized layers with conductive wiring, wherein the distance between conductive wires or interwiring spacing is less than about .35 μ.
A further aspect of the invention is a method of forming a conductive wiring and conductive via on a substrate, which method comprises forming a first insulative layer on the substrate and an etch stop layer on the first insulative layer. A second insulative layer is formed on the etch stop layer and a first opening of about the size of the ultimate via is formed in the second insulative layer. Using a mask, a trench is formed in the second insulative layer while simultaneously forming a via in the etch stop and in the first insulative layer. Subsequently, a conductive material is simultaneously deposited in and completely fills the via and trench, with the conductive via providing electrical connection between the conductive wiring and substrate.
Another aspect of the invention is a method of forming a conductive wiring and a conductive via on a substrate, which method comprises forming a first
insulative layer on a substrate and forming an etch stop layer on the first insulative layer. A second insulative layer is formed in the etch stop layer and a trench formed in the second insulative layer at a first location where the wiring is desired. A first opening is then formed in the etch stop layer and in the first insulative layer at a second location where the via is desired, with the first opening penetrating through the etch stop layer and the first insulative layer. Subsequently, a conductive material is simultaneously deposited in the first opening and in the trench completely filling the first opening and the trench, the trench forming the conductive wiring, the first opening forming the conductive via, the conductive via providing electrical connection between the conductive wiring and the substrate.
Another aspect of the invention is a method of forming a conductive wiring and conductive via on a substrate, which method comprises forming an insulating layer on the substrate and forming a trench in the insulative layer at a first location where the wiring is desired. An etch stop layer is then formed in the insulative layer and a first opening formed inside the trench in the etch stop layer at a second location where the via is desired, but not in the insulative layer. A second opening of about the size of the first opening is formed under the first opening in the insulative layer at the second location where the via is desired using the etch stop layer as a hard mask. The etch stop layer is then removed and a conductive material is simultaneously deposited in the openings and in the trench so that the conductive material completely fills the openings and the trench, the trench forming the conductive wiring, the openings forming the conductive via, and the conductive via providing electrical connection between the conductive wiring and the substrate.
Still another object of the invention is a method of forming a conductive wiring and a conductive via on a substrate, which method comprises forming a first insulative layer on the substrate and forming an etch stop layer on the first insulative layer. A first opening is formed in the etch stop layer at a first location where the via is desired, the first opening penetrating through the etch stop layer. A second insulative layer is formed on the etch stop layer. Subsequently, a trench is formed in the second insulative layer at a second location where the wiring is desired and, simultaneously, a second opening is formed through the first opening and the first insulative layer. The trench and the second opening penetrates through the second insulative layer and the first insulative layer, respectively. A conductive material is then simultaneously deposited in the second opening and in the trench so that the conductive material completely fills the second opening and the trench, the trench forming the conductive wiring, the second opening forming the conductive via and the conductive via providing electrical connection between the conductive wiring and the substrate.
Brief Description of Drawings Figs. 1(a) and 1(b) are sequential cross-sectional views of a prior art semiconductor substrate showing formation of a conductive via and conductive wiring.
Figs. 2(a) through 2(e) depict sequential cross- sectional views of a prior art structure formed by a single damascene technique.
Fig. 3 depicts a prior art semiconductor substrate produced by repetition of a single damascene technique. Figs. 4(a) through 4(c) depict sequential cross- sectional views of a prior art structure formed by a dual damascene technique.
Figs. 5(a) through 5(c) are sequential cross- sectional views of a semiconductor device having a conductive via and conductive wiring formed in accordance with one embodiment of the present invention. Figs. 6(a) through 6(c) are sequential cross- sectional views of a semiconductor device having a conductive via and conductive wiring formed in accordance with another aspect of the present invention.
Figs. 7(a) and 7(b) are sequential cross-sectional views of a semiconductor device having a conductive via and conductive wiring formed in accordance with another embodiment of the present invention.
Figs. 8(a) through 8(g) are sequential cross- sectional views of a semiconductor device having a conductive via and conductive wiring formed in accordance with another embodiment of the present invention.
Fig. 9 is a cross-sectional view of a semiconductor device produced in accordance with the present invention.
Description of the invention The present invention is directed to a semiconductor device comprising a substrate and a plurality of planarized layers vertically formed thereon, and an interconnection structure comprising conductive vias and conductive wiring, wherein the profiles of the conductive vias and conductive wiring are controlled with great accuracy to achieve minimal interwiring spacing as required by high density design rule. Preferably, the interwiring spacing is less than about 0.35 μ. It is particularly preferred to provide an interwiring spacing of from about 0.05 μ to about 0.18 μ, most preferably from about 0.05 μ to about 0.10 μ. A semiconductor device having such improved conductive via and conductive wiring profiles and minimal interwiring spacing is achieved by a process comprising a sequence of manipulative steps which include a dual damascene
technique wherein vias and trenches are simultaneously filled with a conductive material.
The various embodiments of the present invention comprises a dual damascene technique wherein the vias and trenches are simultaneously filled with conductive material conventionally employed in fabricating interconnection structures, such as aluminum, tungsten copper and alloys, with or without an adhesion/barrier layer. The conductive material is simultaneously deposited in the vias and trenches by techniques which are known in the art. For example, metallization techniques such as various types of chemical vapor deposition (CVD) processes, including low pressure chemical vapor deposition (LPCVD), and plasma enhanced chemical vapor deposition (PECVD) may be employed. Normally, when high melting point metals such as tungsten are deposited, CVD techniques are used. Low melting point metals, such as aluminum and aluminum-based alloys including aluminum-copper alloys, may be deposited by melting or sputtering. Polysilicon can also be employed as a conductive material in the interconnection pattern.
The various embodiments of the present invention involve the use of known planarization techniques, such as conventional chemical-mechanical planarization techniques. See, for example, U.S. Patent Nos. 5,262,354 and 4,944,836, which are incorporated by reference herein in their entirety.
The various embodiments of the present invention involve the formation of openings, such as vias and trenches, employing conventional photolithographic techniques including the use of photoresists, masks, etch recipes, and etching techniques as, for example, plasma etching and reactive ion etching. The various embodiments of the present invention also employ an etch stop layer, such as a nitride layer, preferably silicon nitride (Si3N4). Etch stop layers are conventionally
employed in the art of semiconductor manufacturing, as are their methods of deposition, e.g., CVD, or plating. The various embodiments of the present invention involve a conventional semiconductor substrate, such as monocrystalline silicon, and conventional insulative layers, such as oxide layers, e.g., layers of a silicon oxide, formed in a conventional manner, as by thermal oxidation of a deposited silicon layer, plasma enhanced CVD, thermal enhanced CVD and spin on techniques. A first embodiment of the present invention is sequentially schematically depicted in Figs. 5(a) through 5(c), wherein a first insulative layer 52 is deposited on a semiconductor substrate 51, and an etch stop layer 53 deposited on the first insulative layer 52. The etch stop layer can be any suitable conventional stop material selected consistent with the insulative layers. For example, if the insulative layers are made of silicon oxide, the etch stop_ layer can be made of silicon nitride, silicon oxynitride or undoped polysilicon. A second insulative layer 54 is deposited on the etch stop layer 53 and a first photoresist mask 55 formed on the second insulative layer. A first opening is formed in second insulative layer 54 but not penetrating etch stop layer 53 by a first etching process as shown in Fig. 5(a), preferably anisotropic etching, most preferably reactive ion etching. The size of the first opening is about the size of the ultimate via. As shown in Fig. 5(b), after removing the first photoresist mask 55, a second photoresist mask 56 is formed on second insulative layer 54, a trench is formed in second insulative layer 54 to include the first opening by a second etching process while extending the first opening as shown in phantom lines. As shown in Fig. 5(c), the trench is formed in second insulative layer 54 while simultaneously extending the first opening through etch stop layer 53 and first insulative layer 52. The dual damascene
metallization technique is then employed to simultaneously fill the via and trench with conductive material to form an interconnection wherein the conductive via provides electrical connection between the conductive wiring and substrate.
In the first embodiment, the first etching process has a greater selectivity with respect to the etch stop layer than the second etching process. As known in the art, by a greater selectivity with respect to the etch stop layer is meant that the insulative layer is etched at a greater rate than the etch stop layer. After simultaneously filling the via and trench with a conductive material, the second insulative layer 54 is planarized, preferably by chemical-mechanical polishing. This first embodiment provides improved control over the profiles of the via and trench by providing better control of their depth.
A second embodiment of the present invention is illustrated in Figs. 6(a) through 6(c) wherein first insulative layer 62 is deposited on semiconductor substrate 61, and an etch stop layer 63, preferably Si3N4, deposited on first insulative layer 62. A second insulative layer 64 is deposited on etch stop layer 63 and a trench formed in second insulative layer 64 at a first location where the wiring is desired. As shown in Figs. 6(b) (in phantom) and 6(c), a first opening is formed in etch stop layer 63 and in first insulative layer 62 at a second location where the via is desired, the first opening penetrating through etch stop layer 63 and first insulative layer 62. Subsequently, a conductive material is simultaneously deposited in and completely fills the first opening and the trench, the trench forming the conductive wiring and the first opening forming the conductive via, with the conductive via providing electrical connection between the conductive wiring and the substrate.
Adverting to Figs. 6(a) through 6(c), it is preferred that the first and second insulative layers 62 and 64, respectively, are oxide layers or insulating materials which have a low dielectric constant. The etch stop layer 63 can be any suitable conventional stop material selected consistent with the insulative layers . For example, if the insulative layers are made of silicon oxide, the etch stop layer can be made of silicon nitride, silicon oxynitride or undoped polysilicon. The trench in the second insulative layer 64 can be formed by conventional techniques, as by forming a first patterned mask having an opening over second insulative layer 64 in registry with the first location followed by a first etching through second insulative layer 64 stopping at etch stop layer 63. The trench can be formed by any of various etching techniques, preferably plasma etching or reactive ion etching. The first mask is then removed.
The first opening in the etch stop layer and in the first insulative layer can also be formed by conventional techniques as, for example, by forming a patterned photoresist layer 65 as shown in Fig. 6(b) which fills the trench in the second insulative layer 64, and etching a via shown by phantom lines. The via is formed by a second etching through etch stop layer 63 and through first insulative layer 62, and removing the photoresist layer 65. The thus formed via and trench are shown in Fig. 6(b).
The second etching can also be plasma etching or reactive ion etching. The first etching technique preferably has a higher selectivity with respect to the etch stop layer than the second etching technique. Subsequent to simultaneously filling the via and trench with conductive material, the second insulative layer is planarized in a conventional manner, as by chemical- mechanical processing. The conductive material employed
can be any conductive material conventionally employed in the semiconductor art for providing interconnection patterns, for example, aluminum, aluminum-based alloys and tungsten. The second embodiment involves a sequence of steps different from those of the first embodiment, primarily differing by first creating a trench in the second insulative layer and subsequently forming the via; whereas, in the first embodiment, the initially formed opening is about the size of the via and a trench is subsequently formed. The second embodiment offers the advantages of avoiding the occurrence of residual photoresist material at the bottom of the via and better control of the etching steps. The third embodiment of the present invention avoids the necessity of etching to the depth required in the second embodiment. As shown in Figs. 7(a) and 7(b), the third embodiment comprises forming insulative layer 72 on semiconductor substrate 71. Subsequently, a trench 74 is formed in insulative layer 72 at first location where the wiring is desired employing conventional photolithograph techniques. An etch stop layer 73 is then formed on insulative layer 72 including the trench. An opening is formed inside the trench penetrating through etch stop layer 73 stopping at insulative layer 72 at a second location where the via is desired. A second etching is then conducted using the etch stop layer as a hard mask to extend said opening completely through insulative layer 72. The etch stop layer 73 is removed and a conductive material is simultaneously deposited in the opening and in the trench so that the conductive material completely fills the opening and the trench, the trench forming the conductive wiring and the opening forming the conductive via, with the conductive via providing electrical contact connection between the conductive wiring and the substrate.
The trench is formed by a conventional photolithographic technique, as by forming a first patterned mask having a first mask opening over insulative layer 72 in registry with the first location, etching exposed portions of insulative layer 72 through the first mask opening by first etching process to form the trench and removing the first patterned mask layer. The opening in etch stop layer 73 and insulative layer 72 can also be formed by conventional photolithographic techniques, as, for example, by forming a second mask pattern over etch stop layer 73 inside the trench with the second mask opening in registry with the second location and etching exposed portions of etch stop layer 73 by a second etching process. The thus patterned etch stop layer 73 then serves as a hard mask for etching through insulative layer 72 using a third etching process.
The second and third etching process for penetrating etch stop layer 73 and insulative layer 72, respectively, can be conventional anisotropic techniques, such as plasma etching or reactive ion etching. The etch stop material can be any conventional etch stop material capable of serving as a hard mask, i.e., non-photoresist material, e.g., titanium nitride. Subsequent to deposition of the conductive material to simultaneously fill the via and trench, the insulative layer is planarized as by chemical-mechanical polishing. As in the other embodiments, the conductive material employed can be any conductive material conventionally employed in the semiconductor art to produce interconnection structures, such as aluminum, aluminum- based alloys, including aluminum-copper alloys, and tungsten.
In the third embodiment, etching is simplified and can be conducted with greater control since the etch stop material is etched separately from the insulative
material. Thus, the third embodiment advantageously avoids the accurate depth of focus requirement of the second embodiment attendant upon etching large depths. A fourth and most preferred embodiment of the present invention, which is depicted in Figs. 8(a) through 8(g), is characterized by the advantageous simultaneously etching, in a single step, of the via and trench thereby minimizing the number of manipulative steps and etch recipes. As shown in Figs. 8(a) through 8(g), a first insulative layer 82 is formed on semiconductor substrate 81"and an etch stop layer 83 formed on first insulative layer 82. A first opening 84 is then formed in etch stop layer 83 at a first location where the via is desired, the first opening 84 penetrating through etch stop layer 84 and stopping at first insulative layer 82. A second insulative layer 85 is then formed on etch stop layer 83. A trench 87 is formed in the second insulative layer 85 at a second location where the wiring is desired and, simultaneously therewith, a second opening 87 is formed through first opening 84 and in first insulative layer 82. The trench 87 and the second opening 87 penetrate through second insulative layer 85 and first insulative layer 82, respectively. Subsequently, a conductive material is simultaneously deposited in the second opening and in the trench so that the conductive material completely fills the second opening and the trench, the trench forming the conductive wiring and the second opening forming the conductive via, with the conductive via providing electrical connection between the conductive wiring and the substrate.
As in the other embodiments of the present invention, the insulative layers can be an oxide material, such as a silicon oxide. The etch stop layer can be any suitable conventional stop material selected consistent with the insulative layers. For example, if
the insulative layers are made of silicon oxide, the etch stop layer can be made of silicon nitride, silicon oxynitride or undoped polysilicon. The first opening 84 in etch stop layer 83 can be produced by a conventional photolithographic technique, as by forming a first patterned mask over etch stop layer 83 with a first mask opening in registry with the first location, etching the exposed portions of etch stop layer 83 through the mask opening to form first opening 84 and removing the first mask layer. Preferably, a second patterned mask layer is formed over second insulative layer 85 in registry with the second location prior to simultaneously forming trench 87 in second insulative layer 85 and the second opening through the first opening and in first insulative layer 82. The second mask layer is removed, as by a conventional selective wet etching technique. Subsequently, the conductive material is simultaneously deposited in the second opening and in the trench. The simultaneous formation of the trench in the second insulative layer 85 and the via in first insulative layer 82 can be achieved by a conventional anisotropic etching technique, such as plasma etching and reactive ion etching.
As in the other embodiments of the present invention, after simultaneous deposition of the conductive material in the via and in the trench, the second insulative layer containing the conductive wiring is planarized as by chemical-mechanical polishing. The conductive material can be a metal, preferably a metal selected from the group consisting of aluminum, aluminum- based alloys, and tungsten.
A second aspect of the fourth embodiment comprises etching etch stop layer 83 so that first opening 84 is not formed completely through etch stop layer 83. Upon anisotropic etching, a via having substantially vertical walls is formed.
The fourth embodiment is characterized by the advantageous use of a single etching step to create both the via and trench with a single etch recipe, and obviating the necessity of stripping off etch stop material. An interconnection pattern can be produced employing the fourth embodiment wherein the interwiring spacing is reduced to below about .35 μ, preferably to about .25 μ.
The improved dual damascene technique of the present invention enables the formation of interconnection structures wherein the interwiring spacings, i.e., the distance between conductive lines is minimized. With reference to Fig. 9, an interconnection wiring pattern is shown comprising first insulative layer 92 on semiconductor substrate 91 and second insulative layer 93 on first insulative layer 92, with conductive vias 94 and conductive wiring or conductive lines 95. The interwiring spacing D between conductive lines 95 can be advantageously reduced in the present invention as required by high density design rule. Preferably, the interwiring spacing is less than about 0.35 μ. It is particularly preferred to provide an interwiring spacing of from about 0.05 μ to about 0.18 μ, most preferably from about 0.05 μ to about 0.10 μ. Thus, the present invention enables the production of semiconductive devices having improved density and ultralarge scale integration comprising a plurality of planarized layers having reduced interwiring spacing.
Claims
1. A method of forming a conductive wiring and a conductive via on a substrate, comprising:
(a) forming a first insulative layer on said substrate; (b) forming an etch stop layer on said first insulative layer;
(c) forming a first opening in said etch stop layer at a first location where said via is desired;
(d) forming a second insulative layer on said etch stop layer;
(e) simultaneously forming a trench in said second insulative layer at a second location where said wiring is desired and a second opening through said first opening and said first insulative layer, said trench and said second opening respectively penetrating through said second insulative layer and said first insulative layer; and
(f) simultaneously depositing a conductive material in said second opening and in said trench so that said conductive material completely fills said second opening and said trench, said trench forming said conductive wiring, said second opening forming said conductive via, said conductive via providing electrical connection between said conductive wiring and said substrate.
2. The method as recited in claim 1, wherein said first insulative layer is an oxide layer.
3. The method as recited in claim 1, wherein said second insulative layer is an oxide layer.
4. The method as recited in claim 1, wherein said etch stop layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride and undoped polysilicon, and said first and second insulative layers are silicon oxide.
5. The method as recited in claim 1, wherein said step of forming said first opening in said etch stop layer includes the steps of:
(a) forming a first patterned mask layer over said etch stop layer with a first mask opening in registry with said first location;
(b) etching exposed portions of said etch stop layer through said mask opening to form said first opening in said etch stop layer; and (c) removing said first mask layer.
6. The method as recited in claim 1, further comprising the step of forming a second patterned mask layer over said second insulative layer in registry with said second location prior to the step of simultaneously forming said trench in said second insulative layer and said second opening through said first opening and said first insulative layer.
7. The method as recited in claim 6, further comprising the step of removing said second mask layer prior to the step of simultaneously depositing said conductive material in said second opening and in said trench.
8. The method as recited in claim 1, wherein said step of simultaneously forming said trench in said second insulative layer and said second opening through said first opening and said first insulative layer is achieved by etching.
9. The method as recited in claim 8, wherein said etching is plasma etching.
10. The method as recited in claim 8, wherein said etching is reactive ion etching.
11. The method as recited in claim 8, wherein said etching is a single etching step.
12. The method as recited in claim 1, further comprising the step of polishing said second insulative layer to planarize said conductive wiring and said second insulative layer.
13. The method as recited in claim 12, wherein said step of polishing is achieved by chemical-mechanical polishing.
14. The method as recited in claim 1, wherein said conductive material is a metal.
15. The method as recited in claim 1, wherein said conductive material comprises a metal selected from the group consisting of aluminum, tungsten, copper and alloys thereof, with or without an adhesion/barrier layer.
16. A method of forming a conductive wiring and a conductive via on a substrate, comprising:
(a) forming a first insulative layer on said substrate;
(b) forming an etch stop layer on said first insulative layer; (c) forming a first patterned mask layer over said etch stop layer with a first mask opening in registry with a first location where said via is desired; (d) etching exposed portions of said etch stop layer through said mask opening to form a first opening in said etch stop layer, said first opening penetrating through said etch stop layer;
(e) removing said first mask layer; (f) forming a second insulative layer on said etch stop layer;
(g) forming a second patterned mask layer over said second insulative layer in registry with a second location where said wiring is desired; (h) simultaneously forming a trench in said second insulative layer at said second location and a second opening through said first opening and said first insulative layer, said trench and said second opening respectively penetrating through said second insulative layer and said first insulative layer;
(i) removing said second mask layer; and ( j) simultaneously depositing a conductive material in said second opening and in said trench so that said conductive material completely fills said second opening and said trench, said trench forming said conductive wiring, said second opening forming said conductive via, said conductive via providing electrical connection between said conductive wiring and said substrate.
17. The method as recited in claim 16, wherein said first insulative layer is an oxide.
18. The method as recited in claim 16, wherein said second insulative layer is an oxide.
19. The method as recited in claim 16, wherein said etch stop layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride and undoped polysilicon, and said first and second insulative layers are silicon oxide.
20. The method as recited in claim 16, wherein said step of simultaneously forming said trench in said second insulative layer and said second opening through said first opening and said first insulative layer is achieved by a single etching step.
21. The method as recited in claim 20, wherein said etching is plasma etching.
22. The method as recited in claim 20, wherein said etching is reactive ion etching.
23. The method as recited in claim 16, further comprising the step of polishing said second insulative layer to planarize said conductive wiring and said second insulative layer.
24. The method as recited in claim 23, wherein said step of polishing is achieved by chemical-mechanical polishing.
25. The method as recited in claim 16, wherein said conductive material comprises a metal selected from the group consisting of aluminum, tungsten, copper and alloys thereof, with or without an adhesion/barrier layer.
26. A method of forming a conductive wiring and a conductive via on a substrate, comprising:
(a) forming a first oxide layer on said substrate;
(b) forming a silicon nitride layer on said first oxide layer; (c) forming a first patterned mask layer over said silicon nitride layer with a first mask opening in registry with a first location where said via is desired;
(d) etching exposed portions of said silicon nitride layer through said mask opening to form a first opening in said silicon nitride layer, said first opening penetrating through said silicon nitride layer;
(e) removing said first mask layer;
(f) forming a second oxide layer on said silicon nitride layer;
(g) forming a second patterned mask layer over said second oxide layer in registry with a second location where said wiring is desired;
(h) simultaneously forming a trench in said second oxide layer at said second location and a second opening through said first opening and said first oxide layer by a single etching step, said trench and said second opening respectively penetrating through said second oxide layer and said first oxide layer; (i) removing said second mask layer; and
(j) simultaneously depositing a conductive material in said second opening and in said trench so that said conductive material completely fills said second opening and said trench, said trench forming said conductive wiring, said second opening forming said conductive via, said conductive via providing electrical connection between said conductive wiring and said substrate, wherein said conductive material comprises a metal selected from the group consisting of aluminum, aluminum- based alloy and tungsten.
27. The method as recited in claim 26, wherein said etching is plasma etching.
28. The method as recited in claim 26, wherein said etching is reactive ion etching.
29. The method as recited in claim 26, further comprising the step of chemical-mechanical polishing said second insulative layer to planarize said conductive wiring and said second insulative layer.
30. A method of forming a conductive wiring and a conductive via on a substrate, comprising:
(a) forming a first insulative layer on said substrate; (b) forming an etch stop layer on said first insulative layer;
(c) forming a second insulative layer on said etch stop layer;
(d) forming a trench in said second insulative layer at a first location where said wiring is desired;
(e) forming a first opening in said etch stop layer and said first insulative layer at a second location where said via is desired, said first opening penetrating through said etch stop layer and said first insulative layer; and
(f) simultaneously depositing a conductive material in said first opening and said trench so that said conductive material completely fills said first opening and said trench, said trench forming said conductive wiring, said first opening forming said conductive via, said conductive via providing electrical connection between said conductive wiring and said substrate.
31. The method as recited in claim 30, wherein said first insulative layer and second insulative layer are oxide layers.
32. The method as recited in claim 30, wherein said etch stop layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride and undoped polysilicon, and said first and second insulative layers are silicon oxide.
33. The method as recited in claim 30, further comprising the step of forming a first patterned mask layer having a first mask opening over said second insulative layer in registry with said first location prior to the step of forming said trench on said second insulative layer.
34. The method as recited in claim 33, further comprising the step of removing said first mask layer prior to the step of simultaneously depositing said conductive material in said trench and said first opening.
35. The method as recited in claim 30, wherein said step of forming said trench in said second insulative layer is achieved by etching using a first etching process.
36. The method as recited in claim 35, wherein said step of forming said first opening in said etch stop layer and said first insulative layer includes the steps of: (a) forming a second patterned mask layer over said etch stop layer with a second mask opening in registry with said second location;
(b) etching exposed portion of said etch stop layer using a second etching process; (c) thereafter removing said first insulative layer through said mask opening to form said first opening in said etch stop layer and in said first insulative layer using said second etching process; and
(d) removing said second mask layer.
37. The method as recited in claim 36, wherein said first etching process and said second etching process are achieved by plasma etching.
38. The method as recited in claim 36, wherein said first etching process and said second etching process are achieved by reactive ion etching.
39. The method as recited in claim 38, wherein said first etching process has higher selectivity with respect to said etch stop layer than said second etching process.
40. The method as recited in claim 30, further comprising the step of polishing said second insulative layer to planarize said conductive wiring and said second insulative layer.
41. The method as recited in claim 40, wherein said step of polishing is achieved by chemical-mechanical polishing.
42. The method as recited in claim 30, wherein said conductive material comprises a metal selected from the group consisting of aluminum, tungsten, copper and alloys thereof, with or without an adhesion/barrier layer.
43. A method of forming a conductive wiring and a conductive via on a substrate, comprising:
(a) forming a first oxide layer on said substrate;
(b) forming an etch stop layer on said first insulative layer;
(c) forming a second oxide layer on said etch stop layer;
(d) forming a first patterned mask layer having a first mask opening over said second oxide layer in registry with a first location where said wiring is desired;
(e) forming a trench in said second oxide layer at said first location by etching using a first etching process; (f) forming a first opening in said etch stop layer and said first insulative layer at a second location where said via is desired, said first opening penetrating through said etch stop layer and said first insulative layer; (g) removing said first mask layer; and
(h) simultaneously depositing a conductive material in said first opening and said trench so that said conductive material completely fills said first opening and said trench, said trench forming said conductive wiring, said first opening forming said conductive via, said conductive via providing electrical connection between said conductive wiring and said substrate.
44. The method as recited in claim 43, wherein said etch stop layer comprises material selected from the group consisting of silicon nitride, silicon oxynitride and undoped polysilicon, and said oxide layers are silicon oxide.
45. The method as recited in claim 43, wherein said step of forming said first opening in said etch stop layer and said first insulative layer includes the steps of: (a) forming a second patterned mask layer over said etch stop layer with a second mask opening in registry with said second location;
(b) etching exposed portions of said etch stop layer using a second etching process; (c) thereafter removing said first insulative layer through said mask opening to form said first opening in said etch stop layer and in said first insulative layer using said second etching process; and
(d) removing said second mask layer.
46. The method as recited in claim 45, wherein said first etching process and said second etching process are achieved by plasma etching.
47. The method as recited in claim 45, wherein said first etching process and said second etching process are achieved by reactive ion etching, and said first etching process has higher selectivity with respect to said etch stop layer than said second etching process.
48. The method as recited in claim 43, further comprising the step of chemical-mechanical polishing said second insulative layer to planarize said conductive wiring and said second.insulative layer.
49. The method as recited in claim 43, wherein said conductive material comprises a metal selected from the group consisting of aluminum, tungsten, copper and alloys thereof, with or without an adhesion/barrier layer.
50. A method of forming a conductive wiring and a conductive via on a substrate, comprising:
(a) forming an insulative layer on said substrate;
(b) forming a trench in said insulative layer at a first location where said wiring is desired;
(c) forming an etch stop layer on said insulative layer;
(d) forming a first opening inside said trench in said etch stop layer at a second location where said via is desired, said opening penetrating through said etch stop layer but not into said insulative layer; (e) forming a second opening under said first opening in said insulative layer at said second location where said via is desired using said etch stop layer as a hard mask;
(f) removing said etch stop layer; and
(g) simultaneously depositing a conductive material in said second opening and said trench so that said conductive material completely fills said second opening and said trench, said trench forming said conductive wiring, said second opening forming said conductive via, said conductive via providing electrical connection between said conductive wiring and said substrate.
51. The method as recited in claim 50, wherein said insulative layer is an oxide layer.
52. The method as recited in claim 50, wherein said etch stop layer comprises a material selected from the group consisting of titanium nitride, undoped. olysilicon and silicon nitride, and said insulative layer is silicon oxide.
53. The method as recited in claim 50, wherein said step of forming said trench on said insulative layer comprises:
(a) forming a first patterned mask layer having a first mask opening over said insulative layer in registry with said first location;
(b) etching exposed portions of said insulative layer through said first mask opening to form said trench using a first etching process; and (c) removing said first patterned mask layer.
54. The method as recited in claim 53, wherein said steps of forming said first opening in said etch stop layer and said second opening in said insulative layer includes the steps of: (a) forming a second patterned mask layer over said etch stop layer inside said trench with a second mask opening in registry with said second location;
(b) etching exposed portions of said etch stop layer using a second etching process; (c) removing said second mask layer; and
(d) etching exposed portions of said insulative layer using said etch stop layer as a hard mask employing a third etching process.
55. The method as recited in claim 54, wherein said first, second and third etching processes are achieved by plasma etching.
56. The method as recited in claim 54, wherein said first, second and third.etching processes are achieved by reactive ion etching.
57. The method as recited in claim 56, wherein said first etching process has higher selectivity with respect to said etch stop layer than said second etching process.
58. The method as recited in claim 50, further comprising the step of polishing said insulative layer to planarize said conductive wiring and said insulative layer.
59. The method as recited in claim 58, wherein said step of polishing is achieved by chemical-mechanical polishing.
60. The method as recited in claim 50, wherein said conductive material comprises a metal selected from the group consisting of aluminum, aluminum-based alloy and tungsten, copper and alloys thereof, with or without an adhesion/barrier layer.
61. A method of forming a conductive wiring and a conductive via on a substrate, comprising:
(a) forming an oxide layer on said substrate;
(b) forming a first patterned mask layer having a first mask opening over said insulative layer in registry with a first location where said wiring is desired;
(c) etching exposed portions of said insulative layer through said first mask opening to form a trench using a first etching process; (d) removing said first patterned mask layer;
(e) forming an etch stop layer on said oxide layer;
(f) forming a first opening inside said trench in said etch stop layer at a second location where said via is desired, said opening penetrating through said etch stop layer but not into said oxide layer;
(g) forming a second opening under said first opening in aid oxide layer at said second location where said via is desired using said etch stop layer as a hard mask; (h) removing said etch stop layer; and
(i) simultaneously depositing a conductive material in said second opening and said trench so that said conductive material completely fills said second opening and said trench, said trench forming said conductive wiring, said opening forming said conductive via, said conductive via providing electrical connection between said conductive wiring and said substrate.
62. The method as recited in claim 61, wherein said etch stop layer comprises a material selected from the group consisting of titanium nitride, undoped polysilicon and silicon nitride.
63. The method as recited in claim 61, wherein said steps of forming said first opening in said etch stop layer and said second opening in said insulative layer include the steps of: (a) forming a second patterned mask layer over said etch stop layer inside said trench with a second mask opening in registry with said second location;
(b) etching exposed portions of said etch stop layer using a second etching process; (c) removing said second mask layer; and
(d) etching exposed portions of said insulative layer using said etch stop layer as a hard mask employing a third etching process.
64. The method as recited in claim 63, wherein said first, second and third etching processes are achieved by plasma etching.
65. The method as recited in claim 63, wherein said first, second and third etching processes are achieved by reactive ion etching, and said first etching process has higher selectivity with respect to said etch stop layer than said second etching process.
66. The method as recited in claim 61, further comprising the step of chemical-mechanical polishing said insulative layer to planarize said conductive wiring and said insulative layer.
67. The method as recited in claim 61, wherein said conductive material comprises a metal selected from the group consisting of aluminum, tungsten, copper and alloys thereof, with or without an adhesion/barrier layer.
68. A product made by the process of claim 1.
69. A product made by the process of claim 16.
70. A product made by the process of claim 26.
71. A product made by the process of claim 30.
72. A product made by the process of claim 43.
73. A product made by the process of claim 50.
74. A product made by the process of claim 61.
75. A semiconductor device comprising a substrate and a plurality of planarized insulative layers thereon, with conductive vias and conductive wiring forming an interconnection structure, wherein the interwiring spacing is less than about 0.35 μ.
76. The semiconductor according to claim 75, wherein the interwiring spacing is less than about 0.18 μ-
77. The semiconductor device according to claim 76, wherein the interwiring spacing is about 0.05 μ to less than about 0.18 μ.
78. The semiconductor device according to claim 77, wherein the interwiring spacing is about 0.05 μ to about 0.10 μ.
79. A method of forming a conductive wiring and a via on a substrate comprising:
(a) forming a first insulative layer on said substrate; (b) forming an etch stop layer on said first insulative layer; (c) forming a second insulative layer on said etch stop layer;
(d) forming an opening in said second insulative layer at a first location where said via is desired, said opening penetrating through said second insulative layer but not into said etch stop layer;
(e) forming a trench in said second insulative layer at a second location where said wiring is desired while simultaneously extending said opening through said etch stop layer and through said first insulative layer; and
(f) simultaneously depositing a conductive material in said opening and in said trench so that said conductive material completely fills said opening and said trench, said trench forming said conductive wiring, said opening in said etch stop layer and said first insulative layer forming said conductive via, said conductive via providing electrical connection between said conductive wiring and said substrate.
80. The method recited in claim 79, wherein the first insulative layer and second insulative layer are oxide layers.
81. The method recited in claim 79, wherein said etch stop layer comprises a material selected from the group consisting if silicon nitride, silicon oxynitride and polysilicon, and said first and second insulative layers are silicon oxide.
82. The method as recited in claim 79, further comprising the step of forming a first patterned mask having a first mask opening over said second insulative layer in registry with the first location prior to forming the opening in the second insulative layer.
83. The method as recited in claim 82, further comprising the step of removing said first mask and providing a second mask having a second opening over said second insulative layer in registry with the second location prior to forming said trench in said second insulative layer and simultaneously forming said via through said etch stop layer and said first insulative layer.
84. The method as recited in claim 79, wherein the step of forming said opening in said second insulative layer is achieved by a first etching process.
85. The method as recited in claim 84, wherein the step of forming a trench in the second insulative layer while simultaneously forming a via in said etch stop layer and in said first insulative layer is achieved by a second etching process.
86. The method as recited in claim 84, wherein the first etching process and the second etching process are plasma etching processes.
87. The method as recited in claim 84, wherein the first etching process and the second etching process are reactive ion etching processes.
88. The method as recited in claim 87, wherein said first etching process has a higher selectivity with respect to the etch stop layer than said second etching process.
89. The method as recited in claim 88, further comprising the step of polishing the second insulative layer to planarize said conductive wiring and said second insulative layer.
90. The method as recited in claim 89, wherein the step of polishing is achieved by chemical-mechanical polishing.
91. The method as recited in claim 89, wherein the said conductive material comprises a metal selected from the group consisting of aluminum, tungsten, copper and alloys thereof, with or without an adhesion/barrier layer.
92. A product made by the process of claim 79.
93. The method as recited in claim 1, wherein said first opening penetrates completely through said etch stop layer to said first insulative layer, and wherein said second opening has tapered walls.
94. The method as recited in claim 1, wherein said first opening does not penetrate completely through said etch stop layer, and wherein said second opening has substantially vertical walls.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69531244T DE69531244T2 (en) | 1994-10-11 | 1995-09-25 | SIMPLIFIED DOUBLE DAMASCEN PROCESS FOR THE PRODUCTION OF A MULTIPLE LAYER METALIZATION AND A CONNECTING STRUCTURE |
EP95935091A EP0761014B1 (en) | 1994-10-11 | 1995-09-25 | Simplified dual damascene process for multilevel metallization and interconnection structure |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/320,516 | 1994-10-11 | ||
US08/320,516 US5635423A (en) | 1994-10-11 | 1994-10-11 | Simplified dual damascene process for multi-level metallization and interconnection structure |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1996012297A2 true WO1996012297A2 (en) | 1996-04-25 |
WO1996012297A3 WO1996012297A3 (en) | 1996-07-25 |
Family
ID=23246781
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1995/012194 WO1996012297A2 (en) | 1994-10-11 | 1995-09-25 | Simplified dual damascene process for multilevel metallization and interconnection structure |
Country Status (5)
Country | Link |
---|---|
US (1) | US5635423A (en) |
EP (1) | EP0761014B1 (en) |
DE (1) | DE69531244T2 (en) |
TW (1) | TW293149B (en) |
WO (1) | WO1996012297A2 (en) |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0766303A2 (en) * | 1995-09-29 | 1997-04-02 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having wiring groove and contact hole formed in self-alignment manner and method of fabricating the same |
US5726100A (en) * | 1996-06-27 | 1998-03-10 | Micron Technology, Inc. | Method of forming contact vias and interconnect channels in a dielectric layer stack with a single mask |
FR2754391A1 (en) * | 1996-10-08 | 1998-04-10 | Sgs Thomson Microelectronics | Increased shape form factor structure for integrated circuit |
GB2325083A (en) * | 1997-05-09 | 1998-11-11 | United Microelectronics Corp | A dual damascene process |
WO1999000839A1 (en) * | 1997-06-26 | 1999-01-07 | Advanced Micro Devices, Inc. | Dual damascene etch process |
EP0951067A1 (en) * | 1998-04-16 | 1999-10-20 | STMicroelectronics S.A. | Integrated circuit with etch stop layer and method of fabrication |
GB2336715A (en) * | 1998-04-24 | 1999-10-27 | United Microelectronics Corp | Dual damascene structure and manufacturing methods. |
GB2337160A (en) * | 1998-02-13 | 1999-11-10 | United Intgrated Circuits Corp | Method of forming interconnections for an embedded DRAM |
GB2340302A (en) * | 1998-07-29 | 2000-02-16 | United Microelectronics Corp | Dual damascene process |
GB2340657A (en) * | 1998-06-10 | 2000-02-23 | United Microelectronics Corp | Dual damascene technique |
US6080529A (en) * | 1997-12-12 | 2000-06-27 | Applied Materials, Inc. | Method of etching patterned layers useful as masking during subsequent etching or for damascene structures |
GB2356974A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
US6331380B1 (en) | 1997-12-12 | 2001-12-18 | Applied Materials, Inc. | Method of pattern etching a low K dielectric layer |
US6537905B1 (en) | 1996-12-30 | 2003-03-25 | Applied Materials, Inc. | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
DE10200428A1 (en) * | 2002-01-09 | 2003-04-30 | Infineon Technologies Ag | Production of contact structures in a metallizing on a semiconductor wafer comprises preparing a wafer having an active region, applying a first insulating layer on the wafer |
DE19700868C2 (en) * | 1996-05-16 | 2003-08-14 | Lg Semicon Co Ltd | Method of making connections in a semiconductor device |
Families Citing this family (220)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5756397A (en) * | 1993-12-28 | 1998-05-26 | Lg Semicon Co., Ltd. | Method of fabricating a wiring in a semiconductor device |
US6093615A (en) | 1994-08-15 | 2000-07-25 | Micron Technology, Inc. | Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug |
US5814529A (en) * | 1995-01-17 | 1998-09-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor |
US5658829A (en) | 1995-02-21 | 1997-08-19 | Micron Technology, Inc. | Semiconductor processing method of forming an electrically conductive contact plug |
US5726498A (en) * | 1995-05-26 | 1998-03-10 | International Business Machines Corporation | Wire shape conferring reduced crosstalk and formation methods |
US5614765A (en) * | 1995-06-07 | 1997-03-25 | Advanced Micro Devices, Inc. | Self aligned via dual damascene |
US6022799A (en) * | 1995-06-07 | 2000-02-08 | Advanced Micro Devices, Inc. | Methods for making a semiconductor device with improved hot carrier lifetime |
JPH0964179A (en) * | 1995-08-25 | 1997-03-07 | Mitsubishi Electric Corp | Semiconductor device and its fabrication method |
US6004875A (en) | 1995-11-15 | 1999-12-21 | Micron Technology, Inc. | Etch stop for use in etching of silicon oxide |
US6294799B1 (en) * | 1995-11-27 | 2001-09-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating same |
US6946716B2 (en) * | 1995-12-29 | 2005-09-20 | International Business Machines Corporation | Electroplated interconnection structures on integrated circuit chips |
US6709562B1 (en) * | 1995-12-29 | 2004-03-23 | International Business Machines Corporation | Method of making electroplated interconnection structures on integrated circuit chips |
US5741626A (en) * | 1996-04-15 | 1998-04-21 | Motorola, Inc. | Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) |
KR100215847B1 (en) * | 1996-05-16 | 1999-08-16 | 구본준 | Metal interconnector of semiconductor device and process for forming the same |
US6043164A (en) * | 1996-06-10 | 2000-03-28 | Sharp Laboratories Of America, Inc. | Method for transferring a multi-level photoresist pattern |
US6429120B1 (en) | 2000-01-18 | 2002-08-06 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
US5693563A (en) * | 1996-07-15 | 1997-12-02 | Chartered Semiconductor Manufacturing Pte Ltd. | Etch stop for copper damascene process |
DE69709870T2 (en) * | 1996-07-18 | 2002-08-22 | Advanced Micro Devices Inc | USE OF AN ETCHING LAYER IN AN INTEGRATED CIRCUIT FOR THE PRODUCTION OF STACKED ARRANGEMENTS |
US5854515A (en) * | 1996-07-23 | 1998-12-29 | Advanced Micro Devices, Inc. | Integrated circuit having conductors of enhanced cross-sectional area |
US5691250A (en) * | 1996-08-29 | 1997-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd | Method of forming a metal contact to a novel polysilicon contact extension |
US5847462A (en) * | 1996-11-14 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer |
JPH10214896A (en) * | 1996-11-29 | 1998-08-11 | Toshiba Corp | Manufacture and manufacture device for semiconductor device |
KR100219508B1 (en) * | 1996-12-30 | 1999-09-01 | 윤종용 | Forming method for matal wiring layer of semiconductor device |
US7510961B2 (en) * | 1997-02-14 | 2009-03-31 | Micron Technology, Inc. | Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure |
US5801094A (en) * | 1997-02-28 | 1998-09-01 | United Microelectronics Corporation | Dual damascene process |
US6025116A (en) * | 1997-03-31 | 2000-02-15 | Siemens Aktiengesellschaft | Etching of contact holes |
DE19715501C1 (en) * | 1997-04-14 | 1998-06-25 | Fraunhofer Ges Forschung | Method for structuring thin metal layers. |
US5876614A (en) * | 1997-04-18 | 1999-03-02 | Storage Technology Corporation | Method of wet etching aluminum oxide to minimize undercutting |
EP0881669B1 (en) * | 1997-05-30 | 2005-12-14 | STMicroelectronics S.r.l. | Manufacturing process of a germanium implanted heterojunction bipolar transistor |
US6057227A (en) * | 1997-06-23 | 2000-05-02 | Vlsi Technology, Inc. | Oxide etch stop techniques for uniform damascene trench depth |
JP3350638B2 (en) * | 1997-06-26 | 2002-11-25 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
US6171957B1 (en) | 1997-07-16 | 2001-01-09 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing method of semiconductor device having high pressure reflow process |
US6100184A (en) * | 1997-08-20 | 2000-08-08 | Sematech, Inc. | Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer |
US6294455B1 (en) * | 1997-08-20 | 2001-09-25 | Micron Technology, Inc. | Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry |
US6080655A (en) * | 1997-08-21 | 2000-06-27 | Micron Technology, Inc. | Method for fabricating conductive components in microelectronic devices and substrate structures thereof |
US6143616A (en) | 1997-08-22 | 2000-11-07 | Micron Technology, Inc. | Methods of forming coaxial integrated circuitry interconnect lines |
US6187677B1 (en) | 1997-08-22 | 2001-02-13 | Micron Technology, Inc. | Integrated circuitry and methods of forming integrated circuitry |
TW377501B (en) * | 1997-09-08 | 1999-12-21 | United Microelectronics Corp | Method of dual damascene |
US6066569A (en) * | 1997-09-30 | 2000-05-23 | Siemens Aktiengesellschaft | Dual damascene process for metal layers and organic intermetal layers |
US5877076A (en) * | 1997-10-14 | 1999-03-02 | Industrial Technology Research Institute | Opposed two-layered photoresist process for dual damascene patterning |
US5935762A (en) * | 1997-10-14 | 1999-08-10 | Industrial Technology Research Institute | Two-layered TSI process for dual damascene patterning |
US6107191A (en) * | 1997-11-07 | 2000-08-22 | Lucent Technologies Inc. | Method of creating an interconnect in a substrate and semiconductor device employing the same |
US6057239A (en) * | 1997-12-17 | 2000-05-02 | Advanced Micro Devices, Inc. | Dual damascene process using sacrificial spin-on materials |
US6291334B1 (en) * | 1997-12-19 | 2001-09-18 | Applied Materials, Inc. | Etch stop layer for dual damascene process |
KR100253385B1 (en) | 1997-12-22 | 2000-05-01 | 김영환 | The manufacturing method of the interconnection layer for semiconductor device |
US6358849B1 (en) * | 1997-12-23 | 2002-03-19 | Texas Instruments Incorporated | Integrated circuit interconnect and method |
KR100494148B1 (en) * | 1997-12-29 | 2006-05-22 | 매그나칩 반도체 유한회사 | Metal wiring layer formation method of MOS PET transistor |
US6169664B1 (en) * | 1998-01-05 | 2001-01-02 | Texas Instruments Incorporated | Selective performance enhancements for interconnect conducting paths |
US6028004A (en) * | 1998-01-06 | 2000-02-22 | International Business Machines Corporation | Process for controlling the height of a stud intersecting an interconnect |
US6051369A (en) * | 1998-01-08 | 2000-04-18 | Kabushiki Kaisha Toshiba | Lithography process using one or more anti-reflective coating films and fabrication process using the lithography process |
US6017813A (en) * | 1998-01-12 | 2000-01-25 | Vanguard International Semiconductor Corporation | Method for fabricating a damascene landing pad |
TW392324B (en) * | 1998-01-23 | 2000-06-01 | United Microelectronics Corp | Dual damascene process |
US6204168B1 (en) | 1998-02-02 | 2001-03-20 | Applied Materials, Inc. | Damascene structure fabricated using a layer of silicon-based photoresist material |
JPH11220025A (en) * | 1998-02-03 | 1999-08-10 | Rohm Co Ltd | Semiconductor device and its manufacture |
TW368741B (en) * | 1998-02-26 | 1999-09-01 | United Microelectronics Corp | Manufacturing method for dual damascene |
US6245684B1 (en) * | 1998-03-13 | 2001-06-12 | Applied Materials, Inc. | Method of obtaining a rounded top trench corner for semiconductor trench etch applications |
US6214731B1 (en) * | 1998-03-25 | 2001-04-10 | Advanced Micro Devices, Inc. | Copper metalization with improved electromigration resistance |
US6197696B1 (en) * | 1998-03-26 | 2001-03-06 | Matsushita Electric Industrial Co., Ltd. | Method for forming interconnection structure |
TW374224B (en) * | 1998-04-03 | 1999-11-11 | United Microelectronics Corp | Dual damascene process for manufacturing low k dielectrics |
US6262450B1 (en) * | 1998-04-22 | 2001-07-17 | International Business Machines Corporation | DRAM stack capacitor with vias and conductive connection extending from above conductive lines to the substrate |
US6063711A (en) * | 1998-04-28 | 2000-05-16 | Taiwan Semiconductor Manufacturing Company | High selectivity etching stop layer for damascene process |
DE19829152A1 (en) * | 1998-05-05 | 1999-11-18 | United Microelectronics Corp | Double damascus process |
US6042999A (en) * | 1998-05-07 | 2000-03-28 | Taiwan Semiconductor Manufacturing Company | Robust dual damascene process |
US6680248B2 (en) | 1998-06-01 | 2004-01-20 | United Microelectronics Corporation | Method of forming dual damascene structure |
TW383463B (en) | 1998-06-01 | 2000-03-01 | United Microelectronics Corp | Manufacturing method for dual damascene structure |
JP3186040B2 (en) * | 1998-06-01 | 2001-07-11 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US6303489B1 (en) | 1998-06-03 | 2001-10-16 | Advanced Micro Devices, Inc. | Spacer - defined dual damascene process method |
US6153521A (en) * | 1998-06-04 | 2000-11-28 | Advanced Micro Devices, Inc. | Metallized interconnection structure and method of making the same |
US6165863A (en) * | 1998-06-22 | 2000-12-26 | Micron Technology, Inc. | Aluminum-filled self-aligned trench for stacked capacitor structure and methods |
US6127258A (en) | 1998-06-25 | 2000-10-03 | Motorola Inc. | Method for forming a semiconductor device |
US6025259A (en) * | 1998-07-02 | 2000-02-15 | Advanced Micro Devices, Inc. | Dual damascene process using high selectivity boundary layers |
US7135445B2 (en) * | 2001-12-04 | 2006-11-14 | Ekc Technology, Inc. | Process for the use of bis-choline and tris-choline in the cleaning of quartz-coated polysilicon and other materials |
US7547669B2 (en) * | 1998-07-06 | 2009-06-16 | Ekc Technology, Inc. | Remover compositions for dual damascene system |
US6319813B1 (en) | 1998-07-06 | 2001-11-20 | Micron Technology, Inc. | Semiconductor processing methods of forming integrated circuitry and integrated circuitry constructions |
US6211092B1 (en) | 1998-07-09 | 2001-04-03 | Applied Materials, Inc. | Counterbore dielectric plasma etch process particularly useful for dual damascene |
US6328804B1 (en) | 1998-07-10 | 2001-12-11 | Ball Semiconductor, Inc. | Chemical vapor deposition of metals on a spherical shaped semiconductor substrate |
US6127263A (en) * | 1998-07-10 | 2000-10-03 | Applied Materials, Inc. | Misalignment tolerant techniques for dual damascene fabrication |
US6140217A (en) * | 1998-07-16 | 2000-10-31 | International Business Machines Corporation | Technique for extending the limits of photolithography |
US6245662B1 (en) | 1998-07-23 | 2001-06-12 | Applied Materials, Inc. | Method of producing an interconnect structure for an integrated circuit |
TW374948B (en) * | 1998-07-28 | 1999-11-21 | United Microelectronics Corp | Method of prevention of poisoning trenches in dual damascene process structures and dielectric layer windows |
TW437040B (en) | 1998-08-12 | 2001-05-28 | Applied Materials Inc | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics |
US6103616A (en) * | 1998-08-19 | 2000-08-15 | Advanced Micro Devices, Inc. | Method to manufacture dual damascene structures by utilizing short resist spacers |
US6440863B1 (en) * | 1998-09-04 | 2002-08-27 | Taiwan Semiconductor Manufacturing Company | Plasma etch method for forming patterned oxygen containing plasma etchable layer |
US6670209B1 (en) | 1998-09-11 | 2003-12-30 | Chartered Semiconductor Manufacturing Ltd. | Embedded metal scheme for liquid crystal display (LCD) application |
US6174803B1 (en) | 1998-09-16 | 2001-01-16 | Vsli Technology | Integrated circuit device interconnection techniques |
US6239017B1 (en) | 1998-09-18 | 2001-05-29 | Industrial Technology Research Institute | Dual damascene CMP process with BPSG reflowed contact hole |
US6326300B1 (en) | 1998-09-21 | 2001-12-04 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method |
US6225207B1 (en) | 1998-10-01 | 2001-05-01 | Applied Materials, Inc. | Techniques for triple and quadruple damascene fabrication |
US6069082A (en) * | 1998-10-13 | 2000-05-30 | Chartered Semiconductor Manufacturing Ltd. | Method to prevent dishing in damascene CMP process |
JP3657788B2 (en) | 1998-10-14 | 2005-06-08 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
US6228758B1 (en) | 1998-10-14 | 2001-05-08 | Advanced Micro Devices, Inc. | Method of making dual damascene conductive interconnections and integrated circuit device comprising same |
US6472335B1 (en) * | 1998-10-19 | 2002-10-29 | Taiwan Semiconductor Manufacturing Company | Methods of adhesion promoter between low-K layer and underlying insulating layer |
US6165898A (en) * | 1998-10-23 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
US6004883A (en) * | 1998-10-23 | 1999-12-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual damascene patterned conductor layer formation method without etch stop layer |
JP4074014B2 (en) * | 1998-10-27 | 2008-04-09 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US6037216A (en) * | 1998-11-02 | 2000-03-14 | Vanguard International Semiconductor Corporation | Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process |
US6060380A (en) * | 1998-11-06 | 2000-05-09 | Advanced Micro Devices, Inc. | Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication |
JP3312604B2 (en) * | 1998-11-06 | 2002-08-12 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US6265308B1 (en) | 1998-11-30 | 2001-07-24 | International Business Machines Corporation | Slotted damascene lines for low resistive wiring lines for integrated circuit |
US6077337A (en) * | 1998-12-01 | 2000-06-20 | Intel Corporation | Chemical-mechanical polishing slurry |
US6093632A (en) * | 1998-12-07 | 2000-07-25 | Industrial Technology Research Institute | Modified dual damascene process |
US6187211B1 (en) | 1998-12-15 | 2001-02-13 | Xerox Corporation | Method for fabrication of multi-step structures using embedded etch stop layers |
TW404007B (en) * | 1998-12-16 | 2000-09-01 | United Microelectronics Corp | The manufacture method of interconnects |
US6181011B1 (en) | 1998-12-29 | 2001-01-30 | Kawasaki Steel Corporation | Method of controlling critical dimension of features in integrated circuits (ICS), ICS formed by the method, and systems utilizing same |
US6287961B1 (en) | 1999-01-04 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
US6331481B1 (en) | 1999-01-04 | 2001-12-18 | International Business Machines Corporation | Damascene etchback for low ε dielectric |
US6207576B1 (en) * | 1999-01-05 | 2001-03-27 | Advanced Micro Devices, Inc. | Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide etch stop layer |
US6333560B1 (en) | 1999-01-14 | 2001-12-25 | International Business Machines Corporation | Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies |
JP2000216247A (en) * | 1999-01-22 | 2000-08-04 | Nec Corp | Semiconductor device and its manufacture |
US20030089987A1 (en) * | 1999-02-05 | 2003-05-15 | Suketu A. Parikh | Dual damascene misalignment tolerant techniques for vias and sacrificial etch segments |
US6211085B1 (en) * | 1999-02-18 | 2001-04-03 | Taiwan Semiconductor Company | Method of preparing CU interconnect lines |
US6261947B1 (en) * | 1999-02-18 | 2001-07-17 | Micron Technology, Inc. | Formation of electrical contacts to conductive elements in the fabrication of semiconductor integrated circuits |
JP3525788B2 (en) | 1999-03-12 | 2004-05-10 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
JP3436221B2 (en) | 1999-03-15 | 2003-08-11 | ソニー株式会社 | Manufacturing method of semiconductor device |
US6323125B1 (en) | 1999-03-29 | 2001-11-27 | Chartered Semiconductor Manufacturing Ltd | Simplified dual damascene process utilizing PPMSO as an insulator layer |
JP3700460B2 (en) * | 1999-04-05 | 2005-09-28 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof |
US6016011A (en) * | 1999-04-27 | 2000-01-18 | Hewlett-Packard Company | Method and apparatus for a dual-inlaid damascene contact to sensor |
US6329280B1 (en) * | 1999-05-13 | 2001-12-11 | International Business Machines Corporation | Interim oxidation of silsesquioxane dielectric for dual damascene process |
US6187666B1 (en) * | 1999-06-08 | 2001-02-13 | Advanced Micro Devices, Inc. | CVD plasma process to fill contact hole in damascene process |
DE19927284C2 (en) * | 1999-06-15 | 2002-01-10 | Infineon Technologies Ag | Method for producing an electrically conductive connection in a microelectronic structure |
KR100578222B1 (en) * | 1999-06-28 | 2006-05-12 | 주식회사 하이닉스반도체 | Improved dual damascene process in semiconductor device |
US6251770B1 (en) * | 1999-06-30 | 2001-06-26 | Lam Research Corp. | Dual-damascene dielectric structures and methods for making the same |
US6133144A (en) * | 1999-08-06 | 2000-10-17 | Taiwan Semiconductor Manufacturing Company | Self aligned dual damascene process and structure with low parasitic capacitance |
EP1077475A3 (en) * | 1999-08-11 | 2003-04-02 | Applied Materials, Inc. | Method of micromachining a multi-part cavity |
DE19937994C2 (en) | 1999-08-11 | 2003-12-11 | Infineon Technologies Ag | Etching process for a dual damascene structuring of an insulating layer on a semiconductor structure |
US6083822A (en) * | 1999-08-12 | 2000-07-04 | Industrial Technology Research Institute | Fabrication process for copper structures |
US6518173B1 (en) | 1999-08-18 | 2003-02-11 | Advanced Micro Devices, Inc. | Method for avoiding fluorine contamination of copper interconnects |
US6573187B1 (en) | 1999-08-20 | 2003-06-03 | Taiwan Semiconductor Manufacturing Company | Method of forming dual damascene structure |
US6365327B1 (en) * | 1999-08-30 | 2002-04-02 | Agere Systems Guardian Corp. | Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit |
US6391756B1 (en) * | 1999-08-31 | 2002-05-21 | Micron Technology, Inc. | Semiconductor processing methods of forming contact openings |
US6265319B1 (en) | 1999-09-01 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Dual damascene method employing spin-on polymer (SOP) etch stop layer |
TW428283B (en) * | 1999-09-03 | 2001-04-01 | Taiwan Semiconductor Mfg | Method for making dual damascene structure |
US6391761B1 (en) | 1999-09-20 | 2002-05-21 | Taiwan Semiconductor Manufacturing Company | Method to form dual damascene structures using a linear passivation |
JP2001102447A (en) * | 1999-09-30 | 2001-04-13 | Mitsubishi Electric Corp | Manufacturing method of contact structure |
US6297149B1 (en) * | 1999-10-05 | 2001-10-02 | International Business Machines Corporation | Methods for forming metal interconnects |
US6506683B1 (en) * | 1999-10-06 | 2003-01-14 | Advanced Micro Devices | In-situ process for fabricating a semiconductor device with integral removal of antireflection and etch stop layers |
US6103619A (en) * | 1999-10-08 | 2000-08-15 | United Microelectronics Corp. | Method of forming a dual damascene structure on a semiconductor wafer |
US6211061B1 (en) | 1999-10-29 | 2001-04-03 | Taiwan Semiconductor Manufactuirng Company | Dual damascene process for carbon-based low-K materials |
US6406994B1 (en) | 1999-12-03 | 2002-06-18 | Chartered Semiconductor Manufacturing Ltd. | Triple-layered low dielectric constant dielectric dual damascene approach |
US6329281B1 (en) * | 1999-12-03 | 2001-12-11 | Agere Systems Guardian Corp. | Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer |
US6372647B1 (en) | 1999-12-14 | 2002-04-16 | International Business Machines Corporation | Via masked line first dual damascene |
JP3821624B2 (en) * | 1999-12-17 | 2006-09-13 | シャープ株式会社 | Manufacturing method of semiconductor device |
KR100373358B1 (en) * | 1999-12-22 | 2003-02-25 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device using via first dual damscene process |
KR100403327B1 (en) * | 1999-12-24 | 2003-10-30 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
US6295721B1 (en) * | 1999-12-28 | 2001-10-02 | Taiwan Semiconductor Manufacturing Company | Metal fuse in copper dual damascene |
US6376370B1 (en) | 2000-01-18 | 2002-04-23 | Micron Technology, Inc. | Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy |
US6420262B1 (en) | 2000-01-18 | 2002-07-16 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
JP3346475B2 (en) * | 2000-01-18 | 2002-11-18 | 日本電気株式会社 | Manufacturing method of semiconductor integrated circuit, semiconductor integrated circuit |
GB0001179D0 (en) * | 2000-01-19 | 2000-03-08 | Trikon Holdings Ltd | Methods & apparatus for forming a film on a substrate |
US6465157B1 (en) | 2000-01-31 | 2002-10-15 | Chartered Semiconductor Manufacturing Ltd | Dual layer pattern formation method for dual damascene interconnect |
US6242344B1 (en) | 2000-02-07 | 2001-06-05 | Institute Of Microelectronics | Tri-layer resist method for dual damascene process |
JP2001230317A (en) * | 2000-02-15 | 2001-08-24 | Nec Corp | Method for forming multilayer interconnection structure and multilayer interconnection structure for semiconductor device |
US6573030B1 (en) | 2000-02-17 | 2003-06-03 | Applied Materials, Inc. | Method for depositing an amorphous carbon layer |
US6812131B1 (en) | 2000-04-11 | 2004-11-02 | Honeywell International Inc. | Use of sacrificial inorganic dielectrics for dual damascene processes utilizing organic intermetal dielectrics |
US6316351B1 (en) | 2000-05-31 | 2001-11-13 | Taiwan Semiconductor Manufacturing Company | Inter-metal dielectric film composition for dual damascene process |
US6521542B1 (en) * | 2000-06-14 | 2003-02-18 | International Business Machines Corp. | Method for forming dual damascene structure |
US6758223B1 (en) * | 2000-06-23 | 2004-07-06 | Infineon Technologies Ag | Plasma RIE polymer removal |
US6426298B1 (en) * | 2000-08-11 | 2002-07-30 | United Microelectronics Corp. | Method of patterning a dual damascene |
US6461963B1 (en) | 2000-08-30 | 2002-10-08 | Micron Technology, Inc. | Utilization of disappearing silicon hard mask for fabrication of semiconductor structures |
JP4129971B2 (en) | 2000-12-01 | 2008-08-06 | 新光電気工業株式会社 | Wiring board manufacturing method |
KR100393968B1 (en) * | 2000-12-29 | 2003-08-06 | 주식회사 하이닉스반도체 | method for forming dual damascene of semiconductor device |
JP2002217287A (en) | 2001-01-17 | 2002-08-02 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
JP2002231945A (en) * | 2001-02-06 | 2002-08-16 | Denso Corp | Method of manufacturing semiconductor device |
US6537908B2 (en) * | 2001-02-28 | 2003-03-25 | International Business Machines Corporation | Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask |
US6803314B2 (en) | 2001-04-30 | 2004-10-12 | Chartered Semiconductor Manufacturing Ltd. | Double-layered low dielectric constant dielectric dual damascene method |
KR100395907B1 (en) * | 2001-05-17 | 2003-08-27 | 주식회사 하이닉스반도체 | Method for forming the line of semiconductor device |
US6723639B1 (en) * | 2001-05-24 | 2004-04-20 | Taiwan Semiconductor Manufacturing Company | Prevention of post CMP defects in Cu/FSG process |
US7224063B2 (en) | 2001-06-01 | 2007-05-29 | International Business Machines Corporation | Dual-damascene metallization interconnection |
US6696222B2 (en) * | 2001-07-24 | 2004-02-24 | Silicon Integrated Systems Corp. | Dual damascene process using metal hard mask |
US6762127B2 (en) | 2001-08-23 | 2004-07-13 | Yves Pierre Boiteux | Etch process for dielectric materials comprising oxidized organo silane materials |
US20030213617A1 (en) * | 2002-05-20 | 2003-11-20 | Subramanian Karthikeyan | Method and structure of a reducing intra-level and inter-level capacitance of a semiconductor device |
US6488509B1 (en) | 2002-01-23 | 2002-12-03 | Taiwan Semiconductor Manufacturing Company | Plug filling for dual-damascene process |
US6541397B1 (en) * | 2002-03-29 | 2003-04-01 | Applied Materials, Inc. | Removable amorphous carbon CMP stop |
US7038239B2 (en) | 2002-04-09 | 2006-05-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
JP3989761B2 (en) | 2002-04-09 | 2007-10-10 | 株式会社半導体エネルギー研究所 | Semiconductor display device |
JP4463493B2 (en) | 2002-04-15 | 2010-05-19 | 株式会社半導体エネルギー研究所 | Display device and manufacturing method thereof |
JP3989763B2 (en) | 2002-04-15 | 2007-10-10 | 株式会社半導体エネルギー研究所 | Semiconductor display device |
JP3944838B2 (en) * | 2002-05-08 | 2007-07-18 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
US7256421B2 (en) | 2002-05-17 | 2007-08-14 | Semiconductor Energy Laboratory, Co., Ltd. | Display device having a structure for preventing the deterioration of a light emitting device |
US7253112B2 (en) | 2002-06-04 | 2007-08-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual damascene process |
KR20040009751A (en) * | 2002-07-25 | 2004-01-31 | 동부전자 주식회사 | Method for forming damascene pattern in semiconductor device |
US20040132280A1 (en) * | 2002-07-26 | 2004-07-08 | Dongbu Electronics Co. Ltd. | Method of forming metal wiring in a semiconductor device |
GB2394879B (en) * | 2002-11-04 | 2005-11-23 | Electrolux Outdoor Prod Ltd | Trimmer |
US6917109B2 (en) * | 2002-11-15 | 2005-07-12 | United Micorelectronics, Corp. | Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device |
US7449407B2 (en) * | 2002-11-15 | 2008-11-11 | United Microelectronics Corporation | Air gap for dual damascene applications |
US7138329B2 (en) * | 2002-11-15 | 2006-11-21 | United Microelectronics Corporation | Air gap for tungsten/aluminum plug applications |
US6939761B2 (en) * | 2002-11-22 | 2005-09-06 | Micron Technology, Inc. | Methods of forming buried bit line DRAM circuitry |
US6995085B2 (en) * | 2003-01-17 | 2006-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Underlayer protection for the dual damascene etching |
US7279410B1 (en) * | 2003-03-05 | 2007-10-09 | Advanced Micro Devices, Inc. | Method for forming inlaid structures for IC interconnections |
KR100515058B1 (en) * | 2003-03-31 | 2005-09-14 | 삼성전자주식회사 | Methods of forming semiconductor device having metal patterns |
US7220665B2 (en) * | 2003-08-05 | 2007-05-22 | Micron Technology, Inc. | H2 plasma treatment |
US6875688B1 (en) * | 2004-05-18 | 2005-04-05 | International Business Machines Corporation | Method for reactive ion etch processing of a dual damascene structure |
CA2568795A1 (en) * | 2004-06-09 | 2005-12-22 | Schott Ag | Building up diffractive optics by structured glass coating |
US7223684B2 (en) * | 2004-07-14 | 2007-05-29 | International Business Machines Corporation | Dual damascene wiring and method |
KR100621630B1 (en) * | 2004-08-25 | 2006-09-19 | 삼성전자주식회사 | Damascene processs using metals of two kinds |
US20060094612A1 (en) * | 2004-11-04 | 2006-05-04 | Mayumi Kimura | Post etch cleaning composition for use with substrates having aluminum |
KR100641553B1 (en) * | 2004-12-23 | 2006-11-01 | 동부일렉트로닉스 주식회사 | Method for forming pattern of a layer in semiconductor device |
US20070082477A1 (en) * | 2005-10-06 | 2007-04-12 | Applied Materials, Inc. | Integrated circuit fabricating techniques employing sacrificial liners |
US7514365B2 (en) * | 2005-11-16 | 2009-04-07 | United Microelectronics Corp. | Method of fabricating opening and plug |
KR100798738B1 (en) * | 2006-09-28 | 2008-01-29 | 주식회사 하이닉스반도체 | Method for fabricating fine pattern in semiconductor device |
DE102007005140B4 (en) * | 2007-02-01 | 2010-05-06 | Infineon Technologies Austria Ag | Method for producing a component structure with a dielectric layer and method for producing a trench in a semiconductor body |
US20080254233A1 (en) * | 2007-04-10 | 2008-10-16 | Kwangduk Douglas Lee | Plasma-induced charge damage control for plasma enhanced chemical vapor deposition processes |
US8793866B1 (en) * | 2007-12-19 | 2014-08-05 | Western Digital (Fremont), Llc | Method for providing a perpendicular magnetic recording head |
JP2009182181A (en) * | 2008-01-31 | 2009-08-13 | Toshiba Corp | Semiconductor device |
US8166632B1 (en) | 2008-03-28 | 2012-05-01 | Western Digital (Fremont), Llc | Method for providing a perpendicular magnetic recording (PMR) transducer |
US7863176B2 (en) * | 2008-05-13 | 2011-01-04 | Micron Technology, Inc. | Low-resistance interconnects and methods of making same |
US8173505B2 (en) * | 2008-10-20 | 2012-05-08 | Freescale Semiconductor, Inc. | Method of making a split gate memory cell |
US8277674B2 (en) * | 2009-12-15 | 2012-10-02 | United Microelectronics Corp. | Method of removing post-etch residues |
TWI479549B (en) * | 2009-12-16 | 2015-04-01 | United Microelectronics Corp | Method of removing post-etch residues |
US8962493B2 (en) * | 2010-12-13 | 2015-02-24 | Crocus Technology Inc. | Magnetic random access memory cells having improved size and shape characteristics |
US9064850B2 (en) * | 2012-11-15 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate via formation with improved topography control |
RU2523064C1 (en) * | 2013-01-23 | 2014-07-20 | Открытое акционерное общество "Научно-исследовательский институт молекулярной электроники" (ОАО "НИИМЭ"), Российская Федерация | Forming of multilevel copper interconnections of micro ic with application of tungsten rigid mask |
RU2548523C1 (en) * | 2013-12-17 | 2015-04-20 | Акционерное общество "Научно-исследовательский институт молекулярной электроники (АО "НИИМЭ") | Method for manufacturing of multilevel copper metallisation with ultralow value of dielectric constant for intralayer insulation |
US8980727B1 (en) * | 2014-05-07 | 2015-03-17 | Applied Materials, Inc. | Substrate patterning using hybrid laser scribing and plasma etching processing schemes |
US9543248B2 (en) | 2015-01-21 | 2017-01-10 | Qualcomm Incorporated | Integrated circuit devices and methods |
US10510657B2 (en) * | 2017-09-26 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with interconnecting structure and method for manufacturing the same |
JP2019160922A (en) | 2018-03-09 | 2019-09-19 | 東芝メモリ株式会社 | Semiconductor device |
US10644099B1 (en) | 2018-10-24 | 2020-05-05 | Globalfoundries Inc. | Three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) and method |
US11088068B2 (en) * | 2019-04-29 | 2021-08-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of manufacturing the same |
US20210375672A1 (en) * | 2020-05-27 | 2021-12-02 | Taiwan Semiconductor Manfacturing Co., Ltd. | Redistribution Lines Having Nano Columns and Method Forming Same |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4472240A (en) * | 1981-08-21 | 1984-09-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing semiconductor device |
EP0224013A2 (en) * | 1985-10-28 | 1987-06-03 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate |
US4801350A (en) * | 1986-12-29 | 1989-01-31 | Motorola, Inc. | Method for obtaining submicron features from optical lithography technology |
US4996167A (en) * | 1990-06-29 | 1991-02-26 | At&T Bell Laboratories | Method of making electrical contacts to gate structures in integrated circuits |
EP0425787A2 (en) * | 1989-10-31 | 1991-05-08 | International Business Machines Corporation | Method for fabricating high circuit density, self-aligned metal lines to contact windows |
EP0435187A2 (en) * | 1989-12-26 | 1991-07-03 | Fujitsu Limited | Method of fabricating a semiconductor device |
EP0463972A1 (en) * | 1990-06-28 | 1992-01-02 | Commissariat A L'energie Atomique | Method of making an electric contact on an active element of an MIS integrated circuit |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3961414A (en) * | 1972-06-09 | 1976-06-08 | International Business Machines Corporation | Semiconductor structure having metallization inlaid in insulating layers and method for making same |
US3844831A (en) * | 1972-10-27 | 1974-10-29 | Ibm | Forming a compact multilevel interconnection metallurgy system for semi-conductor devices |
GB8316476D0 (en) * | 1983-06-16 | 1983-07-20 | Plessey Co Plc | Producing layered structure |
US4764484A (en) * | 1987-10-08 | 1988-08-16 | Standard Microsystems Corporation | Method for fabricating self-aligned, conformal metallization of semiconductor wafer |
US4948755A (en) * | 1987-10-08 | 1990-08-14 | Standard Microsystems Corporation | Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition |
US5055423A (en) * | 1987-12-28 | 1991-10-08 | Texas Instruments Incorporated | Planarized selective tungsten metallization system |
US4933303A (en) * | 1989-07-25 | 1990-06-12 | Standard Microsystems Corporation | Method of making self-aligned tungsten interconnection in an integrated circuit |
FR2663784B1 (en) * | 1990-06-26 | 1997-01-31 | Commissariat Energie Atomique | PROCESS FOR PRODUCING A STAGE OF AN INTEGRATED CIRCUIT. |
US5093279A (en) * | 1991-02-01 | 1992-03-03 | International Business Machines Corporation | Laser ablation damascene process |
US5262354A (en) * | 1992-02-26 | 1993-11-16 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5470788A (en) * | 1994-02-28 | 1995-11-28 | International Business Machines Corporation | Method of making self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration |
-
1994
- 1994-10-11 US US08/320,516 patent/US5635423A/en not_active Expired - Lifetime
-
1995
- 1995-04-01 TW TW084103212A patent/TW293149B/zh active
- 1995-09-25 EP EP95935091A patent/EP0761014B1/en not_active Expired - Lifetime
- 1995-09-25 WO PCT/US1995/012194 patent/WO1996012297A2/en active IP Right Grant
- 1995-09-25 DE DE69531244T patent/DE69531244T2/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4472240A (en) * | 1981-08-21 | 1984-09-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing semiconductor device |
EP0224013A2 (en) * | 1985-10-28 | 1987-06-03 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate |
US4801350A (en) * | 1986-12-29 | 1989-01-31 | Motorola, Inc. | Method for obtaining submicron features from optical lithography technology |
EP0425787A2 (en) * | 1989-10-31 | 1991-05-08 | International Business Machines Corporation | Method for fabricating high circuit density, self-aligned metal lines to contact windows |
EP0435187A2 (en) * | 1989-12-26 | 1991-07-03 | Fujitsu Limited | Method of fabricating a semiconductor device |
EP0463972A1 (en) * | 1990-06-28 | 1992-01-02 | Commissariat A L'energie Atomique | Method of making an electric contact on an active element of an MIS integrated circuit |
US4996167A (en) * | 1990-06-29 | 1991-02-26 | At&T Bell Laboratories | Method of making electrical contacts to gate structures in integrated circuits |
Non-Patent Citations (2)
Title |
---|
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 30, no. 8, January 1988, NEW YORK US, pages 252-253, XP000097503 ANONYMOUS: "Methods of forming small contact holes" * |
PROCEEDINGS OF THE 8TH INT. IEEE VLSI MULTILEVEL INTERCONNECTION CONF., SANTA CLARA, CA, USA, JUNE 11-12, 1991, pages 144-152, XP002002163 KAANTA ET AL: "Dual damascene : a ULSI wiring technology" cited in the application * |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0766303A2 (en) * | 1995-09-29 | 1997-04-02 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having wiring groove and contact hole formed in self-alignment manner and method of fabricating the same |
EP0766303A3 (en) * | 1995-09-29 | 1997-04-23 | Toshiba Kk | |
US6163067A (en) * | 1995-09-29 | 2000-12-19 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having wiring groove and contact hole in self-alignment manner |
US5976972A (en) * | 1995-09-29 | 1999-11-02 | Kabushiki Kaisha Toshiba | Method of making semiconductor apparatus having wiring groove and contact hole formed in a self-alignment manner |
DE19700868C2 (en) * | 1996-05-16 | 2003-08-14 | Lg Semicon Co Ltd | Method of making connections in a semiconductor device |
US5726100A (en) * | 1996-06-27 | 1998-03-10 | Micron Technology, Inc. | Method of forming contact vias and interconnect channels in a dielectric layer stack with a single mask |
FR2754391A1 (en) * | 1996-10-08 | 1998-04-10 | Sgs Thomson Microelectronics | Increased shape form factor structure for integrated circuit |
US7112528B2 (en) | 1996-12-30 | 2006-09-26 | Applied Materials, Inc. | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
US6537905B1 (en) | 1996-12-30 | 2003-03-25 | Applied Materials, Inc. | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
GB2325083B (en) * | 1997-05-09 | 1999-04-14 | United Microelectronics Corp | A dual damascene process |
NL1006162C2 (en) * | 1997-05-09 | 1998-12-01 | United Microelectronics Corp | Method for manufacturing an integrated circuit with conductor structures. |
FR2763424A1 (en) * | 1997-05-09 | 1998-11-20 | United Microelectronics Corp | Dual damascene process for integrated circuits |
GB2325083A (en) * | 1997-05-09 | 1998-11-11 | United Microelectronics Corp | A dual damascene process |
WO1999000839A1 (en) * | 1997-06-26 | 1999-01-07 | Advanced Micro Devices, Inc. | Dual damascene etch process |
US6143476A (en) * | 1997-12-12 | 2000-11-07 | Applied Materials Inc | Method for high temperature etching of patterned layers using an organic mask stack |
US6080529A (en) * | 1997-12-12 | 2000-06-27 | Applied Materials, Inc. | Method of etching patterned layers useful as masking during subsequent etching or for damascene structures |
US6458516B1 (en) | 1997-12-12 | 2002-10-01 | Applied Materials Inc. | Method of etching dielectric layers using a removable hardmask |
US6331380B1 (en) | 1997-12-12 | 2001-12-18 | Applied Materials, Inc. | Method of pattern etching a low K dielectric layer |
GB2337160B (en) * | 1998-02-13 | 2000-03-29 | United Intgrated Circuits Corp | Method of fabricating embedded dynamic random access memory |
GB2337160A (en) * | 1998-02-13 | 1999-11-10 | United Intgrated Circuits Corp | Method of forming interconnections for an embedded DRAM |
US6410425B1 (en) | 1998-04-16 | 2002-06-25 | Stmicroelectronics S.A. | Integrated circuit with stop layer and method of manufacturing the same |
EP0951067A1 (en) * | 1998-04-16 | 1999-10-20 | STMicroelectronics S.A. | Integrated circuit with etch stop layer and method of fabrication |
FR2777697A1 (en) * | 1998-04-16 | 1999-10-22 | St Microelectronics Sa | INTEGRATED CIRCUIT WITH STOP LAYER AND MANUFACTURING METHOD THEREOF |
GB2336715B (en) * | 1998-04-24 | 2000-03-15 | United Microelectronics Corp | Dual damascene structure and its manufacturing method |
GB2336715A (en) * | 1998-04-24 | 1999-10-27 | United Microelectronics Corp | Dual damascene structure and manufacturing methods. |
GB2340657B (en) * | 1998-06-10 | 2000-07-05 | United Microelectronics Corp | Dual damascene technique |
GB2340657A (en) * | 1998-06-10 | 2000-02-23 | United Microelectronics Corp | Dual damascene technique |
GB2340302A (en) * | 1998-07-29 | 2000-02-16 | United Microelectronics Corp | Dual damascene process |
GB2340302B (en) * | 1998-07-29 | 2000-07-26 | United Microelectronics Corp | Method of manufacture using dual damascene process |
GB2356974A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
DE10200428A1 (en) * | 2002-01-09 | 2003-04-30 | Infineon Technologies Ag | Production of contact structures in a metallizing on a semiconductor wafer comprises preparing a wafer having an active region, applying a first insulating layer on the wafer |
Also Published As
Publication number | Publication date |
---|---|
US5635423A (en) | 1997-06-03 |
WO1996012297A3 (en) | 1996-07-25 |
TW293149B (en) | 1996-12-11 |
DE69531244T2 (en) | 2004-04-15 |
DE69531244D1 (en) | 2003-08-14 |
EP0761014B1 (en) | 2003-07-09 |
EP0761014A1 (en) | 1997-03-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5635423A (en) | Simplified dual damascene process for multi-level metallization and interconnection structure | |
US6627539B1 (en) | Method of forming dual-damascene interconnect structures employing low-k dielectric materials | |
US6245663B1 (en) | IC interconnect structures and methods for making same | |
US6465888B2 (en) | Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene | |
US5736457A (en) | Method of making a damascene metallization | |
US6071809A (en) | Methods for forming high-performing dual-damascene interconnect structures | |
US6143641A (en) | Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures | |
US6309957B1 (en) | Method of low-K/copper dual damascene | |
US6153521A (en) | Metallized interconnection structure and method of making the same | |
US6150269A (en) | Copper interconnect patterning | |
JPH11168105A (en) | Manufacture of semiconductor integrated circuit | |
US6191484B1 (en) | Method of forming planarized multilevel metallization in an integrated circuit | |
US6191025B1 (en) | Method of fabricating a damascene structure for copper medullization | |
US6380078B1 (en) | Method for fabrication of damascene interconnects and related structures | |
US6066560A (en) | Non-linear circuit elements on integrated circuits | |
JP2003179136A (en) | Mask layer and interconnection structure for manufacturing dual damascene semiconductor | |
US6426558B1 (en) | Metallurgy for semiconductor devices | |
US6501180B1 (en) | Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures | |
US6319859B1 (en) | Borderless vias with HSQ gap filled metal patterns having high etching resistance | |
US6319820B1 (en) | Fabrication method for dual damascene structure | |
US6350695B1 (en) | Pillar process for copper interconnect scheme | |
US6204096B1 (en) | Method for reducing critical dimension of dual damascene process using spin-on-glass process | |
US6261960B1 (en) | High density contacts having rectangular cross-section for dual damascene applications | |
US20020173079A1 (en) | Dual damascene integration scheme using a bilayer interlevel dielectric | |
US6511904B1 (en) | Reverse mask and nitride layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1995935091 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1995935091 Country of ref document: EP |
|
WWG | Wipo information: grant in national office |
Ref document number: 1995935091 Country of ref document: EP |