WO1996015550A1

WO1996015550A1 - Silicon-germanium-carbon compositions and processes thereof

Info

Publication number: WO1996015550A1
Application number: PCT/US1995/013883
Authority: WO
Inventors: Mcdonald Robinson; Richard C. Westhoff; Charles E. Hunt; Li Ling; Ziv Atzmon
Original assignee: Lawrence Semiconductor Research Laboratory, Inc.
Priority date: 1994-11-10
Filing date: 1995-10-26
Publication date: 1996-05-23
Also published as: US5906708A; US5961877A; EP0799495A4; EP0799495A1; US20020081861A1; US6064081A

Abstract

Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e. Si-Ge-C), methods for growing Si-Ge-C epitaxial layers(s) (42) on a substrate (32), etchants especially suitable for Si-Ge-C etch-stops (42), and novel method of use for Si-Ge-C compositions are provided. In particular, the invention relates to Si-Ge-C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.

Description

SILICON-GERMANIUM-CARBON COMPOSITIONS AND PROCESSES THEREOF

Background:

The present invention relates to silicon-germanium-based compositions comprising silicon, germanium, and carbon (Si-Ge-C), methods for growing Si-Ge-C epitaxial layer(s) on a substrate, etchants especially suitable for Si-Ge-C etch-stops, and novel methods of use for Si-Ge-C compositions. In particular, the present invention relates to Si-Ge-C compositions, especially for use as etch-stops, related processes and etchants useful for microelectronic and nanotechnology fabrication. In etching we remove a film or layer from a substrate, in some instances defining the layer to be removed by photolithography. One way to etch is to immerse the substrate in a bath of some chemical that attacks the fim. Preferably, the chemical should react with and etch the film or layer in a smooth and reproducible manner, producing soluble products that can be carried away from the substrate. In particular, an ideal etchant will not attack any layer underneath the film being etched, so that the etch process will be self-limiting. Unfortunately, the etching is often not self-limiting and therefore goes below the desired depth. Etch-stops are designed to address this problem.

Semiconductors have the interesting property that when they are alloyed with certain elements, the rate of wet chemical etch in the alloy will vary from that of the unalloyed semiconductor. Alloys with different etch rates can be used to cause etching to slow at a pre-defined interface. Typically, a layer with a particular composition etches at a known rate in a etchant. A second adjacent layer may etch at a different rate because it has a different composition. The layer with the lower etch rate is often referred to as the etch-stop layer.

Etch-stops are used to fabricate devices for a wide variety of applications. Membranes and diaphragms formed via etch-stops are used in sensors such as pressure transducers, as elements in experimental x-ray lithography systems, as windows for high energy radiation, and as low thermal mass supports for microcalorimeter and bolometric radiation detectors. Additional uses for selective etch-stops are in micromachining applications such as accelerometers, gears, micro-beams, miniature fluid lines, pumps and valves, and in flow sensors. Another application with a potentially large commercial market is in fabricating silicon-on-insulator (SOI) substrates by the bond-and-etch-back silicon-on-insulator (BESOI) process. Silicon-based selective chemical etch-stop layers such as Si-B, Si-Ge, Si-Ge-B, Si-P, and Si-As have major problems and disadvantages which are overcome by the present invention. The disadvantages can be illustrated by examining examples pertaining to the commonly used Si-Ge-B etch-stops. First, the specially doped layer (e.g. Si-Ge-B) and the lightly doped silicon have limited selectivity. Selectivity is defined as the etch rate of lightly doped silicon divided by the etch rate of the etch-stop layer, or in some cases its reciprocal as discussed below. Limited selectivity increases the manufacturing cost by creating a need for tightly controlled, and sometimes labor-intensive processing to prevent the etch from going beyond the intended depth. This problem is exacerbated when fabricating the thin layers that are required for submicron electronic devices. Certain chemical solutions etch a lightly doped silicon layer more rapidly than a heavily doped layer. For this purpose lightly doped means less than approximately 1E17 dopant atoms per cm³, and heavily doped means more than approximately IE 19 dopant atoms per cm³. For example, 21 weight percent (wt%) potassium hydroxide in H₂O (KOH-H.O) at about 70°C, etches the (100) plane of lightly doped silicon rapidly (approximately 1 micrometer per minute), but the etch rate becomes slow (less than 0.01 micrometer per minute), making possible selective etching, as the boron concentration in the silicon increases to more than about 5E19 atoms per cm³.

The conventional formulations of these etchants have serious problems when used with the above-mentioned etch-stop layers. For example, KOH-H₂O, an inexpensive etchant, is prone to producing a rough surface when it etches silicon. Ethylenediamine pyrocatechol in water (EDP-H₂O) provides somewhat better etch selectivity and is less prone to developing surface roughness than KOH-H₂O, but has limited application in that it emits extremely toxic vapors and is relatively expensive. Another etchant cesium hydroxide in water, (CsOH-H₂O), can provide smoother surfaces than KOH-H₂O for conventional etch-stop layers but is even more expensive than EDP-H₂O. Surface roughness arises from the anisotropic etch properties of the solutions that preferentially etch lightly doped silicon. These solutions etch certain crystallographic directions in the material faster than other directions. For example, a chemical solution consisting of 21 wt% KOH-H₂O at 70°C will rapidly etch the (100) plane of lightly doped silicon, but only slowly etch the (111) plane. This leads to the etched surface being rough as illustrated in Figures 1 A-B. As shown in Figure 1 A, a solution of KOH-H₂O (11) will rapidly etch lightly doped silicon (12). If a small particle such as particle (13) adheres to the surface of the lightly doped silicon (12), the etch rate will be locally retarded under the particle (13). Slow etching planes (14) on the (111) plane will form as the particle (13) is undercut by the etch solution. This leads to the formation of a slow-etching pyramid under the particle (13). If the etch selectivity is not sufficiently high these pyramids will propagate into the etch-stop layer (15) shown in Figure 1A as peaks (16), resulting in a rough surface.

Another problem with conventional etch-stop compositions, especially those containing a high boron concentration, is they leave an insoluble staining residue on the surface of the substrate. This residue both roughens and contaminates the substrate surface. Increasing the KOH concentration of the etch solution, for example, from 21 wt% to 40 wt% will eliminate the surface staining, but also substantially decreases the etch selectivity. In contrast to the above etchants, conventional formulations of 1 :3 :8 and 1:3:12 parts by volume of HF-HNO₃-CH₃COOH (HNA) etch lightly doped silicon somewhat less rapidly than heavily doped silicon and are therefore used to preferentially remove etch-stop layers. In this case, selectivity is defined as the etch rate of etch-stop layer divided by the etch rate of the lightly doped silicon. The above formulations of HNA have major drawbacks, including relatively low selectivity, and selectivity decreasing rapidly with time during etching due to reduction of the HNO₃ to HNO₂.

Still another problem with conventional etch-stop compositions is that the impurity which provides the etch selectivity is also a donor or acceptor dopant in the silicon. Thus, for example, when a Si-Ge-B etch-stop is used to fabricate a BESOI substrate, boron diffusing out from the etch-stop layer during a bonding anneal causes unwanted electrically active dopant in the device layer. This problem is illustrated in Figures 2 A-B which show concentration profiles of boron and germanium as a function of depth in a substrate layer, an etch-stop layer, and a device layer, before a bonding anneal (Figure 2 A) and after the anneal (Figure 2B). Figure 2 A illustrates the boron (21) and germanium (22) concentration profiles in the substrate (23), the etch-stop layer (24), and in the device layer (25) after epitaxial layer growth and before the bonding anneal. Figure 2B shows the changed boron (26) and germanium (27) concentration profiles after the bonding anneal. Because boron diffuses through the material faster than germanium during the bonding anneal, its profile is broadened such that significant "diffusion tails" extend from the etch-stop layer into the substrate (23) and the device layer (25). In a BESOI structure the boron diffusion tail causes an unacceptable level of electrically active dopant to exist in the device layer (25).

There are reports in the literature of Si-Ge-C layer fabrication. However, to the best of applicants' knowledge, none of the existing processes for forming Si-Ge-C are suitable for producing Si-Ge-C layers as part of a large scale manufacturing process. Feijόo et al., Etch Stop Barriers in Silicon Produced by Ion Implantation of Electrically Non-Active Species, Journal of the Electrochemical Society (1992) describe silicon layers implanted with silicon, germanium, and carbon at doses between 1E14 and 3E16 ions/cm² and energies between 35 and 200 keV and testing them as etch-stop barriers in an EDP-H₂O based solution (p. 2309, Abstract). When ions are implanted in this range of dose and energies, the lattice structure is damaged. Feijόo states the results obtained indicate that the effectiveness of the etch-stop is influenced (i.e. improved) by both the implantation damage and the chemical interaction between the implanted ions and the defective crystal (Abstract). The resulting damage greatly restricts the number of useful commercial applications for Feijόo's etch-stop barriers. Accordingly, Feijόo's methods and results are substantially different from the present invention. U.S. Patent No. 4,885,614 to Furukawa et al., Semiconductor Device with Crystalline Silicon-Germanium-Carbon Allov. describes another process of producing a silicon-germanium-carbon alloy film principally by molecular beam epitaxy, but also by plasma enhanced chemical vapor deposition (CVD), photoenhanced CVD, microwave excited CVD, thermal CVD and metal-organic chemical vapor deposition methods. Molecular beam epitaxy (MBE) might provide good crystalline quality but is a slow and expensive process. With regard to a description of the thermal CVD process (col. 10, lines 37-43) Furukawa describes that the surface of a silicon substrate was cleaned and the temperature thereof adjusted to 650°C. Gaseous SiH4, GeH₄ and CH₄ were allegedly introduced into a reactor so as to give a total pressure of 100 torr. Thus, a Si-Ge-C alloy film was purportedly formed on the substrate by a thermal CVD method. However, applicants believe methane at the stated process temperature is far too stable to fiinction as a carbon source for thermal CVD formation of the silicon-germanium-carbon film. Further, Furukawa et al. do not recognize or discuss the use of Si-Ge-C as an etch-stop.

Regolini et al., Growth and characterization of strain compensated Si_1-x-yGe_xC_y epitaxial layers Materials Letters (1993) describe metal-organic chemical vapor deposition (MOCVD) for fabricating epitaxial Si-Ge-C layers with less than 1 atomic percent carbon, which is far less than desirable for etch-stops. Further, there is no mention in the Regolini et al. publication of using Si-Ge-C as an etch-stop.

Summary of Invention:

This invention describes a silicon-based etch-stop which is composed of an alloy containing silicon, germanium and carbon (Si-Ge-C). In one embodiment, this alloy demonstrates etch selectivity of 8000 to 1 compared with lightly doped silicon. High etch selectivity is demonstrated for both the case in which the Si-Ge-C epitaxial layer acts as the etch-stop, and for the opposite case in which the Si-Ge-C layer is preferentially removed. This invention further describes a method by which the etch-stop layer is grown epitaxially and with excellent crystal quality by CVD onto a silicon substrate. One or more high quality, undoped or deliberately doped epitaxial silicon-based layers can be grown before and/or after the etch-stop layer. This invention further describes an innovative range of etch solution compositions which, combined with the unique composition of the etch-stop layer, enhance the selectivity for removal of the etch-stop layer by more than two orders of magnitude over previous processes for etch-stop layer removal, and compared with previous formulations, provide an etch rate which varies far less with time. Further advantages will be apparent from the following description of the preferred embodiments.

Brief Description of the Drawings:

Figures 1A-B are cross-sections illustrating surface roughness of conventional etch-stop layers.

Figures 2A-B are graphs illustrating the dopant diffusion tail that is common with conventional etch-stop layers.

Figure 3 is a perspective view illustrating a SOI substrate.

Figures 4A-F are cross-sections illustrating a BESOI process using an etch-stop layer.

Figures 5A-B are cross-sections illustrating reduced surface roughness with a Si-Ge-C etch-stop layer.

Figures 6 A-B are graphs illustrating the absence of an electrically active dopant tail with a Si-Ge-C etch-stop layer.

Figures 7A-F are ball-and-stick representations of crystal structure illustrating the effect of carbon and germanium atoms on stress in silicon alloys.

Figure 8 is a graph illustrating the superior etch selectivity of Si-Ge-C in KOH-H₂O compared with Si-Ge-B. Figure 9 is a graph illustrating the superior etch selectivity of Si-Ge-C in HNA compared with Si-Ge-B.

Figures 10A-C are cross-sections illustrating a process for making a membrane using an etch-stop layer Figures 11A-C are cross-sections illustrating a process for making a cantilever beam using an etch-stop layer.

Figure 11D is a perspective view illustrating the cantilever beam formed using the process of Figures 11A-C.

Detailed Description of the Preferred Embodiments:

Example: BESOI Fabrication: One important application of the present invention is in fabricating BESOI substrates. BESOI is used for advanced integrated circuit applications in which the device semiconductor layer (31) shown in Figure 3 is isolated from the base wafer (32) by an insulating layer (33). The following description illustrates advantages of the invention. An embodiment of a BESOI process is illustrated in Figures 4A-F. As shown in Figure 4 A, BESOI fabrication starts with two substrates, a base wafer (32) of a silicon wafer which can be either a lightly or heavily doped silicon wafer doped with either P-type or N-type dopant, such as boron or phosphorous, and a device wafer (41) of lightly doped silicon wafer of either of the same P-type or N-type dopants, and preferably a P-type dopant, such as boron. A Si-Ge-C layer (42) is grown epitaxially onto the device wafer (41), and a device epitaxial silicon layer (31) is grown epitaxially onto the Si-Ge-C layer. The Si-Ge-C layer (42) is 50-500 nm thick, is preferably 75-200 nm thick, and is most preferably about 100 nm thick. The Si-Ge-C layer (42) includes 2-6 atomic percent carbon, preferably 4-5 atomic percent carbon, and most preferably about 4.5 atomic percent carbon, and includes 18-65 atomic percent germanium, preferably 35-50 atomic percent germanium, and most preferably about 40 atomic percent germanium. The device silicon epitaxial layer (31) is 500-2000 nm thick, is preferably 100-150 nm thick, and is most preferably about 120 nm thick, and contains electrically active dopant of the P-type or N-type in the range of 1E13-1E19 atoms per cm³, preferably 1E14-1E18 atoms per cm³, and most preferably about 1E15 atoms per cm³.

In the next step, thermal oxide layers (43, 44) shown in Figure 4B are grown by a conventional technique such as exposing the surface of either one or preferably both of the wafers (32, 41) to water vapor at 800-1000°C for about 5-300 minutes. W. S. Ruska, Microelectronic Processing (1987) describes such conventional techniques and is hereby incorporated by reference in its entirety. The base wafer oxide layer (43) thickness is 50-1000 nm, preferably 100-500 nm, and most preferably about 200-300 nm. The device wafer oxide (44) thickness is 20-100 nm, preferably 40-70 run, and most preferably about 50-60 nm. The oxide layer thickness is preferably less on the device wafer (41) than on the base wafer (32) so that the thermal oxidation step will not diffuse or precipitate the carbon out of the Si-Ge-C layer. The next step is to invert the device wafer (41) and to bond it to the base wafer (32) by contacting the respective oxide surfaces (44, 43) firmly together to form an oxide layer (33) as shown in Figure 4C.

Figure 4D illustrates that in the next step most of the device wafer (41) is removed by lapping or grinding, and optionally polished by a conventional technique to form a sacrificial silicon layer (43). The thinning is preferably stopped when approximately 10 to 50 micrometers of the sacrificial layer (43) remains over the etch-stop layer (42).

Figure 4E illustrates the structure after the first selective etch step in which the final 10 to 50 micrometers of the sacrificial layer (43) is removed using a chemical solution such as 10 to 45 wt% and preferably 21 wt% KOH-H₂O, and in a temperature range of from 50 to 100°C, and preferably at about 70°C, which will etch the sacrificial layer (43), but will substantially stop etching when it reaches the etch-stop layer (42). Figure 4F illustrates the result of the final etch step in which the etch-stop layer (42) shown in Figure 4E is removed using a chemical solution such as HNA at room temperature which etches the Si-Ge-C layer rapidly, but essentially stops etching when it reaches the lightly doped epitaxial device layer (31). The final structure, shown also in Figure 3, is the lightly doped epitaxial device layer (31) separated from the substrate (32) by the insulating oxide (33).

Figures 5 A-B illustrate how the present invention solves the surface roughness problem involved in BESOI processing by the conventional method shown in Figure 1B. Figure 5A again shows a solution of KOH-H₂O (11) will rapidly etch lightly doped silicon (12). Again if a small particle (13) adheres to the surface of the lightly doped silicon (12), the etch rate is locally retarded under the particle (13), and the slow etching planes (14) on the (111) plane form as the particle (13) is undercut by the etch solution. However, in the present invention, the resulting pyramidal defect will no longer propagate into the etch-stop layer (15) because of the improved selectivity of the etch-stop layer. As shown in Figure 5B, the surface roughness (51) is substantially reduced when the etch front reaches the etch-stop layer (15) due to the pyramidal defects being substantially etched away before the etch front significantly proceeds into the etch-stop layer (15).

Chemical vapor deposition of an epitaxial Si-Ge-C laver on silicon:

One aspect of the present invention is that we have discovered a method to grow Si-Ge-C layers epitaxially by a commercially viable CVD method onto silicon at temperatures that are low enough to "quench" carbon into the epitaxial layer. Low temperature is important because whereas the germanium-silicon system exhibits complete solid solubility, carbon is nearly insoluble in silicon. The maximum solubility of carbon in silicon is about 1 part per million at the melting point of silicon. Thus, to incorporate several atomic percent carbon into silicon the epitaxial layer growth takes place at a low enough temperature so that the carbon atoms are essentially immobile in the silicon lattice. In practice the growth temperature is preferably less than about 800°C. Numerous publications on the CVD growth of silicon carbide suggest that for most hydrocarbon gases a growth temperature greater than 1100°C is required to decompose the hydrocarbon precursor gases to supply a gas source of carbon. In the present invention, we discovered that cyclopropane or ethylene can provide a source of carbon that is sufficiently reactive to deposit carbon-containing layers in a CVD process at temperatures as low as 600°C.

We have further discovered that certain novel processes significantly improve the ability to grow high quality Si-Ge-C layers. For example, the following process produces Si-Ge-C epitaxial layers with 42 atomic percent germanium, 5 atomic percent carbon, and a low defect density. A lightly doped, P-type (100) 200 mm diameter prime silicon substrate is cleaned and loaded into a CVD reactor using a robotic transfer arm. A suitable reactor for this application is an Epsilon One, Model E-2, manufactured by ASM America, Phoenix Arizona. Initially, the reactor temperature is held in the range from 25-900°C, preferably 800-900°C, and most preferably about 850°C. Hydrogen gas is introduced into the reactor at preferably atmospheric pressure, or at reduced pressure of, for example, 5-100 torr, at a flow rate of 10-100 standard liters per minute (slm), preferably 15-40 slm, most preferably about 20 slm. Next, the substrate is heated to 1000-1200°C, preferably to 1100-1190°C, and most preferably to about 1150°C. The reactor is most preferably held at about 1150°C for 30 to 600 seconds, preferably 60 to 300 seconds, and most preferably about 90 seconds to remove the native oxide layer from the substrate. The substrate is then cooled to 900ºC in the H₂ atmosphere before the deposition of silicon. At 900°C, 5 to 200 standard cubic centimeters per minute (seem), preferably 10 to 50 seem, and most preferably about 20 seem of SiH₂Cl₂ (dichlorosilane) is introduced into the reactor atmosphere to initiate deposition of the undoped or lightly doped epitaxial silicon. Deposition continues as the substrate is cooled further, and at 700°C a low flowrate (e.g., 0.1 sccm) of GeH₄ (germane) is added to the deposition atmosphere. The substrate is cooled still further, and at 550-750°C, preferably 600-700°C, and most preferably about 625°C the low flowrate of GeH₄ is increased over a span of 15 seconds to a final flowrate of from 1.0 to 20.0 seem, preferably 1.4 to 5.0 seem, and most preferably about 1.8 seem. Just as the GeH₄ flowrate reaches its final value, C₃H₆ (cyclopropane) is added at a low flowrate (e.g. 25 seem) to the deposition atmosphere. The low flowrate of cyclopropane is increased over a span of 15 seconds to a final flowrate of from 50 to 200 seem, preferably 75 to 150 seem, and most preferably about 100 seem. All final gas flowrates are then held constant for 1 to 100 minutes, preferably 5 to 10 minutes, and most preferably about 6.5 minutes while a Si-Ge-C layer of approximately 200 nm thickness is grown. Following deposition the reactor is purged with 20 slm of pure H₂ for about 45 seconds. Afterward the robotic transfer arm removes the substrate from the reactor. In an alternative embodiment, an alkene, such as ethylene can be substituted for cyclopropane in a similar process.

The reasons for the above process improvements are as follows. The surface of silicon forms a tenacious silicon dioxide (SiO₂) when exposed to air. This oxide is removed from silicon during heating in hydrogen to high temperature such as 1150°C, but the oxide tends to reform when the silicon surface is exposed to trace amounts of oxygen or water vapor at lower temperature. By starting the CVD silicon growth at 900°C, and by adding a small concentration of GeH₄ to the gas at 700°C, we prevent trace amounts of oxygen and water vapor in the deposition atmosphere from causing oxide nuclei to form as the temperature is lowered to the level that is favorable for Si-Ge-C deposition. As this protective Si-Ge layer is deposited the GeH₄ concentration is held low and ramped up quickly to keep the thickness and stress of the layer well below the critical thickness for formation of misfit dislocations. The C₃Hg flowrate is ramped from a low value to the final value for a totally different reason. In developing this process we discovered that the best crystalline quality is obtained by starting the Si-Ge-C deposition with a low concentration of hydrocarbon and then ramping the flowrate up until the desired carbon concentration is obtained. The reason may be related to the low solubility of carbon in silicon. Starting the Si-Ge-C deposition with a low surface concentration of carbon may be important in establishing a steady-state growth process in which carbon is incorporated in non-equilibrium concentrations into the silicon-germanium lattice.

An economical epitaxial layer growth process is important if the epitaxial single Si-Ge-C layers are to be used for commercial applications. As will be demonstrated in the examples which follow, the process which we discovered can be operated in a commercial CVD epitaxial reactor, at rates sufficiently high that the Si-Ge-C layers can be produced at prices comparable to present epitaxial silicon layers. A suitable reactor for this application is again the Epsilon One, Model E-2, manufactured by ASM America, Phoenix Arizona. The reactor can be configured for single wafer, automated processing using vacuum-compatible load lock ports and a nitrogen-purged robotic wafer transfer chamber. The load lock ports and the wafer transfer chamber effectively isolate the process chamber from atmospheric contamination. Evacuation of the load lock ports is important to prevent air from entering the process chamber and to remove adsorbed moisture from the surfaces of the substrates before processing. High purity materials are important for low temperature, defect-free production of epitaxial Si-Ge-C layers. Hydrogen and nitrogen liquid sources having impurity levels less than 10 parts per billion (ppb) can be obtained from Air Products & Chemicals, Inc., in Allentown, PA. Dichlorosilane gas of Ultraplus grade can be obtained from Praxair, in Kingman, AZ; and a 1:99 volume ratio and a 10:90 volume ratio of germane:hydrogen of Megabit grade can be obtained from Solkatronic Chemicals, in Fairfield, NJ. The 10:90 volume ratio of cyclopropane:helium of semiconductor grade can be obtained from Air Products & Chemicals. The hydrogen, nitrogen, germane and cyclopropane gases can be further purified by point-of-use Nanochem purifiers made by Semi-Gas Systems, in Santa Clara, CA.

Additional processes and embodiments for the formation of thin heteroepitaxial films of Si-Ge-C grown on silicon substrates using CVD and C₂H₂ gas as a carbon source at the relatively low temperature of 625°C are described in the unpublished manuscript by Z. Atzmon et al. Chemical Vapor Deposition Of Heteroepitaxial Si_1-x-yGe_xC_y Films On (100)Si Substrates (Appendix A) which entire manuscript is hereby incorporated herein by reference.

Advantages of Si-Ge-C being isoelectronic:

An additional advantage of the Si-Ge-C etch-stop over the most commonly used Si-Ge-B etch-stop is that all three components of the Si-Ge-C alloy are isoelectronic, i.e., none supplies an electrically active dopant. Thus, if there is slight diffusion of one of the elements into the silicon device layer, the electrically active dopant concentration will not be affected. Further, since germanium and carbon affect the band structure and bandgap of silicon, it will be advantageous for some applications to leave the Si-Ge-C etch-stop layer in place to become part of the device structure. Figures 6 A-B illustrate the point. Figure 6 A illustrates carbon (61) and germanium (62) concentration profiles over a substrate (63), on which an epitaxial Si-Ge-C etch-stop layer (64) and a lightly doped device layer (65) have been epitaxially grown before a bonding anneal. This structure represents the starting point for a BESOI process, which can be compared to the Si-Ge-B structure shown in Figures 2 A-B. In Figures 6 A, the boron concentration (66) is deliberately low throughout the concentration profile. The substrate (63) is shown with a boron concentration of about 1E17 atoms per cm³, and the epitaxial layers (64, 65) are grown with a boron concentration of about 2E15 atoms per cm³. Figure 6B shows the concentration profiles after the bonding anneal. The carbon (67) and boron (68) profiles broaden during the anneal due to diffusion. In contrast to the Si-Ge-B etch-stop in Figure 2B, the carbon (69) in the device layer (65) of Figure 6B does not contribute electrical carriers and the substrate boron diffusion tail (70), residing in the etch-stop layer (64), does not contribute electrical carriers to the device layer (65).

Advantages of Si-Ge-C permitting strain control:

The present invention also permits strain control in the Si-Ge-C layer. Germanium and carbon atoms both differ in size from silicon. The fourfold covalent atomic radius of germanium, is about 5% larger than silicon, whereas carbon is about 50% smaller. The effects of germanium and carbon addition to silicon are shown schematically in Figures 7A-F. In undoped silicon there is naturally occurring spacing (71) between the silicon atoms represented as solid dots in Figure 7A. When germanium atoms are added to silicon, the lattice parameter or atomic spacing (72) in the crystalline structure is increased by the larger germanium atoms represented by the large white dots in Figure 7B. By contrast when carbon atoms represented by the small grey dots are added to silicon the atomic spacing (73) is decreased as shown in Figure 7C. As shown in Figure 7D, when a Si-Ge epitaxial layer represented by the upper three rows of solid and white dots is grown onto a silicon substrate represented by the lower five rows of solid dots, a compressive in-plane stress arises as the Si-Ge layer is forced to assume the atomic spacing (71) of the unstrained silicon substrate. The Si-Ge lattice expands in a direction normal to the silicon substrate to form spacing (74) causing a tensile strain in that direction. Conversely, when a Si-C layer is grown epitaxially onto a silicon substrate, the Si-C layer is under an in-plane tensile strain and a compressive strain in the direction normal to the silicon substrate. Thus, when either a Si-Ge or a Si-C layer is grown epitaxially onto silicon the growing layer experiences a stress that increases with the thickness of the layer and with the concentration of Ge or C. At some critical thickness the stress exceeds the yield stress, the point at which dislocations nucleate at the epitaxial layer-substrate interface and propagate to form a two-dimensional defect array (75) as illustrated in Figure 7E for the case of Si-Ge. This array of misfit dislocations allows the epitaxial layer to assume its unstrained atomic spacing (72), and in doing so relieves the stress in the epitaxial layer. If, however, the epitaxial layer includes Ge and C in a ratio defined by: (atomic radius Si - atomic radius C)/(atomic radius Ge - atomic radius Si), about 9:1 Ge:C, the epitaxial layer will have similar atomic spacing (71) to undoped silicon and be free of stress as shown in Figure 7F. In this case, the epitaxial layer-substrate interface remains free of misfit dislocations. In different applications it will be advantageous to grow Si-Ge-C layers that (1) are strain-free, or (2) have strain that is grown-in to a pre-defined level, or (3) have lattice parameter misfit at so high a level as to cause misfit dislocations to form. Fabrication of a cantilever beam in an accelerometer application is an example in which the layer should be grown stress free so that the beam will not be bowed. On the other hand when a Si-Ge-C layer is to be made into a membrane, a slightly tensile stress, created by increasing the carbon-to-germanium ratio, is desirable so that the membrane will be smooth and "tight". For semiconductor devices, both strain and composition are means by which the bandgap and band structure can be varied for particular applications. At the same time it is usually important for electronic applications that the epitaxial layers, whether strained or unstrained, must be free of defects including misfit dislocations. For some mechanical applications, on the other hand, it may be desirable to create an array of misfit dislocations. Such dislocations can strengthen the silicon by a process known as "work hardening".

The above-referenced interface misfit stress can be measured in any of several ways. One is to measure the interatomic spacing of a Si-Ge-C layer grown epitaxially onto a silicon substrate, in the direction perpendicular to the substrate surface, by precision X-ray diffraction. As long as the critical stress for formation of misfit dislocations has not been exceeded, the difference in lattice parameter between the epitaxial layer and the substrate is proportional to the stress in the grown layer. Another method is to measure the bow of a silicon substrate before and after depositing the epitaxial Si-Ge-C layer. The change in bow is related by a simple formula to the stress in the Si-Ge-C layer (P. Singer, "Film Stress and How to Measure It", Semiconductor International. October 1992, p. 58, which is incorporated by reference in its entirety).

Advantages of Si-Ge-C having high etch selectivity: As Figures 8 and 9 illustrate the etch selectivity of the Si-Ge-C epitaxial layer is much higher than that of Si-Ge-B in both KOH-H₂O and HNA etch solutions. In Figure 8, the etch selectivity of Si-Ge-C in 21 wt% KOH-H₂O is plotted against carbon content in the epitaxial layer, with the etch selectivity of a Si-Ge-B layer having 1E21 atoms per cm³ of Ge and 2E20 atoms per cm³ of B is shown on the left side of Figures 8 and 9 for comparison. The germanium content of the carbon-containing etch-stop layers increases approximately in proportion to the carbon content to compensate strain, in atomic percent as follows:

Here etch selectivity in KOH-H₂O is defined as the etch rate of lightly doped silicon divided by the etch rate of the etch-stop layer. Figure 8 is a graph of the selectivity of Si-Ge-C and Si-Ge-B etch stops with respect to lightly doped silicon. A selectivity of 8000: 1 in 21 wt% KOH-H₂O at 70°C has been measured by employing black wax to mask the etch-stop layer before exposing to the etchant, measuring the resultant step in the etch-stop layer and comparing that distance against the etch depth in lightly doped silicon under the same etchant. However, it is believed that by employing a silicon nitride mask, the selectivity of the Si_0.53Ge_0.42C_0.05 etch-stop will be even higher.

In any event, the selectivity of the Si-Ge-C etch-stop is apparently higher than that of SiO₂ and is a significant improvement over Si-Ge-B which shows a maximum selectivity of 2000: 1 under the same conditions. Figure 9 compares the etch selectivity of Si-Ge-B and Si-Ge-C as a function of carbon concentration in five HNA solutions. For etch-stop removal in HNA, etch selectivity is defined as the etch rate of the etch-stop layer divided by the etch rate of lightly doped silicon. Figure 9 illustrates that in HNA solution, the selectivity of the etch-stop layer is enhanced by two innovations. The five HNA solutions are prepared from standard aqueous reagents which are as follows: 49 wt% HF, 70 wt% HNO₃, and 99 wt% CH₃OOH. First, we discovered that selectivity increases with carbon content, reaching a maximum selectivity at about 4 atomic percent carbon. Second, we discovered that selectivity increases as the HNO₃ content of the HNA solution decreases, reaching maximum selectivity of more than 800:1 with the HF:HNO₃:CH₃COOH volume ratio of 1:0.3: 12 and 4 atomic percent carbon. A further benefit of reducing the HNO₃ concentration in the HNA solution is that the solution is stable against the chemical reduction of HNO₃ to HNO₂, a problem that plagues users of the conventional 1:3:8 and 1 :3:12 HNA compositions. It is an important advantage that our etch solutions remain colorless and etch selectivity is independent of time for etch times of 30 minutes or more (1 :3:8 and 1 :3: 12 HNA solutions turn yellow and lose selectivity rapidly over the first few minutes of use). We discovered that the novel HNA formulations also will increase the etch selectivity of Si-Ge-B as the HNO₃ concentration of the solution is decreased reaching a maximum of 50.

The unique properties of the Si-Ge-C etch-stop layers combined with the new HNA etch compositions are suggested by the behavior of the Si-Ge-C surface in the etch solution. The etch solution is believed to work by simultaneously oxidizing the surface (performed by the HNO₃) and etching the oxide (performed by the HF). Si-Ge-C surfaces are hydrophilic when they emerge from the HNA solutions for all etch compositions from 1 :3 : 12 to 1 :0.1 : 12 in contrast to lightly doped Si with hydrophobic surfaces, indicating that the oxide removal performed by HF dominates the etching rate of Si-Ge-C layers.

Favorable results are believed to be obtained for etch selectivity in HNA when the silicon is in the range of 50 to 90 atomic percent, the germanium is in the range of 9 to 50 atomic percent, and the carbon is in the range of 1 to 10 atomic percent, preferably in the range of 3 to 6 atomic percent. More preferably, the Si-Ge-C is in the range for Si, Ge and C of 50-60 atomic percent, 36-45 atomic percent, and 4-5 atomic percent, respectively.

We believe that the some of useful ranges of Si-Ge-C compositions are: silicon in a range of 0 to 99.9 atomic percent, preferred 45 to 83 atomic percent, further preferred about 55.5 atomic percent, germanium in a range of 1 to 92 atomic percent, preferred 15 to 50 atomic percent, and further preferred about 40 atomic percent, and carbon in the range of 0.1 to 10 atomic percent, preferred 2 to 6 atomic percent, and further preferred about 4.5 atomic percent. Examples: Si-Ge-C Etch-Stop in Nanotechnology Applications

A. Membrane One example of silicon membrane fabrication is illustrated in Figures 10A-C. As shown in Figure 10A, Si-Ge-C layer (101) is epitaxially grown onto a lightly doped, conventional polished silicon substrate (102). Favorable results can be achieved by using the processes described earlier in the section on epitaxial growth of Si-Ge-C layers by CVD on silicon. The silicon substrate (102) and Si-Ge-C layer (101) form a structure which is inverted as shown in Figure 10B and an oxide layer (104) is formed on the back side of the silicon substrate (102). A positive photoresist (not shown) is applied to the oxide layer (104), and then exposed through openings in the mask. The exposed and developed photoresist is removed and then the underlying exposed oxide layer is removed with a conventional HF solution. The exposed portion of the back side of the silicon substrate (102) is etched by a 21 wt% KOH-H₂O etchant that rapidly removes the lightly doped silicon substrate (102) as indicated by surface ( 103) formed during an intermediate stage of the etch, but then etches at a slower rate when it reaches the Si-Ge-C (101) as shown in Figure 10C. As shown in Figure 10C, when the etching is complete the Si-Ge-C layer (101) remains as a membrane supported by a silicon substrate frame (105) defined the remaining portions of the silicon substrate (102). The carbon-to-germanium ratio in the etch-stop layer is adjusted so that the Si-Ge-C membrane (101) is preferably in tension. This ensures that the membrane (101) is "tight" and well supported by the frame (105).

B. Cantilever Beam Another example of a micromechanical application of a Si-Ge-C epitaxial etch-stop layer is in fabricating a cantilever beam as illustrated in Figures 11 A-C. In Figure 11 A, a Si-Ge-C etch-stop layer (111) and a lightly doped silicon layer (112) are grown onto a silicon substrate (113). A masking oxide (114) shown in Figure 11B is grown and patterned using a technique like that used in the membrane fabrication, and the exposed portion of the lightly doped silicon (112) is etched by a 21 wt% KOH-H₂O etchant that rapidly removes the lightly doped silicon but etches very slowly when it reaches the Si-Ge-C layer (111). Next, the Si-Ge-C layer (111) is etched by HNA that rapidly removes the exposed Si-Ge-C layer (111) as shown in Figure 11C, but only etches lightly doped silicon very slowly. In this way the cantilever beam (115) formed from the lightly doped silicon layer (112) is freed from the surrounding silicon substrate. Figure 1 ID is a perspective drawing showing the finished cantilever beam (115) attached to the rest of the lightly doped silicon layer (112) at one end. Other precision micro-miniature structures can be fabricated using processes like this.

It will be appreciated by those of ordinary skill in the art that many variations in the foregoing embodiments are possible while remaining within the scope of the present invention. Thus, the invention has applications well beyond those enumerated. The present invention should thus not be considered limited to the preferred embodiments.

CHEMICAL VAPOR DEPOSITION OF HETEROEPITAXIAL

Si_{1 -x-y}Ge_xC_y FILMS ON (100)Si SUBSTRATES

Z. Atzmon. A. E. Bair. E. J. Jaquez and J. W. Mayer

Department of Chemical. Bio. and Materials Engineering, Arizona State University, Tempe,

Arizona 85287

D. Chandrasekhar. David J. Smith and R. L. Hervig

Center of Solid State Science. Arizona State University, Tempe. Arizona 85287

McD. Robinson

Lawrence Semiconductor Research Laboratory Inc., Tempe, Arizona 85282

Thin heteroepitaxial films of Si_1-x-yGe_xC_y have been grown on (100)Si substrates using atmospheric pressure Chemical Vapor Deposition (CVD) at 625°C. The crystallinity, composition and microstructure of the SiGeC films were characterized using Rutherford backscattering specuometry, secondary-ion-mass-spectrometry and cross-sectional transmission electron microscopy. The crystallinity of the films was very sensitive to the flow rate of C₂H₂ which served as the C source. Films with up to 2% C were epitaxial with good crystallinity and very few interfacial defects. Between 800 and 900 seem of 10% C₂H₂ in He, the C content increased dramatically from 2% to 10% and the as-grown films changed from crystalline to amorphous. In order to establish deposition conditions for the crystalline-amorphous phase transformation, one SiGeC film was deposited as the 10% C₂H₂ flow was increased linearly from 500 to 1500 sccm during growth. When the C content reached -4%, the film developed considerable stacking defects and disorder, and at around 1 1 % C. the film became amorphous.

LIST OF TABLES

Table I: Sample growth conditions in CVD system.

Claims

What is claimed is:

1. An etch-stop structure, comprising:

a substrate;

one or more epitaxial layers grown sequentially, starting at the substrate, at least one of which comprises Si-Ge-C, wherein carbon is present in the Si-Ge-C layer(s) in an amount sufficient for preferential etch selectivity over the substrate and/or adjacent epitaxial layers, the Si-Ge-C layer(s) comprising:

0-99.9 atomic percent Si,

1-92 atomic percent Ge, and

0.1-10 atomic percent C.

2. The structure of claim 1, comprising:

45-83 atomic percent Si,

15-50 atomic percent Ge, and

2-5 atomic percent C.

3. The structure of claim 1, comprising:

55.5 atomic percent Si,

40 atomic percent Ge, and

4.5 atomic percent C.

4. The structure of claim 1, comprising:

28-90 atomic percent Si,

9-67 atomic percent Ge, and

1-5 atomic percent C.

5. The structure of claim 1, comprising:

60 atomic percent Si,

36 atomic percent Ge, and

4 atomic percent C.

6. The structure of claim 1, comprising:

53 atomic percent Si;

42 atomic percent Ge; and

5 atomic percent C.

7. The structure of claim 1, comprising:

70 atomic percent Si;

27 atomic percent Ge; and

3 atomic percent C.

8. A method for using Si-Ge-C as an etch-stop in conjunction with a silicon substrate, comprising:

growing one or more epitaxial layers, the first layer being grown on the substrate, wherein at least one of the epitaxial layers comprises Si-Ge-C; and

etching the one or more layers adjacent to the Si-Ge-C layer and/or the Si-Ge-C layer.

9. The method of claim 8, wherein the carbon in the Si-Ge-C layers is present in an amount sufficient for preferential etch selectivity over the one or more layers adjacent to the Si-Ge-C layer. 10. The method of claim 8, wherein the Si-Ge-C layer etches slower than the one or more adjacent epitaxial layers.

11. The method of claim 8, wherein the Si-Ge-C layer etches faster than the one or more adjacent epitaxial layers.

12. The method of claim 8, wherein the Si-Ge-C layer etches slower than the silicon substrate.

13. The method of claim 8, wherein the Si-Ge-C layer etches faster than the silicon substrate. 14. The method of claim 8, 9, 10, 11, 12, or 13, wherein the Si-Ge-C is grown on the substrate by thermal chemical vapor deposition.

15. The method of claim 8, 9, 10, 11, 12, or 13, wherein the carbon is in the range of 1 to 10 atomic percent.

16. A method for using Si-Ge-C as an etch-stop in conjunction with a silicon, germanium, or silicon-germanium substrate, comprising:

growing one or more epitaxial layers sequentially, starting at the substrate, at least one of which comprises Si-Ge-C, wherein carbon is present in the Si-Ge-C layer(s) in an amount sufficient for preferential etch selectivity over the substrate and/or adjacent epitaxial layers; and

etching the one or more layers adjacent to the Si-Ge-C layer and the Si-Ge-C layer.

17. A method for using Si-Ge-C as an etch-stop, comprising:

providing a silicon substrate; and

epitaxially growing one or more layers on the silicon substrate, wherein at least one of the epitaxial layers comprises Si-Ge-C.

18. A wet chemical etchant, comprising:

3.5 - 15.8 mole percent of HF;

0.2 - 9.7 mole percent of HNO₃;

34.8 - 82.6 mole percent of CH₃COOH; and

12.3 - 46.5 mole percent of H₂O.

19. A wet chemical etchant, comprising:

6.2 - 8.2 mole percent of HF;

0.3 - 6.9 mole percent of HNO₃;

53.8- 71.1 mole percent of CH₃COOH; and

20.4 - 33.1 mole percent of H₂O.

20. A process for making an etchant, comprising the step of mixing the following reagents:

0.5 to 2 parts by volume of 49 wt% HF;

0.1 to 3 parts by volume of 70 wt% HNO₃; and

8 to 12 parts by volume of 99 wt% CH₃COOH.

21. A process for making an etchant, comprising the step of mixing the following reagents:

6.2 - 8.2 mole percent of HF;

0.5 - 8.4 mole percent of HNO₃;

43.7 - 70.7 mole percent of CH₃COOH; and

20.7 - 40.4 mole percent of H₂O.

22. A process for making an etchant, comprising the step of mixing the following reagents:

6.8 - 8.1 mole percent HF;

0.6 - 5.0 mole percent HNO₃;

58.7 - 70.3 mole percent CH₃COOH; and

21.0 - 29.5 mole percent H₂O.

23. A process for etching a structure including one or more epitaxial layer(s) and/or a substrate, comprising:

immersing the structure, at least partially in the etchant of claim 18 or 19; and rinsing the etchant from the structure.

24. The process of claim 23, wherein the etchant is in a temperature range of 15-50°C. 25. The process of claim 16, wherein the etchant is 10-45 wt% KOH H₂O and is maintained at a temperature in the range of 50 to 100°C.

26. A process for etching a structure, comprising.

27. The process of claim 16, wherein the etchant is 21 wt% KOH-H₂O and is maintained at a temperature in the range of 50 to 100°C. 28. A process for forming epitaxial Si-Ge-C, comprising the steps of:

loading a silicon substrate in a thermal chemical vapor deposition reactor; epitaxially growing one or more layers on the silicon substrate of which one of the layers comprises Si-Ge-C; and

terminating the process. 29. The process of claim 28, further comprising:

cleaning the substrate before loading the substrate in the reactor.

30. The process of claim 28, further comprising the step of removing a native oxide layer from the substrate by immersing the substrate in dilute HF and/or baking the substrate at 850-1200°C in H₂ in the reactor.

31. The process of claim 28, further comprising:

adjusting the temperature of the reactor to a deposition temperature. 32. The process of claim 28, wherein the epitaxially growing step includes the step of supplying gaseous sources of Si, Ge, C, and H and/or B, As, P to a growing surface.

33. The process of claim 28, further comprising:

purging the gases with H₂ or an inert gas from reactor;

34. The process of claim 28, 29, 30, 31, 32, or 33, wherein the carbon source is cyclopropane or ethylene.

35. The process of claim 28, wherein the concentration of the carbon containing gas supplied to the growing surface is ramped up over time.

36. The process of claim 28, wherein the concentration of the carbon containing gas supplied to the growing surface increases linearly with respect to time. 37. A product made in accordance with the processes defined in claim 28, 29, 30, 31, 32, or 33.

38. A layered epitaxial structure, comprising:

a single crystal substrate; and

one or more epitaxial layers, the first layer being grown on the silicon substrate, of which at least one of the layers comprises Si-Ge-C, wherein the substrate and the one or more of the etch-stop layers include P-type dopant and/or N-type dopant.

39. A layered epitaxial structure, comprising:

a single crystal substrate; and

one or more epitaxial layers on the silicon substrate of which one of the layers comprises Si-Ge-C, wherein the atomic percent ratio of germanium to carbon in the Si-Ge-C layer is outside the range of 6 7 to 1 and 12 to 1

40. The layered epitaxial structure of claim 38 or 39, wherein the atomic percent of carbon is up to 10.

41. The layered epitaxial structure of claim 38 or 39, wherein the atomic percent of carbon is in the range of 1 to 10.

42. The layered epitaxial structure of claim 38 or 39, wherein the concentration of electrically active dopant in and adjacent to the Si-Ge-C layer is lightly doped.

43. The layered epitaxial structure of claim 38 or 39, wherein the concentration of electrically active dopant in and adjacent to the Si-Ge-C layer is heavily doped. 44. The layered epitaxial structure of claim 38 or 39, wherein the concentration of electrically active dopant in and adjacent to the Si-Ge-C layer is less than 1E15 atom per cm³.

45. A method of forming a silicon-on-insulator material, the method comprising the steps of: forming a carbon-silicon alloy epitaxial layer having a carbon concentration sufficient to function as an etch-stop and a germanium concentration 6.7 - 12 times larger than the carbon concentration, wherein the carbon alloy resides on a surface of a first semiconductor silicon substrate;

forming a second silicon epitaxial layer on the carbon-silicon alloy layer;

providing a first oxide layer on a surface of the second epitaxial layer;

providing a second oxide layer on a second semiconductor silicon substrate;

bringing into contact the first and second oxide layers thereby bonding together the first and second semiconductor substrates to thereby form a laminated structure;

removing most of the first silicon substrate;

exposing the laminate to an anisotropic etch for the first silicon substrate until the remainder of the first silicon substrate is removed, but only a part of the carbon-silicon alloy layer is removed; and

exposing the resultant structure to a second isotropic etch for the carbon-silicon alloy layer for a time sufficient only to remove the remainder of the carbon-silicon alloy layer thereby producing a silicon-on-insulator material.