WO1996018988A3 - Circuits, systems and methods for controlling the display of blocks of data on a display screen - Google Patents

Circuits, systems and methods for controlling the display of blocks of data on a display screen Download PDF

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Publication number
WO1996018988A3
WO1996018988A3 PCT/US1995/015847 US9515847W WO9618988A3 WO 1996018988 A3 WO1996018988 A3 WO 1996018988A3 US 9515847 W US9515847 W US 9515847W WO 9618988 A3 WO9618988 A3 WO 9618988A3
Authority
WO
WIPO (PCT)
Prior art keywords
display
data
window
circuitry
registers
Prior art date
Application number
PCT/US1995/015847
Other languages
French (fr)
Other versions
WO1996018988A2 (en
Inventor
Sudhir Sharma
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Priority to JP8519143A priority Critical patent/JPH10510634A/en
Priority to EP95944065A priority patent/EP0804785A2/en
Publication of WO1996018988A2 publication Critical patent/WO1996018988A2/en
Publication of WO1996018988A3 publication Critical patent/WO1996018988A3/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Abstract

Display control circuitry is provided which includes a frame buffer (104) having a plurality of memory spaces (301) each for storing a block of display data. Circuitry (200) is provided for generating display position data representing a position on a display screen corresponding to a current display pixel being generated. For each memory space (301), a window control circuit (201) is provided for controlling the transfer of a block of data from the given memory space (301) to a selected window on the display screen. Each window control circuit (201) includes first registers (205, 206) for storing data defining horizontal boundaries of the window, second registers (210, 211) for storing data defining vertical boundaries of the window, and circuitry (207, 208, 209, 212, 213, 214) for comparing the display position data with data stored in the first and second registers and generate an enable signal when the position on the screen of the current pixel is within the window boundaries. Memory control circuitry (300, 302) is provided for retrieving data from the memory space (301) selected in response to the enable signals received from the window control circuits (201).
PCT/US1995/015847 1994-12-06 1995-12-06 Circuits, systems and methods for controlling the display of blocks of data on a display screen WO1996018988A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8519143A JPH10510634A (en) 1994-12-06 1995-12-06 Circuit, system and method for controlling display of a block of data on a display screen
EP95944065A EP0804785A2 (en) 1994-12-06 1995-12-06 Circuits, systems and methods for controlling the display of blocks of data on a display screen

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US34989494A 1994-12-06 1994-12-06
US08/349,894 1994-12-06

Publications (2)

Publication Number Publication Date
WO1996018988A2 WO1996018988A2 (en) 1996-06-20
WO1996018988A3 true WO1996018988A3 (en) 1996-09-12

Family

ID=23374419

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/015847 WO1996018988A2 (en) 1994-12-06 1995-12-06 Circuits, systems and methods for controlling the display of blocks of data on a display screen

Country Status (5)

Country Link
US (1) US6157366A (en)
EP (1) EP0804785A2 (en)
JP (1) JPH10510634A (en)
KR (1) KR980700633A (en)
WO (1) WO1996018988A2 (en)

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* Cited by examiner, † Cited by third party
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US7292209B2 (en) * 2000-08-07 2007-11-06 Rastar Corporation System and method of driving an array of optical elements
JP2003066938A (en) * 2001-08-24 2003-03-05 Sharp Corp Display controller, display control method and image display system
US20040268207A1 (en) * 2003-05-21 2004-12-30 Engim, Inc. Systems and methods for implementing a rate converting, low-latency, low-power block interleaver
JP4342578B2 (en) * 2007-07-24 2009-10-14 株式会社エヌ・ティ・ティ・ドコモ Information processing apparatus and program

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US4649377A (en) * 1983-05-24 1987-03-10 Hitachi, Ltd. Split image display control unit
US4829294A (en) * 1986-06-25 1989-05-09 Hitachi, Ltd. Document processing method and system using multiwindow
US5121114A (en) * 1989-05-29 1992-06-09 Sharp Corporation Information processing apparatus having a specified-area confirming function

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JPS60117376A (en) * 1983-11-29 1985-06-24 Yokogawa Medical Syst Ltd Picture display device for computerized tomographic image pickup device
JPS613194A (en) * 1984-06-15 1986-01-09 株式会社東芝 Image display
US4691303A (en) * 1985-10-31 1987-09-01 Sperry Corporation Refresh system for multi-bank semiconductor memory
US4903197A (en) * 1987-02-27 1990-02-20 Bull Hn Information Systems Inc. Memory bank selection arrangement generating first bits identifying a bank of memory and second bits addressing identified bank
US5067105A (en) * 1987-11-16 1991-11-19 International Business Machines Corporation System and method for automatically configuring translation of logical addresses to a physical memory address in a computer memory system
JP2512080B2 (en) * 1988-05-06 1996-07-03 株式会社日立製作所 Display device having multi-window function
US5185597A (en) * 1988-06-29 1993-02-09 Digital Equipment Corporation Sprite cursor with edge extension and clipping
US4961071A (en) * 1988-09-23 1990-10-02 Krooss John R Apparatus for receipt and display of raster scan imagery signals in relocatable windows on a video monitor
GB8825764D0 (en) * 1988-11-03 1988-12-07 Lucas Ind Plc Computer memory addressing system
US4982345A (en) * 1989-01-23 1991-01-01 International Business Machines Corporation Interactive computer graphics display system processing method for identifying an operator selected displayed object
US5202671A (en) * 1989-10-24 1993-04-13 International Business Machines Corporation Pick function implementation in a parallel processing system
DE68925361T2 (en) * 1989-10-30 1996-07-25 Philips Electronics Nv Random access memory with page addressing mode
US5012408A (en) * 1990-03-15 1991-04-30 Digital Equipment Corporation Memory array addressing system for computer systems with multiple memory arrays
DE69122147T2 (en) * 1990-03-16 1997-01-30 Hewlett Packard Co Method and device for clipping pixels from source and target windows in a graphic system
US5159572A (en) * 1990-12-24 1992-10-27 Motorola, Inc. DRAM architecture having distributed address decoding and timing control
US5251178A (en) * 1991-03-06 1993-10-05 Childers Jimmie D Low-power integrated circuit memory
KR940002475B1 (en) * 1991-08-20 1994-03-24 삼성전자 주식회사 Display editing apparatus
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US5488390A (en) * 1993-07-29 1996-01-30 Cirrus Logic, Inc. Apparatus, systems and methods for displaying a cursor on a display screen
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US5506810A (en) * 1994-08-16 1996-04-09 Cirrus Logic, Inc. Dual bank memory and systems using the same
US5473566A (en) * 1994-09-12 1995-12-05 Cirrus Logic, Inc. Memory architecture and devices, systems and methods utilizing the same
US5500819A (en) * 1994-09-30 1996-03-19 Cirrus Logic, Inc. Circuits, systems and methods for improving page accesses and block transfers in a memory system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4649377A (en) * 1983-05-24 1987-03-10 Hitachi, Ltd. Split image display control unit
US4829294A (en) * 1986-06-25 1989-05-09 Hitachi, Ltd. Document processing method and system using multiwindow
US5121114A (en) * 1989-05-29 1992-06-09 Sharp Corporation Information processing apparatus having a specified-area confirming function

Also Published As

Publication number Publication date
JPH10510634A (en) 1998-10-13
US6157366A (en) 2000-12-05
WO1996018988A2 (en) 1996-06-20
KR980700633A (en) 1998-03-30
EP0804785A2 (en) 1997-11-05

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