COMMUNICATIONS NETWORK, A DUAL
MODE DATA TRANSFER SYSTEM THEREFOR
This invention relates to communication over a multiplex data communications network. In particular, this invention relates to a system for interchanging data bytes within a node between a microcontroller (MCU) and a first peripheral at a chosen clock
frequency. Then within the same node, the first peripheral generates a protocol bit and then converts both the protocol bit and each bit of the data bytes from the MCU into variable pulse width modulated (VPWM) bits forming a VPWM message. After forming the message of VPWM bits, the first peripheral sends the VPWM bits to a second peripheral that converts each VPWM bit into a communications symbol (known as a J1850 symbol) conforming to the communication requirements of the Society of Automotive Engineers (SAE) established
Recommended Practice J18S0 (a set of technical
requirements and parameters).
The second peripheral, a transceiver, drives these symbols onto a single-wire communications bus to communicate the message to other nodes connected -to the bus. The second peripheral also routes a reflection of the symbols back to the first peripheral and reconverts the symbols into VPWM bits. The first peripheral than reassembling the reflected bits into bytes used in the next interchange of bytes with the MCU and to check for the achievement of arbitration if other nodes on the bus are transmitting.
Normally, transmitting and receiving serial bytes between the first peripheral device and the MCU require
interrupts in the transfer programming. U.S. Patent No. 5,274,636 dated Dec. 26, 1993 of Halter et al.
entitled "Automatic Multiplex Data Link System, Symbol Encoder Decoder Therefor" (or SED patent) teaches such a system. Such interruptions imposes a heavy burden on the MCU to perform the process of transmitting and receiving serially arranged byte messages. During transmission, programming of the MCU must allow for, illustratively, 34 microseconds between bytes for the introduction of an interrupt. This imposes time restraints on the MCU when preparing each byte for transmission, similar time restraints occur for receiving bytes of data. We searched for ways to reduce the imposed time restraints on the MCU while improving the processing performance. That search ended in the present invention which accomplishes reducing the time restraints required to process the data prior to converting the data into J1850 symbols and for determining whether a node has gained control of the bus by winning an arbitration contest with competing nodes during a message frame.
The present invention discloses using a
conventional serial peripheral interface (SPI)
transfer circuit within the MCU to communicate with a serial peripheral data register (LSPDR) in a peripheral referred to as a link device (Link) . The transfer of data bytes between the MCU and the Link occurs in the form of individual bits of a byte transferred serially from a data register in the MCU to a data register in the link during a SPI transfer (SPI-XFR) at a chosen clock rate illustratively, one bit/one μs pulse. Then, from the Link, the individual bits of the SPI-XFRed byte are converted to variable pulse width modulated
bits and are then driven onto the bus by an integrated driver/receiver (IDR) module as J1850 symbols at the chosen clock rate but delayed to compensate for the variations in pulse width of each symbol, e.g., one symbol may be longer than another (64 or 128 μs long). Hence 64 clock pulses would occur during the transfer of a 64 μs long symbol. The ratio of SPI transfer to bus transfer are such that a period of time,
illustratively 500 μs, may result between SPI-XFRs of individual bytes, removing the need for interrupts. The system, however, contains the capability of operating in an interrupt mode.
The sending and receiving of bits of the data bytes between the Link and the second peripheral called an integrated driver receiver circuit (IDR) and over the single-wire bus occur at the same rates of speed that symbols travel over the bus.
Clock signal (SPISCK) clocks bits of data bytes through circuits within the MCU at a fixed clock frequency while shift clock (SHCLK), clock (CLK) and clock divide by 2 (CLKDIV2) and clock circuits within the Link and IDR during transfers of VPWM bits and symbols
The invention and its modes of operation will be more fully understood from the following detailed description when taken with the appended drawing figures in which:
Fig. l illustrates in block diagram form a
communications network employing the dual-stage data transfer system of this invention in each node of the network;
Fig. 2 depicts in expanded block diagram form to show the components of the Link in a pair of nodes of Fig. 1 connected to the communication bus;
Figs. 3, 4 and 5 illustrate in partial block and logic diagram form the transmitter/receiver, the transmitter and receiver circuits, respectively, of the symbol encoder/decoder modified to interface and form a part of the Link;
Fig. 6A-6G depict significant timing sequences associated with the operation of the SPI-XFR system;
Fig. 7A-7J illustrate timing diagrams associated with transferring a three-byte message from the MCU to the Link and over the single-wire bus to other nodes of the network;
Fig. 8 illustrates a state diagram of the various states required to transfer byte messages from the MCU to the bus and for checking arbitration of symbols on the bus;
Fig. 9A-9C illustrates in partial block and partial logic diagram form the devices in Link used to exchange data bytes with the MCU and to send to and receive from the bus data symbols; and
Fig. 10A and 10B depict the flowchart of the firmware programs for controlling the operation of the MCU during solicited and unsolicited SPI-XFRs of data bytes.
Fig. 10C represents a detail of said flowchart.
Fig. 1 depicts a block diagram of a communications network 10 with several nodes 16a-16f coupled between a single-wire bus 12 and a plurality of sensors or application devices 14a-14f. The nodes include MCUs 18a-18f and Links 22a-22f circuits and interfaces for performing SPI-XFRs, and IDRs 20a-20f connected to the Links for converting between digital pulses and J1850
symbols during sending and receiving messages over bus 12. Each Link 22 interconnects between an MCU 18 and an IDR 20.
Nodes 16a-16f, disposed throughout the vehicle, connect to bus 12 via stubs 13a-l3f, respectively. Bus 12 supports bi-directional transfers of serial data between nodes. Nodes 16a-l6f permit exchange of bit stream information of almost any established protocol. THE NODES
Sensor to MCU Tranefers
Referring to Fig. 2, there a block diagram depicts additional details of nodes 16a and 16b.
Illustratively, in node 16a, sensor 14a detects analog measurands and an analog to digital converter in MCU
18a converts that signal into digital signals usable by MCU 18a. MCU 18a accepts and then transforms the digital signals into a series of message bytes for transfer over bus 12. To effect the transfers, each message byte routes over a parallel bus within MCU 18a and into a conventional MCU serial peripheral data register (MSPDR) 19f for temporary storage. Loading a Message Byte into the L ink by a SPT-XFR From MCU.
Assume node 22a desires to transmit a message over bus 12 to other nodes connected to the bus. When prompted, MCU 18a interchanges the stored message byte by a SPI-XFR, bit-by-bit, serially with a previously transferred data byte stored in a serial peripheral data register (LSPDR) 28a of Link 22a. During the initial SPI- XFR, MCU 18a gets unusable data while Link 22a gets the first message byte associated with the sensed data. The interchanging of bits occur via SPI circuit 19d through master-in slave-out (MISO) and
master-out slave-in (MOS1) pins of MCU 18a that connects MSPDR 19f to LSPDR 28a. A SPI clock (SPISCX) signal emanating from Link 22a clocks movement of bits through MSPDR 19f while a Link clock signal (SHCLK) clocks movement of bits through LSPDR 28a. SPISCK starts after MCU 18a strobes a handshaking signal called Byte Ready (BYT RDY) from a designated output port to holding registers STATEIN 62a, STATEOUT 70a and a main state machine (MSTATE 48a) of Link 22a. The operation and structural details of MSTATE 48a, STATEIN 62a and STATEOUT 70a appear in co-pending patent application, serial number U.S.S.N. 08/356,999 of
Halter et. al. filed December 16, 1994.
Upon receipt of BYT RDY, Link 22a immediately initiates, illustratively, a high-speed l MHz, eightbit, SPI- XFR. MSPDR unloads byte 1 through the MISO pin transferring serially one bit at a time of the first byte of the message to LSPDR. Simultaneously, LSPDR serially unloads bits of byte X (unknown data) into the MOSI pin of MCU 18a. Figs. 6E and 6F show the SPI-XFR in response to SPISCK of Fig. 6C. The rising edge of SPISCK causes MCU 18 to place data at the sending MISO pin and at the sending MOSI pin of Link 22. The falling edge of SPISCK causes the latching of the data on the receiving pins of MCU 18a and Link 22a. The transfer of each byte consumes about 11 μs.
Following the transfer of byte 1, and the receipt of an unusable byte X, MCU 18a writes the next byte, byte 2, over byte X in MSPDR 19f and then strobes BYT RDY again. The rising edge of this second BYT RDY must occur at least 2.1 μs after the falling edge of the last SPISCK pulse of the SPI transfer. (See Fig. 7D and 7G Index # 2).
Link and IDR Converting the SPI
Transferred Data Bits into Data Symbols
The most significant bit (MSB) and then each succeeding bit of byte l in LSPDR 28a routes to an Encoder 37a of Fig. 2. Encoder 37a converts each bit into send codes SNDO and 6ND1. These send codes have values of 00, 01, 10 or 11 depending upon the bit value and level (HIGH or LOW) of the bus for the next symbol.
Send codes route to ports of the XMIT/REC Ckt 24 of Fig. 3 of the symbol/encoder (SED) 23a and join (not shown) an additional code (a logic 0 code or a fixed ground signal) to form a three-bit-send code. This three-bit-send code joins with a three-bit-receive code (not shown) to form a six-bit code that routes to a 6 to 3 ROM address multiplexer (MUX) 38. As described in the SED patent, U.S. Patent No. 5,274,636, each data byte bit from the SPI-XFR causes an address from MUX 38 of XMIT/REC Ckt 24 in SED 23 to select one of eight 10 bit transmit words stored in a decoder ROM 40. These 10 bit words represent nominal lengths of time for the various J1850 symbols (minus 19 μs). It takes about 19 μs for SED 22a of Fig. 2 to receive back from IDR 20a the reflection of the leading edge of the transmitted symbol. Primarily, the messages will contain symbols for the start-of-frame (SOF) (also referred to as start-of-message (SOM)), a long bit (nominally 128 μs), a short bit (nominally 64 μs), an end-of-data (EOD) and an end-of-frame (EOF) symbol which are nominally 200 and 239 μs respectively.
Converting Nomi nal Length Words i nto J1850 Symbols
Within the XMIT/REC Ckt24, a comparator 44 compares time counted in a 10-bit counter 42 to the value of the ROMDATA word from the 4 to 10 Decoder ROM 40 to determine if a comparison occurs. If so, then
circuits in Transmit (XMIT) Ckt 26 of Fig. 4 ends the transmission of that symbol. The link then starts the transmission of the next symbol and initiates a variable pulse width modulated (VPWMout) signal of the selected width and logic level from SED 23a of Fig. 2 to the transmitter (XMIT) circuit of an interface driver receiver (IDR) circuit 20a. The XMIT ckt of IDR 20a converts each VPWMout signal into a trapezoidal pulse shaped symbol resembling an analog signal. These symbols travel over bus 12 at a rate of about 10.4 K bits/sec. or 10.4 Kilobauds.
Checking Arbitration
A receiver circuit in IDR 20a taps single-wire bus 12 and reflects each symbol back towards transmitting MCU 18a. For data symbols, not protocol symbols, this reflection of symbols occurs during state 10 (ST10), explained infra (or see Fig. 8, of the main state machine in Link 23a). Arbitration of the symbols on bus 12 occurs with respect to a BITVAL signal from SED 23a. (The transfer and arbitration of protocol symbols are explained in co-pending application of Halter et. al. filed December 16, 1994, serial no. U.s.S.N.
08/356,999).
A change to ST10, the main state for bus 12 transmitting and receiving bits to and from bus 12, causes the XMITMODE of STATEIN 62a to set and to initiate transmission of a symbol bit onto bus 12. The receiver circuit of IDR 20a receives a reflection of the symbol placed on bus 12 and converts the symbol to a digital bit and routes the bit back to a receive pin of link 22a. The receive pin connects to REC Ckt 27 of Fig. 5 within SED 23a. The REC Ckt 27 contains
circuits that determine whether a logic 1 or 0 bit value (BITVAL) relates to the reflected symbol. Then
STATEIN holding register 62a of Fig. 2 compares the BITVAL received from SED 23A to the previous MSB of LSPDR 28a. (See Fig. 9B). If the same bit comes in that was previously the MSB of LSPDR 28a, then Link 22a wins arbitration and moves to ST 12. If not. Link 22a loses arbitration to another node on bus 12. (See Fig. 7H, I, and J that illustrates which node wins
arbitration).
In ST 12, the arbitrated bit shifts into LSPDR 28a and the BITCNT in STATEIN 62a increments. (See
9C). If the BIT CNT does not equal zero, then MSTATE 48a moves back to ST 10. Arbitration of symbols and the movement between ST10 and ST12 continues until all symbols in the message byte passes. The Link clock signal, SHCLK, clocks the bit movement during ST 10 and ST12. Fig. 6G illustrates the reception of logic 1 and logic 0 bits from bus 12. The time between SHCLK pulses is determined by the duration of the pulse. A logic 0 could be a long or short symbol, hence the duration of the pulse may be either 64 or 128 μs. From ST 12, if BIT CNT equals zero, then MSTATE 48a moves^o ST 13.
SPI TRANSFER FOR UNLOADING TO THE MCU THE RECEIVED BYTE AMP LOADING THE NEXT BYTE TO THE LINK
In ST 13, node 16a prepares for a SPI transfer after receiving eight reflections of bits from bus 13 and placing them in LSPDR 28a.
in ST14, the SPI-XFR between Link 22a and MCU 18a occurs in response to the 1 μs SPISCK. By using BIT
CNT, Link 22a and MCU 18a interchange the eight bits in the LSPDR 28a with the eight bits of byte 2 in MSPDR
19f. TRANSMITTING THE NEXT BYTE ONTO THE BUS
In ST 15, Link 22a clears the SPI-XFR holding register in STATEOUT 70a due to the completion of the SPI-XFR. Assuming BYTE 2 does not represent the LAST BYTE and MCU 18a has indicated another BYT RDY (BYTE 3), MSTATE 48a moves to ST17, the normal transmitting path.
In ST17, the bits of BYTE 2 are transmitted over bus 12. BYT RDY holding register in STATEIN 27a is cleared, and the LAST BYTE shift register is shifted. The shifting of the LAST BYTE is necessary because its status is associated with the data byte that was most recently shifted in from MCU 18a. Upon completion of the message, a cycle redundancy check (CRC) of the transmitted characters is performed (ST15, 19, 20, 21, 10) . After the (CRC), an end of frame (EOF) occurs (ST10, 23, 24).
TIMING WITHIN LINK
As noted in Fig. 2, SED 23 provides clock signals for the node. An OSC signal from MCU 18 provides a source of continuous and accurate clock signals used for clocking system operations.
THE CL K SIGNAL.
After dividing OSC into OSCDIV2 and 0SCDIV4, a multiplexer (MUX) circuit (not shown) extracts from the two pulse trains a first clock signal (CLK) of Fig. 6A of a chosen frequency, e.g., 2 MHz and the inverse clock signal (CLKL) .
THE CLKDIV2 SIGNAL
Within SED 23, a sequential logic divide by two () circuit converts, illustratively, the 2 MHz CLK signal to a 1 MHz CLKDIV2 signal of Fig. 6B that routes to various sequential logic circuits of Link 22. CLKDIV2
signals control the transfer of input signals into Link 22 and the changing of the states. Note in Fig. 9A, the rising edge of the CLKDIV2 signal clocks memory 33b.
THE INTCLK SIGNAL
A combinational logic circuit converts CLKDIV2 to a 1 MHz INTCLK signal of FIG. 6C offset from CLKDXV2 by a 1/4 cycle. The INTCLK signal clocks the setting of flags and other output signals from Link 22 including SO-0 through so-33. (See Fig. 9A). INTCLK combines with other control signals to create additional control signals such as SPICLK that occur at the same time as INTCLK.
THE STENH SIGNAL
Another delay circuit converts the INTCLK βignal into a 1/4 cycle pulse occurring in the last 1/4 of the INTCLK cycle. The STENH signal, Fig. 6D, provides the clock signal for gating the state output signals.
THE OPERATTON OF THE SYSTEM
To describe the operation of the system when transferring data bytes, refer to Fig. 7 through Fig. 10B. In Fig. 9A, a sensor 14 supplies variable
measurand information such as pressure, rate of flow, speed etc. in digital form to MCU 18. MCU 18,
illustratively, which could be a microcontroller such as the M68HCO5 of Motorola or an equivalent, converts the digital bits from sensor 14 into message frames:. J1850 messages require a protocol symbol (SOF) to precede a header byte and one or two protocol symbols (EOD and EOF) to follow the cyclic redundancy check (CRC) bytes in a message frame. The manner this
MCU/Link system deals with protocol symbols is
explained in the copending application mentioned supra.
With reference to Fig. 7, Fig. 7A shows the sequence of numbers of the state machine flow diagram of Fig. 8 in an effort to coordinate the operation of the system. Fig. 7B shows an idle condition of bus 12 and that bus 12 has been idle for some period of time before MCU 18 initiates a transmission. This means that when bus 12 became idle, MCU 18 did not have a message queued up for transmission.
Solicited Transfer: SPI-XFR Initiated by MCU
When MCU 18 obtains a message for transmission, MCU 18 attempts to perform a solicited transfer. Such a transfer occurs when MCU 18 transmits an initial message byte, usually the header byte. MCU 18 enters a transmitting mode by not setting the serial peripheral interface status flag (SPIF) in Fig. 10A of the serial peripheral status register (SPSR) or as a result of a reset of the system. MCU 18 asserts the BYT RDY pin to start the transmission of a message.
After the solicited transfer, SPIF gets set automatically by MCU hardware. Then unsolicited transfers occur for all subsequent transfers between Link 22 and MCU 18.
Figs. 10A and 10B illustrate in flowchart form, the software operations in MCU 18 used to communicate with link 22. These charts represent an effort to organize the generation and flow of signals through MCU 18. These flowcharts differ from the conventional box and diamond flowcharts.
In these charts, signals entering and leaving the flow of control pass along lines and proceed down the page. Conventional start of program and end of program are used. Trapezoidal or rectangularly shaped boxes
indicate signals entering and leaving the flow of control. Actions are signified by a small black circle on the lines, the description of the action being given to the left or right of the flow lines. When
introducing a decision, the flow line branches to the right or left. A branch may be caused by either a YES or NO condition, with these being signified by a Y or N in a small box as indicated. An arrowhead depicts where secondary flow rejoins the main flow. A
reference number indicates the position or step along the line being discussed.
Returning now to the solicited transfer, note in Fig. 10A, this firmware program requires MCU 18 to determine the status of SPΣF. Assuming a set SPIF, MCU 18 then must determine the status of bus 12. Link 22 provides an idle bus status signal to MCU 18. For an idle bus 12, CPU 19a receives instructions to determine the status of the input capture flag (ICF). A set ICF signal means an idle bus has occurred since the last time MCU 18 inspected bus 12, i.e., there is an
outstanding unprocessed idle signal. For example, MCU 18 was receiving a message, for which the transmission has finished. MCU 18 must process the received message before starting the transmission, due to time
considerations. Assuming no ICF, then CPU 19a
determines whether the XMTNUM RAM counter, used to count the number of bytes in the transmit buffer
(XMTBUF), has a non-zero value. Using the message depicted in Fig. 7C, illustratively, XMTNUM equals 3. Assuming an idle bus 12, and CPU 19a learns the
availability of a message, then CPU 19a sets the
XMITMODE flag. (See steps 200-209 of Fig. 10A).
An event (internal or external to MCU 181 causes CPU 19a to generate a message frame for transmission over bus 12. An application layer subroutine formats
the message frame and stores the bytes in XMTBUF.
XMTNUM gets set to the number of bytes that MCU 18 will transmit.
In this configuration, CPU 19a fills XMTBUF
(usually an 11 byte buffer) backwards, as shown in
Fig. 10C, so that the first byte to send gets stored as XMTBUF, XMTNUM-1 or XMTBUF, 2; the second byte stored as XMTBUF, XMTNUM-2 or XMTBUF, 1; and the third byte stored as XMTBUF, XMTNUM-3 or XMTBUF, 0.
After establishing XMTNUM-3, with bus 12 idle, CPU 19a sets XMTNDXBXMTNUM, illustratively to 3 and
ARBNDX=XMTNUM or 3. ARBNDX is an index into XMTBUF that points to the next byte coming back from bus 12. (See steps 210-212).
At step 214, CPU 19a receives instructions to load
XMTNDX-1 or the data in XMTBUF, 2 into the SPI data register (SPDR) 19f. Then at step 216, CPU 19a sets BYT RDY pin HI. This informs link 22 of a byte ready for transmission. (See Fig. 7G, index #1).
CPU 19a then sets XMTNDX equal to XMTNDX-1 or in this illustration to 2. CPU 19a receives instructions to determine if the SPI-XFR between MCU 18 and Link 22 has been completed. (See Fig. 10A, step 219) . Usually, this transfer consumes about 11 μs well within the first 400 μs polling cycle. The byte that was stored in the LSPDR 28, which is unusable, comes into the MSPDR 19f of MCU 18.
After completion of the transfer, the hardware in MCU 18 automatically clears the SPIF bit in the SPI Status Register, (SPSR) (not shown). Then CPU 19a receives instructions to load the byte received from the LSPDR 28 into a non-volatile MCU register. This completes the solicited transfer. MCU 18 does not care about the initial byte that comes back into the MSPDR from Link 22. (See steps 220-221).
If XMTNDX does not equal zero, CPU 19a sets BYT RDY pin LO. This means that there are more bytes to transmit, if there are more bytes to transmit, then CPU 19a loads the second byte to be transmitted in the MSPDR 19f by writing over the returned initial byte and then setting BYT RDY pin HI a second time. (See steps 222-224) . The rising edge of the second short BYT RDY pulse must occur at least 2.1 μs after the falling edge of the last SPISCK pulse of the SPI-XFR. (See the waveforms in Fig. 7D and 7F) . When the SOF symbol ends, Link 22 begins transmitting the first byte onto bus 12. CPU 19a then sets XMTNDX equal to XMTNDX-1. XMTNDX is now 1. If XMTNDX is not equal to zero, then CPU 19a sets BYT RDY pin LOW. CPU 19a then exits the. solicited transfer routine. (See steps 226-229).
MCU RECEIPT OF AN UNSOLICITED BYTE BY SPT XFR and SPI XFR OF 2ND BYTE
After loading byte 1 on bus 12, IDR 20 and Link 22 reflect byte 1 (received off bus 12) back to MCU 18 via an unsolicited transfer. (See Fig. 7G, index #3).
In Fig. 10A, during another 400 μs polling cycle, at step 200, CPU 19a determines if SPIF is set. This serial peripheral transfer flag notifies MCU 18 that the solicited data transfer between MCU 18 and Link 22 has been completed. Hence the program branches to the unsolicited transfer program on Fig. 10B.
ARBTTRATTON CHECKED
At the same time MCU 18 receives back the
unsolicited byte 1, Link 22 receives byte 2 (if any) from MCU 18 via the SPI-XFR. During the time Link 22 was attempting to transmit byte 1, Link 22 could ave lost arbitration to another transmitting node. If so, the byte it was attempting to transmit is not the byte
that ends up being transmitted on bus 12. MCU 18 checks each byte it receives back from Link 22 against the byte it attempted to transmit. If byte 1 does not match, MCU 18 switches to a receive operation. If the first byte received back matches but subsequent bytes do not, MCU 18 assumes an error has occurred. This is due to the fact that this system utilizes a single-byte header and arbitration should be resolved with the first byte. If the second or subsequent bytes do not match, MCU 18 terminates transmission of the message and waits for the next idle bus period.
PERFORMANCE OF THE UNSOL ICTTED TRANSFER
In Fig. 10B, after the SPIF bit goes to a logic 1, MCU 18 receives instructions to clear BYT RDY and then to determine if XMITMODE flag is set. Since node 1 is transmitting, the program branches to the next
instruction which requires determining if ARBNDX is equal to zero. If so, then the program exits but, illustratively, since ARBNDX was previously set to 3,
CPU 19a reacts to the next instruction of accessing the SPI STATUS REGISTER (SPSR). Then CPU 19a receives the instruction to load the data byte read from bus 12 into a nonvolatile MCU register (not shown). This action also clears the SPIF bit.
Then CPU 19a determines if the byte received from bus 12 equals the byte transmitted. If so, CPU 19a updates the ARBNDX by setting it to [3-1] or 2. (See steps 230-240).
TRANSFER OF THE TAST BYTE
CPU 19a receives instructions to determine if XMTNDX equals zero. Since XMTNDX does not, CPU 19a executes the next instruction to place the last byte in the SPDR (XMTNDX-1) . Then CPU 19a receives the
instruction to set the BYT RDY pin HI. Leaving the BYT RDY pin HI indicates that the byte in the MSPDR is the last byte to be transmitted. CPU 19a then moves to execute the instruction to update the XMTNDX before existing the program. XMTNDX now becomes zero.
Illustratively, CPU 19a loads the last byte into MSPDR 19f and asserts the BYT RDY pin HI. BYT RDY pin remains HI through the next unsolicited transfer. This is referred to as the long form of BYT RDY. This tells Link 22 that the byte sitting in MSPDR I9f is the last byte to transmit. As with the short BYT RDY pulse, the rising edge of a long BYT RDY must occur at least 2.1 μs after the falling edge of the last SCK pulse of the SPI XFR. During the unsolicited transfer (Fig. 7G, index #4), MCU 18 receives BYTE 2, while Link 22 receives byte 3. Following the transfer, MCU 18 returns the BYT RDY pin LO.
Illustratively, two more unsolicited transfers must occur, namely an unsolicited transfer for the third byte and one for the CRC byte. For each of these two unsolicited transfers, XMTNDX equals zero. So no more bytes are sent to Link 22 for transmission. After each unsolicited transfer, CPU 19a must check the byte received against XMTBUF, ARBNDX-1 and decrement ARBNDX afterwards. LINK A UTOMATICA LLY TRANSMITS A CRC
Following the transmission of byte 3, unsolicited transfer (Fig. 7G, index≠ 5) sends byte 3 to MCU 18. Then MCU 18 exits the Unsolicited program. Link 22 automatically transmits the proper CRC byte on to bus 12. Unsolicited transfer (index≠ 6) sends the CRC to MCU 18. During the unsolicited transfer for the CRC, ARBNDX equals 0, so MCU 18 does not participate in this transfer. The idle pin returns to LO (index # 7)
indicating bus 12 is once again idle. This causes an interrupt to MCU 18.
Since other modifications and changes varied to fit particular operating requirements and environments will be apparent to those skilled in the art, the invention is not considered limited to the example chosen for purposes of disclosure, and covers all changes and modifications which do not constitute departures from the true spirit and scope of this invention.