WO1996024137A3 - Circuits, systems and methods for improving row select speed in a row select memory device - Google Patents

Circuits, systems and methods for improving row select speed in a row select memory device Download PDF

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Publication number
WO1996024137A3
WO1996024137A3 PCT/US1996/001351 US9601351W WO9624137A3 WO 1996024137 A3 WO1996024137 A3 WO 1996024137A3 US 9601351 W US9601351 W US 9601351W WO 9624137 A3 WO9624137 A3 WO 9624137A3
Authority
WO
WIPO (PCT)
Prior art keywords
row select
memory device
circuits
systems
methods
Prior art date
Application number
PCT/US1996/001351
Other languages
French (fr)
Other versions
WO1996024137A2 (en
Inventor
G R Mohan Rao
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Priority to JP8523716A priority Critical patent/JPH10513297A/en
Priority to EP96906247A priority patent/EP0807308A2/en
Publication of WO1996024137A2 publication Critical patent/WO1996024137A2/en
Publication of WO1996024137A3 publication Critical patent/WO1996024137A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Abstract

A memory device (200) is provided which includes an array (202) of rows and columns of memory cells (201). Row decoder circuitry (206) is provided for selecting a given row of cells (201) for access. Circuitry (208, 209) is included for providing a selected one of a plurality of supply voltages to the row decoder circuitry (206), a first positive voltage provided during an active state of the row decoder circuitry (206) and a second positive voltage provided during an inactive state of the row decoder circuitry (206).
PCT/US1996/001351 1995-01-31 1996-01-31 Circuits, systems and methods for improving row select speed in a row select memory device WO1996024137A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8523716A JPH10513297A (en) 1995-01-31 1996-01-31 Circuits, systems and methods for improving row selection speed in row selection storage
EP96906247A EP0807308A2 (en) 1995-01-31 1996-01-31 Circuits, systems and methods for improving row select speed in a row select memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/381,189 US5701143A (en) 1995-01-31 1995-01-31 Circuits, systems and methods for improving row select speed in a row select memory device
US08/381,189 1995-01-31

Publications (2)

Publication Number Publication Date
WO1996024137A2 WO1996024137A2 (en) 1996-08-08
WO1996024137A3 true WO1996024137A3 (en) 1996-09-26

Family

ID=23504054

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/001351 WO1996024137A2 (en) 1995-01-31 1996-01-31 Circuits, systems and methods for improving row select speed in a row select memory device

Country Status (5)

Country Link
US (1) US5701143A (en)
EP (1) EP0807308A2 (en)
JP (1) JPH10513297A (en)
KR (1) KR19980701822A (en)
WO (1) WO1996024137A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229508B1 (en) * 1997-09-29 2001-05-08 Sarnoff Corporation Active matrix light emitting diode pixel structure and concomitant method
US6772273B1 (en) * 2000-06-29 2004-08-03 Intel Corporation Block-level read while write method and apparatus
DE10219066B4 (en) * 2002-04-29 2006-12-14 Infineon Technologies Ag RAM memory circuit
US20050105372A1 (en) * 2003-10-30 2005-05-19 Fujitsu Limited Semiconductor memory
JP4437710B2 (en) * 2003-10-30 2010-03-24 富士通マイクロエレクトロニクス株式会社 Semiconductor memory
WO2006038174A2 (en) * 2004-10-01 2006-04-13 Chen-Jean Chou Light emitting device display and drive method thereof
JP5151106B2 (en) * 2006-09-27 2013-02-27 富士通セミコンダクター株式会社 Semiconductor memory and system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3621302A (en) * 1969-01-15 1971-11-16 Ibm Monolithic-integrated semiconductor array having reduced power consumption
EP0498251A2 (en) * 1991-02-05 1992-08-12 International Business Machines Corporation Word line driver circuit for dynamic random access memories

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257987B1 (en) * 1986-08-22 1991-11-06 Fujitsu Limited Semiconductor memory device
US5034917A (en) * 1988-05-26 1991-07-23 Bland Patrick M Computer system including a page mode memory with decreased access time and method of operation thereof
JP2614514B2 (en) * 1989-05-19 1997-05-28 三菱電機株式会社 Dynamic random access memory
KR0140673B1 (en) * 1993-01-27 1998-06-01 모리시다 요이찌 Semiconductor memory
US5365479A (en) * 1994-03-03 1994-11-15 National Semiconductor Corp. Row decoder and driver with switched-bias bulk regions
US5455526A (en) * 1994-08-10 1995-10-03 Cirrus Logic, Inc. Digital voltage shifters and systems using the same
US5452244A (en) * 1994-08-10 1995-09-19 Cirrus Logic, Inc. Electronic memory and methods for making and using the same
US5506810A (en) * 1994-08-16 1996-04-09 Cirrus Logic, Inc. Dual bank memory and systems using the same
US5442588A (en) * 1994-08-16 1995-08-15 Cirrus Logic, Inc. Circuits and methods for refreshing a dual bank memory
US5500819A (en) * 1994-09-30 1996-03-19 Cirrus Logic, Inc. Circuits, systems and methods for improving page accesses and block transfers in a memory system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3621302A (en) * 1969-01-15 1971-11-16 Ibm Monolithic-integrated semiconductor array having reduced power consumption
EP0498251A2 (en) * 1991-02-05 1992-08-12 International Business Machines Corporation Word line driver circuit for dynamic random access memories

Also Published As

Publication number Publication date
KR19980701822A (en) 1998-06-25
JPH10513297A (en) 1998-12-15
US5701143A (en) 1997-12-23
EP0807308A2 (en) 1997-11-19
WO1996024137A2 (en) 1996-08-08

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