WO1996041250A3 - System and method for processing multiple requests and out of order returns - Google Patents
System and method for processing multiple requests and out of order returns Download PDFInfo
- Publication number
- WO1996041250A3 WO1996041250A3 PCT/US1996/008549 US9608549W WO9641250A3 WO 1996041250 A3 WO1996041250 A3 WO 1996041250A3 US 9608549 W US9608549 W US 9608549W WO 9641250 A3 WO9641250 A3 WO 9641250A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- cpu
- requests
- cache
- tags
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0857—Overlapped cache accessing, e.g. pipeline by multiple requestors
Abstract
A system and method for processing a sequence of requests for data by one or more central processing units (CPUS) after cache misses. Each CPU request includes a CPU-ID tag identifying the CPU issuing the request for data and an address identifying a location in lower-level memory where the data is stored. Cache-control ID tags are assigned to identify the locations in the request queue of the respective CPU-ID tags associated with each CPU request. Cache-control requests consisting of the cache-control ID tags and the respective address information are sent from the request queue to the lower-level memory or storage devices. Data is then returned along with the corresponding CCU-ID tags in the order in which it is returned by the storage devices. Finally, the sequence of CPU requests for data is fulfilled by returning the data and CPU-ID tag in the order in which the data was returned from lower-level memory. By issuing multiple requests for data and allowing out of order data return, data is retrieved from lower-level memory after cache misses more quickly and efficiently than processing data requests in sequence. By checking the request queue, pending CPU requests for the same data including requests for the same long word of data can be identified. Cache hits for multiple requests are determined by simultaneously checking sets in cache memory. Multiple instructions are then issued for multiple superset cache hits.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/479,035 | 1995-06-07 | ||
US08/479,035 US5778434A (en) | 1995-06-07 | 1995-06-07 | System and method for processing multiple requests and out of order returns |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1996041250A2 WO1996041250A2 (en) | 1996-12-19 |
WO1996041250A3 true WO1996041250A3 (en) | 1997-03-06 |
Family
ID=23902394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/008549 WO1996041250A2 (en) | 1995-06-07 | 1996-06-03 | System and method for processing multiple requests and out of order returns |
Country Status (2)
Country | Link |
---|---|
US (2) | US5778434A (en) |
WO (1) | WO1996041250A2 (en) |
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CN112328520B (en) * | 2020-09-30 | 2022-02-11 | 郑州信大捷安信息技术股份有限公司 | PCIE equipment, and data transmission method and system based on PCIE equipment |
US11734005B2 (en) | 2021-07-04 | 2023-08-22 | Mellanox Technologies, Ltd. | Processor with split read |
CN114979131B (en) * | 2022-04-07 | 2024-04-19 | 中国科学院深圳先进技术研究院 | Cloud computing-oriented communication method and device for labeled von neumann architecture |
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-
1995
- 1995-06-07 US US08/479,035 patent/US5778434A/en not_active Expired - Lifetime
-
1996
- 1996-06-03 WO PCT/US1996/008549 patent/WO1996041250A2/en active Application Filing
-
1998
- 1998-02-17 US US09/024,134 patent/US6173369B1/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4370710A (en) * | 1980-08-26 | 1983-01-25 | Control Data Corporation | Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses |
EP0292188A2 (en) * | 1987-05-18 | 1988-11-23 | Fujitsu Limited | Cache system |
EP0568231A1 (en) * | 1992-04-29 | 1993-11-03 | Sun Microsystems, Inc. | Methods and apparatus for providing multiple outstanding operations in a cache consistent multiple processor computer system |
Also Published As
Publication number | Publication date |
---|---|
WO1996041250A2 (en) | 1996-12-19 |
US5778434A (en) | 1998-07-07 |
US6173369B1 (en) | 2001-01-09 |
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