WO1997003444A1 - System comprising field programmable gate array and intelligent memory - Google Patents

System comprising field programmable gate array and intelligent memory Download PDF

Info

Publication number
WO1997003444A1
WO1997003444A1 PCT/US1996/011226 US9611226W WO9703444A1 WO 1997003444 A1 WO1997003444 A1 WO 1997003444A1 US 9611226 W US9611226 W US 9611226W WO 9703444 A1 WO9703444 A1 WO 9703444A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
clock
memory
signal
integrated circuit
Prior art date
Application number
PCT/US1996/011226
Other languages
French (fr)
Inventor
Kenneth E. Leeds
Charles R. Erickson
Original Assignee
Xilinx, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx, Inc. filed Critical Xilinx, Inc.
Priority to JP50587497A priority Critical patent/JP3736855B2/en
Priority to EP96923615A priority patent/EP0780017A1/en
Publication of WO1997003444A1 publication Critical patent/WO1997003444A1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/32Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736Structural details of routing resources
    • H03K19/1774Structural details of routing resources for global signals, e.g. clock, reset
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17758Structural details of configuration resources for speeding up configuration or reconfiguration
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/1776Structural details of configuration resources for memories
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17772Structural details of configuration resources for powering on or off

Definitions

  • Xilinx Data Book BACKGROUND OF THE INVENTION "The Programmable Logic Data Book"
  • Xilinx Data Book published by Xilinx, Inc.
  • Xilinx field programmable gate arrays
  • These FPGAs are capable of retrieving configuration data from a serial or parallel memory.
  • the Xilinx Data Book discusses a circuit in which an FPGA receives configuration data from a serial PROM when the FPGA is in a master serial configuration mode, e.g. as shown in Fig. 1. Referring to Fig. 1, an FPGA 1 generates a clock signal on a clock signal line 2.
  • This clock signal is received by a serial PROM 3 , which generates in response thereto a serial data stream on an output line 4.
  • the serial data is received by FPGA 1, which becomes configured in response thereto.
  • FPGA 1 When FPGA 1 is done configuring itself, it asserts a DONE signal on line 5, indicating that configuration is complete. This signal deselects PROM 3.
  • FIG. 2 A variation of this system is shown in Fig. 2.
  • the Fig. 2 system includes first and second FPGAs la and lb.
  • FPGA la sends clock signals on line 2 to both PROM 3 and FPGA lb.
  • PROM 3 responds to the clock signals by providing data signals to FPGA la on line 4.
  • FPGA la is in the "master serial configuration mode” and FPGA lb is in the "slave configuration mode".
  • Serial PROM 3 thus continues to send data to FPGA la via line 4. This data is passed from FPGA la to FPGA lb via a line 7.
  • FPGA lb takes the data from line 7 and uses that data to configure
  • FPGAs la and lb include open drain output buffers which drive leads 5a and 5b, respectively. Leads 5a and 5b are "AND-tied" together. When FPGAs la and lb are both done being configured, the signal on leads 5a and 5b goes high, indicating that both FPGAs are done being configured, and deselecting PROM 3.
  • FIG. 3 Another variation of FPGA configuration is shown in Fig. 3, in which an FPGA 10 communicates address signals via an address bus 11 to a parallel EPROM 12.
  • EPROM 12 responds by providing data signals on a data bus 13 (typically 8 bits wide) . These data signals are received by FPGA 10, which configures itself in accordance with this data.
  • This type of programming mode is known as a master parallel configuration mode. Instead of relying on the FPGA to generate clock signals which are applied to a PROM during serial configuration mode, or relying on the FPGA to generate address signals during master parallel configuration mode, it is known to rely on an intelligent device, such as a microprocessor, to generate clock and/or address signals.
  • an intelligent device such as a microprocessor
  • Microprocessor 20 retrieves configuration data via data bus 23, and passes that configuration data to FPGA 24 via a serial data line 25. Timing is controlled by a clock signal communicated on a clock signal line 26 by microprocessor 20. When FPGA 24 is programmed in this manner, it is in the slave serial mode.
  • Other known modes for configuring FPGAs include a peripheral asynchronous mode and a peripheral synchronous mode. In these modes an intelligent device such as a microprocessor writes configuration data to the FPGA, typically a byte at a time. (See pages 2-38 to 2-41 of the Xilinx Data Book) .
  • Xilinx FPGAs can be configured in each of the foregoing modes. Each of these modes has its own advantages and disadvantages. Using a serial PROM is often advantageous because serial PROMs have a small number of pins and are relatively inexpensive. To use a serial PROM, at least one FPGA in the system must be capable of generating a clock signal for causing the serial PROM to provide configuration data. Since FPGAs are mass-produced, and support all these configuration modes, they all contain clock and oscillator circuitry, even though the devices in slave serial configuration mode never use this circuitry.
  • the FPGA In master parallel mode, the FPGA must also have oscillator and clock circuitry, and circuitry for generating addresses. In any configuration mode that uses an intelligent device such as a microprocessor, the resources of that microprocessor must be used to initialize any FPGAs in the system.
  • An FPGA system in accordance with this invention includes a circuit having a memory and capable of generating the necessary signals to program an FPGA integrated circuit without requiring external intelligent circuitry such as a microprocessor and without requiring the FPGA to contain clock or oscillator circuitry.
  • the memory circuit generates a clock signal and a serial data signal which is received by an FPGA during configuration.
  • the memory circuit sends several bits of configuration data in parallel to the FPGA (typically one byte at a time) during configuration. In either event, the resources of a microprocessor are not required, nor is it necessary for the FPGA to contain clock and oscillator circuitry.
  • the memory is an integrated circuit.
  • the memory can employ PROM, EPROM, EEPROM, fuse, antifuse, ROM or other technology.
  • Fig. 1 schematically illustrates an FPGA in master serial configuration mode.
  • Fig. 2 schematically illustrates one FPGA in master serial configuration mode and one FPGA in slave serial configuration mode.
  • Fig. 3 schematically illustrates an FPGA during parallel configuration.
  • Fig. 4 schematically illustrates an FPGA being configured by a microprocessor.
  • Fig. 5a schematically illustrates an FPGA being configured by a memory circuit in accordance with a first embodiment of the invention.
  • Fig. 5b illustrates a variation of the embodiment of Fig. 5a.
  • Fig. 6 illustrates an FPGA.
  • Fig. 7a is a block diagram of the memory circuit of Fig. 5.
  • Fig. 7b is a block diagram of an alternate embodiment of the memory circuit of Fig. 7a including means for receiving an externally generated clock signal.
  • Fig. 7c to 7e are block diagrams of other embodiments of a memory circuit including means for ascertaining when the last bit of configuration data has been provided to an FPGA.
  • Fig. 8a schematically illustrates a plurality of FPGAs being configured by a memory circuit in accordance with a second embodiment of the invention.
  • Fig. 8b schematically illustrates a variation of the embodiment Fig. 8a.
  • Fig. 9 schematically illustrates a plurality of FPGAs being configured by a pair of memory circuits in accordance with a third embodiment of the invention.
  • Fig. 10 schematically illustrates a plurality of FPGAs being configured by a memory circuit in accordance with a fourth embodiment of the invention.
  • Fig. 11 schematically illustrates an FPGA being configured by a parallel memory accordance with a fifth embodiment of the invention.
  • Fig. 12 is a block diagram of the parallel memory of Fig. 11.
  • Fig. 13 schematically illustrates a plurality of FPGAs being configured by a parallel memory in accordance with a sixth embodiment of the invention.
  • Fig. 14 schematically illustrates a seventh embodiment of the invention using a parallel memory having a data bus in which each line of the data bus is connected to an associated FPGA.
  • Fig. 15 schematically illustrates an eighth embodiment of the invention in which three FPGAs receive configuration data in parallel.
  • a memory integrated circuit 30 receives power signals Vcc (typically 5 volts) , ground and an optional reset signal on lines 31, 32 and 33, respectively.
  • the reset signal can be generated by the circuitry in which the system of Fig. 5a is incorporated. In one embodiment, the reset signal is generated by a host microprocessor (not shown) , or a control button on the system.
  • Memory circuit 30 includes a data output signal lead 34, a clock output signal lead 35, and a reset signal output signal lead 36.
  • memory circuit 30 Upon power up (or when the signal on reset signal line 33 goes active) , memory circuit 30 asserts a reset signal on lead 36, which is received by an FPGA integrated circuit 37. This reset signal puts FPGA 37 in a "configuration mode".
  • memory circuit 30 provides clock and data signals on leads 35 and 34, which are received by FPGA 37 and used to configure FPGA 37.
  • FPGA 37 When FPGA 37 is done configuring itself, it asserts a DONE signal on a lead 38, indicating that configuration is complete, and causing memory circuit 30 to cease transmitting configuration data.
  • memory circuit 30 is an EPROM, but other memory technologies (fuses, antifuses, SRAMs, EEPROMs, mask-programmed ROMs, etc.) can also be used.
  • FPGA 37 is typically an integrated circuit comprising an array of configurable logic elements. These elements can have a structure such as the logic element structure used in the Xilinx XC2000, XC3000, XC4000 or XC5000 families of devices. These elements can also have a structure such as that disclosed in U.S. Patent Re 34,363 (incorporated herein by reference) or the structure used in the Flex series of FPGAs manufactured by Altera Corporation.
  • Configuration data can be routed from the FPGA serial data input lead (coupled to lead 34) to configuration memory cells within the FPGA in the same manner as in the Xilinx or Altera devices, or as described the '363 patent. However, in accordance with this invention, timing is typically controlled by the clock signal generated by memory circuit 30.
  • an FPGA contains an array of configurable logic elements, e.g. as shown in '363 Patent Figs. 2, 3a or 3b, or Xilinx Data Book Fig. 1 (page 2-20 of the Xilinx Data Book) .
  • Fig. 6 shows a block diagram of an example of an FPGA, which contains an array of configurable logic elements, or cells 40, arranged in an array 41 of rows and columns. Each cell 40 can be programmed, or configured, to perform any of a number of logic functions. Interspersed about cells 40 is a wiring grid 42. The input and output leads of cells 40 can be programmably electrically coupled to the wires in grid 42.
  • this programmable electrical coupling is accomplished using pass transistors or tri ⁇ state buffers driven by SRAM memory cells.
  • Fig. 6 shows one of the cells (cell 40a) coupled to wiring grid 42 via pass transistors 44.
  • the other cells 40 are also coupled to the wiring grid via pass transistors and each cell input or output line may be coupled to more than one wire of grid 42, but this is not shown in Fig. 6 for the sake of clarity.
  • grid 42 is illustrated as showing three wires between adjacent rows and columns of cells 40, other numbers of wires are typically provided between adjacent rows and columns of cells.
  • the wires in grid 42 are shown as extending the entire length and width of the array, typically, wires within grid 42 have varying lengths, some extending a short distance, some extending a longer distance.
  • the horizontal wires in grid 42 are typically programmably connected to the vertical wires in grid 42 at some of the locations where the horizontal and vertical wires cross.
  • I/O cells 46 Surrounding array 41 is a set of programmable I/O cells 46, which can be programmably connected to wires 42. I/O cells 46 can receive signals from the I/O pins of the FPGA, and provide those signals onto selected wires within grid 42. In addition, I/O cells 46 can receive signals from grid 42 and provide those signals to the I/O pins. In this way, signals from outside the FPGA can be communicated via I/O cells 46 to wiring grid 42, and to selected cells 40 within array 41. Output signals from the various cells can be communicated via grid 42 to other cells 40 within array 41, and/or to I/O cells 46 via grid 42.
  • the programmable interconnections between the various structures shown in Fig. 6 and the configuration of cells 40 are typically controlled by SRAM memory cells within the FPGA (not shown) .
  • the SRAM memory cells within the FPGA can be arranged as a shift register (see the '363 Patent) or arranged as described in the Xilinx Data Book, or as in the Xilinx XC2000, XC3000, XC4000 or XC5000 family of circuits, or as in the Altera Flex circuits.
  • SRAM memory cells e.g. EEPROM memory cells can be used in an FPGA in accordance with the invention.
  • Fig. 7a is a block diagram of memory circuit 30.
  • a clock generator circuit 50 provides a clock signal on lead 35 via a tri-state buffer 51. (As mentioned above, the clock signal on lead 35 is used by FPGA 37 during configuration.)
  • Clock generator circuit 50 can contain a conventional oscillator.
  • clock generator 50 may contain a multivibrator.
  • clock generator 50 can contain an odd number of inverting circuits connected in the form of a feedback loop.
  • clock generator 50 can be coupled to a crystal, LC circuit or other structure external to memory circuit 30.
  • Clock generator 50 also provides a clock signal on a lead 52 which drives a sequential address select circuit 54.
  • a reset control circuit 56 Upon power-up or receipt of a signal on reset line 33, a reset control circuit 56 applies a reset signal to FPGA 31 via lead 36, and a reset signal to address select circuit 54 via a lead 58.
  • the reset signal on lead 58 causes circuit 54 to assert an active output signal on a select line
  • clock generator circuit 50 provides a clock signal to address select circuit 54 via clock line 52.
  • Address select circuit 54 responds to this clock signal by holding select line 60a inactive and asserting an active output signal on the next select line 60b, which in turn causes data from a second row of memory cells 62b to be loaded into shift register 66. The process thus repeats itself until either a) all of the data from memory cells 66 has been shifted out; or b) FPGA 37 asserts a signal on line 38 indicating that configuration is complete.
  • a tri-state control circuit 71 tri-states buffers 51 and 68. In this way, memory circuit 30 controls the configuration of FPGA 37. (Because buffers 51 and 68 are tri-stated, the input pins of FPGA 37 driven by leads 34 and 35 during configuration can be used for other tasks after configuration is complete.
  • Fig. 7b illustrates an alternative embodiment of a memory circuit in accordance with my invention comprising a multiplexer 72 and a control lead 73.
  • multiplexer 72 passes clock signals from clock generator circuit 50 to shift register 66 via lead 70 as described above. These clock signals control the shifting of data from shift register 66.
  • the clock signals from clock generator 50 are coupled to a divide by m circuit 74 via multiplexer 72.
  • the output signal from divide by m circuit drives address selector circuit 54.
  • Shift register 66 contains m bits, where m is an integer, e.g. 8. Thu ⁇ , address select circuit 54 is clocked by divide by m circuit 74 every time m bits from shift register 66 are provided to output lead 34, i.e. every time shift register 66 is emptied of its contents.
  • the signal on control lead 73 When the signal on control lead 73 is high clock generator circuit 50 is disabled, tri-state buffer 51 is put in a tri-state mode, and lead 35 serves as a clock input lead to memory circuit 30. In this mode, the clock signal received on lead 35 is coupled to shift register 66 via multiplexer 72 and lead 70. In addition, as mentioned above, the output signal from multiplexer 72 drives divide by m circuit 74, which is turn clocks address selector circuit 54. In this way, the memory circuit can use either an internally generated clock signal (from clock generator 50) or an externally generated clock signal (received from lead 35) , depending on the state of the signal on control lead 73. Of importance, the signal on control lead 73 can be received via an input pin from a device external to memory circuit 30. Alternatively, the signal on control lead 73 can be provided by a memory cell within memory circuit 30 that is programmed at the same time as the memory cells within rows 62a-62n.
  • Fig. 7b uses lead 35 as a bi-directional lead that can either receive or provide a clock signal, in other embodiments, lead 35 is not bi-directional, and a separate lead is used to receive an externally generated clock signal.
  • memory circuit 30 When power is first applied to the circuit of Fig. 5a, it may take time before the voltage levels within FPGA 37 reach proper values. Further, FPGA 37 may have to reset some or all of its internal memory cells to a known state prior to configuration. Thus, in one embodiment, memory circuit 30 provides a time delay between power-up and the time memory circuit 30 begins to provide configuration data, to ensure that FPGA 37 is ready to receive that configuration data. Alternatively, as shown in Fig. 5b, FPGA 37 may have an output lead 39 coupled to memory circuit 30. In this embodiment, memory circuit 30 commences sending configuration data upon receipt of an INIT signal on lead 39. The INIT signal is provided by FPGA 37 to indicate that it is ready to receive data.
  • FPGA 37 can contain circuitry which determines whether there is a risk that configuration data have been lost. In the event of such a risk, FPGA 37 can assert the INIT signal at that time to start reconfiguration.
  • Fig. 8a illustrates a variation of the embodiment of Fig. 5a, in which three FPGAs 37a, 37b and 37c are configured. All three devices receive the clock signal from memory 30 via lead 35. Of importance, FPGAs 37a and 37b include serial output leads 76a and 76b, respectively.
  • memory circuit 30 provides preamble data to FPGA 37a via line 34, including a length count indicating how many bits of configuration data are going to be provided to FPGAs 37a-37c. This preamble data is stored in FPGA 37a, and passed on to FPGAs 37b and 37c via lines 76a and 76b, respectively.
  • FPGA 37a receives configuration data from memory 30 via lead 34 and uses that data to configure itself, but holds its serial output lead 76a high. As soon as FPGA 37a is done configuring itself, FPGA 37a begins to pass the serial data from lead 34 to lead 76a. This data is then used by FPGA 37b to configure itself. While FPGA 37b is configuring itself, it holds serial output lead 76b high. As soon as FPGA 37b is done configuring itself, it begins to pass the serial data from lead 76a to lead 76b. FPGA 37c receives and uses the data from lead 76b to configure itself. Of importance, each FPGA 37a to 37c includes a counter which increments every time a clock signal is received on lead 35.
  • Each FPGA 37a, 37b, 37c includes an associated open drain output line 38a, 38b, 38c which are "AND-tied" and coupled to memory circuit 30.
  • FPGAs 37a, 37b and 37c have counted a number of clock pulses equal to the length count, all of lines 38a, 38b and 38c are held active (e.g. high), which then causes memory circuit 30 to tri-state buffers 51 and 68 (Fig. 7a) , and to cease sending configuration data to the FPGAs.
  • Fig. 8a shows three FPGAs, the same principle can be applied to any other number of FPGAs.
  • FPGAs 37a-37c contain clock or oscillator circuits.
  • FPGA 37a turns off the transistor driving open drain lead 38a when FPGA 37a is done being loaded with configuration data
  • FPGA 37b turns off the transistor driving lead 38b when FPGA 37b is done being loaded with configuration data
  • FPGAs 37a to 37c do not rely on counting clock signals to determine when to assert a signal on leads 38a to 38c.
  • memory circuit 30 includes a counter 120 (Fig. 7c) that is reset by the signal provided on lead 58 by reset control circuit 56 at the start of configuration.
  • Counter 120 counts the clock pulses on lead 70.
  • Memory circuit 30 also includes a register 122 that contains the number of configuration bits stored in memory circuit 30. (The data in register 122 can be loaded into the memory circuit at the same time as the data in memory cells 62.)
  • a comparator 124 provides an output signal on an output lead 126 when the contents of counter 120 and register 122 are equal, indicating that the last bit of configuration data has been provided by memory circuit 30. This signal causes buffers 51 and 68 to be tri-stated.
  • address select circuit 54 contains an address counter 58a and an address decoder 58b. (Counter 58a is reset by the reset signal on lead 58 and incremented by the signal on lead 52.)
  • comparator 124 compares the address in counter 58a with the contents of register 122 to determine when the last bit of data has been provided to the FPGAs.
  • a circuit 128 detects the presence of this code value and asserts an output signal on a lead 130 that tri-states buffers 51 and 66. In this way, the code value is programmed into memory cells 62 to mark the location of the last bit of configuration data.
  • Figure 8b illustrates a variation of the circuit Fig. 8a in which FPGAs 37a to 37c provide INIT signal ⁇ on output leads 39a to 39c, respectively.
  • the circuits driving leads 39a to 39c are open drain, and leads 39a to 39c are "AND-tied".
  • FPGAs 37a to 37c provide INIT signals when they require and are ready to receive configuration data as described above.
  • Each of FPGAs 37a to 37c also monitors leads 39a to 39c, and are put into configuration mode if any one of the other FPGAs assert an INIT signal.
  • Fig. 9 shows another embodiment of my invention containing an optional memory circuit 30b.
  • two or more memories such as memories 30a and 30b can be cascaded.
  • data output leads 34a and 34b are coupled together to drive the data input lead of FPGA 37a.
  • memory circuit 30a asserts a deselect signal on a lead 77 that deselects memory circuit 30b, causing memory circuit 30b to tri-state the buffer driving output lead 34b.
  • Memory circuit 30a then shifts the data stored therein onto lead 34a.
  • memory circuit 30a When the last bit of data from memory circuit 30a has been shifted out onto lead 34a, memory circuit 30a tri-states the buffer driving output lead 34a, and asserts a select ⁇ ignal on lead 77, which causes memory circuit 30b to begin sending data via lead 34b to FPGA 37a. In one embodiment, this is done under control of the clock signal provided on clock lead 35a by memory circuit 30a.
  • memory circuit 30b generates its own clock signal on a clock lead tied to lead 35a.
  • memory circuit 30b tri-states its clock output lead, whereas when memory circuit 30b is providing data, memory circuit 30a tri-states its clock lead.
  • an active signal is asserted on leads 38a to 38c. These leads are AND- tied, and are used to deselect memory circuits 30a and 30b upon completion of configuration. While Fig. 9 illustrates two memory circuits 30a, 30b, it should be noted that other numbers of ⁇ erial memory circuits can be used.
  • Fig. 10 illustrates a variation of my invention in which memory circuit 30 is used to configure FPGAs 37a' , 37b' and 37C .
  • memory circuit 30 upon power-up, memory circuit 30 sends clock and data signals to FPGAs 37a' to 37c' via leads 34 and 35.
  • FPGA 37a' and FPGA 37b' communicate inactive signals on leads 78a and 78b, respectively thereby causing FPGA 37b' and 37c' to ignore the clock and data signals on leads 35 and 34.
  • FPGA 37a' then uses the data signals from memory circuit 30 to configure itself.
  • FPGA 37a' When FPGA 37a' is done configuring itself, it holds lead 78a active, which causes FPGA 37b' to receive the data and clock signals from memory circuit 30 via leads 34 and 35 and use the data to configure itself. When FPGA 37b' is done being configured, it holds lead 78b active, and FPGA 37c' begins storing data from lead 34. As in the embodiments of Figs. 8 and 9, output leads 38a' to 38c' of FPGAs 37a' to 37c' are AND-tied together, and go active when all FPGAs are done configuring themselves, which in turn causes memory circuit 30 to tri-state the buffers driving its clock and data output leads.
  • FPGA 37a' includes an input lead corresponding to the input lead in FPGA 37b' coupled to lead 78a. This input lead in FPGA 37a' is tied active, causing FPGA 37a' to make use of the configuration data provided by memory circuit 30 at the start of configuration.
  • Fig. 10 shows three FPGAs being configured, this technique can be used to configure other numbers of FPGAs.
  • Fig. 11 illustrate ⁇ another embodiment of the invention which uses a parallel memory integrated circuit 80 instead of serial memory circuit 30.
  • memory circuit 80 provides to FPGA 81 words of n bits of data at a time via a data bus 82. (Typically, n equals 8.)
  • memory circuit 80 Prior to configuration (e.g. upon power-up or system reset) , memory circuit 80 asserts a reset signal on a line 83, indicating to FPGA 81 that configuration is about to commence.
  • Memory circuit 80 then provides a series of words of data on data bus 82, and a series of write control signals on a write control line 84.
  • FPGA 81 responds to the write control signals by loading data from bus 82 into the configuration memory cells within FPGA 81.
  • FPGA 81 When FPGA 81 is done being configured, it asserts a signal on a line 85, thereby causing memory circuit 80 to tri-state the buffers driving data bus 82 and write control line 84.
  • Fig. 12 schematically illustrates memory circuit 80.
  • Memory circuit 80 includes a clock generator 90 which provides a clock signal on a clock lead 92 to an address select circuit 94.
  • a reset control circuit 96 applies a pulse to an address select circuit 94 via a lead 97, which asserts an active signal on a ⁇ elect lead 98a, thereby causing data from a first row of memory cells 100a to be provided to a tri-state driver circuit 102.
  • Driver circuit 102 drives data bus 82 of memory 80.
  • Clock generator 90 provide ⁇ the write control signal on line 84 via a tri-state buffer 106.
  • clock generator 90 applies a clock signal on lead 92, causing address select circuit 94 to hold lead 98a inactive, and to assert an active signal select lead 98b.
  • the active signal on lead 98b causes data from memory cells 100b to be provided to driver circuit 102, which in turn drives this data onto data bus 82.
  • Another write control signal is then applied to lead 84. In this way, data is provided to FPGA 81 until configuration is complete.
  • FPGA 81 asserts a signal on lead 85, which causes a tri-state control circuit 108 to tri-state buffer 106 and driver circuit 102.
  • the signal on lead 84 goes active every time a word of data is ready on line 82.
  • the timing for the signal on lead 84 is similar to a write strobe signal used in the asynchronou ⁇ peripheral mode configuration de ⁇ cribed on pages 2-40 and 2-41 in the Xilinx data book.
  • the frequency of the signal on lead 84 can be n times the frequency of the signal on lead 92, where n i ⁇ the width of data bu ⁇ 82. Thu ⁇ , the signal on lead 84 is used by FPGA 81 in a manner similar to the clock signal in the synchronous peripheral mode configuration described on pages 2-38 and 2-39 of the Xilinx Data Book.
  • Fig. 13 illustrates a variation of the structure of Fig. 12, in which a plurality of FPGAs 81a, 81b, and 81c are configured with data from memory circuit 80.
  • FPGA 81a includes a serial output lead 110a for providing serial data from FPGA 81a to FPGA 81b and FPGA 81b contains a serial output lead
  • FPGAs 81a to 81c also receive a clock signal from memory circuit 80 via a clock lead 112.
  • FPGA 81a includes a shift register. After FPGA 81a is done configuring itself, it starts shifting data received from memory circuit 80 onto serial output lead 110a. The timing for shifting out data onto lead 110 is controlled by the clock ⁇ ignal on lead 112, generated by memory circuit 80.
  • FPGA 81b then configures itself with data received from lead 110a. As soon as FPGA 81b is done configuring itself, it shift ⁇ configuration data out onto lead 110b ⁇ o FPGA 81c can be configured. Thu ⁇ , FPGA 81a receive ⁇ it ⁇ configuration data in parallel whereas FPGAs 81b and 81c receive their configuration data in series.
  • FPGAs 81a to 81c include output leads 85a to 85c that are AND-tied together and used to indicate to memory circuit 80 that configuration is complete.
  • Fig. 13 show ⁇ three FPGAs being configured using this technique, other number ⁇ of FPGAs can be configured in this manner.
  • Fig. 14 illustrate ⁇ a variation of the ⁇ tructure of Fig. 13 in which a plurality of FPGAs 81a', 81b' are each coupled to an a ⁇ sociated lead of data bus 82'.
  • each FPGA 8la', 81b' receives a serial data stream from memory circuit 80' via its associated lead 82a', 82b' of bus 82', and uses that data to configure itself.
  • each FPGA 81a', 81b' also receives the write control signal from lead 84 to control timing. In this way, FPGAs 81a',
  • each FPGA 81a', 81b' asserts a signal on its as ⁇ ociated lead 85a', 85b'.
  • Lead ⁇ 85a' and 85b' are AND-tied together and are coupled to memory circuit 80'.
  • Memory circuit 80' re ⁇ pond ⁇ to the ⁇ ignal on leads 85a'and 85b' by tri-stating the circuitry that drives bus 82'.
  • Fig. 14 shows only two FPGAs being programmed in thi ⁇ manner, data bu ⁇ 82' can have more than two bus lead ⁇ (typically bus 82' contains eight bus leads) , and thus other numbers of FPGAs can be configured in parallel using this technique.
  • Fig. 15 illustrates an embodiment of the invention in which three FPGAs 81a" to 81c" are coupled to memory circuit 80 via a data bus 82" and write control lead 83".
  • FPGAs 81a" and 81b" assert inactive signal ⁇ on leads 114a and 114b, respectively.
  • FPGA 81a" receives configuration data from bus 82" and configure ⁇ itself in response thereto.
  • FPGA 81a" is done configuring itself, it holds lead 114a active and thereafter ignores the data on bus 82".
  • FPGA 81b” responds to the signal on lead 114a by using the data from bus 82" to configure itself.
  • FPGA 81b" is done configuring itself it holds lead 114b active, and thereafter ignores the data on bus 82".
  • FPGA 81c" then use ⁇ the data on bus 82" to configure itself.
  • the FPGAs in the embodiments of Figs. 9 to 15 can provide INIT signal ⁇ to initialize or permit configuration a ⁇ di ⁇ cu ⁇ ed above in relation to Fig ⁇ 5b and 8b.
  • various programmable logic devices having reprogrammable memory cells can be u ⁇ ed in accordance with my invention.
  • EEPROM or SRAM- based PLA and PAL-type architecture devices can be used with a memory in accordance with my invention.
  • PAL and "PLA” are well known terms. See, for example, the LSI Databook, published by Monolithic Memorie ⁇ , Inc. in 1985, incorporated herein by reference, and in particular, chapter 5.
  • the memories described above receive a signal from the FPGA or FPGAs indicating when configuration is complete (e.g. the signal on leads 38 and 85) .
  • the memories are programmed with information indicative of the location of the last bit of data needed to configure the FPGAs.
  • memory circuits 30 and 80 contain circuitry that tri-states clock and data output lines (or data and write control lines) without having to receive a signal from the FPGAs indicative of completion of configuration.
  • memory circuit 30 provides a signal on line 36 indicating when configuration is about to commence.
  • line 36 need not be present and FPGA 37 can rely on a clock pulse on line 35 to indicate when configuration is about to commence.
  • lead 83 is eliminated, and FPGAs 81 rely on a write control signal on lead 84 for an indication as to when configuration is to begin.
  • memory circuit 80 can be programmable to either use the clock signal generated by clock generator 90 or to receive an externally generated clock circuit, e.g. as in Fig. 7b.
  • the memory circuit can contain means for determining when the last word of data has been provided to an FPGA, similar to Figs. 7c to 7e. The memory circuit can then communicate a DONE ⁇ ignal to the FPGA or FPGAs receiving the configuration data.
  • Fig. 7a The structures depicted in Fig. 7a are typically formed within a single integrated circuit. Similarly, the structures in the embodiments of Figs. 7b to 7e and
  • the FPGAs can be configured in a number of the ways described above.
  • the FPGAs contain one or more mode control pins which receive signals indicating how the FPGAs are to be configured (e.g. in series or parallel) .
  • the FPGAs and memories can be constructed using any appropriate technology, e.g. NMOS, PMOS, CMOS, bipolar, etc.
  • the FPGAs can route data from their pins to configuration memory cell ⁇ a ⁇ di ⁇ cussed above or as described in U.S. Patent Application Serial No. 08/223,247, filed April 1, 1994 by Erickson, et al., incorporated herein by reference.
  • Other modifications of the invention will be apparent to those of ordinary skill in the art in light of the foregoing description.

Abstract

A memory device controls the flow of data from the memory device to a configurable logic device. This is in contrast to circuits in which a configurable logic device generates a clock signal that controls the flow of data from a memory device to a configurable logic device. In one embodiment, the configurable logic device is a field programmable gate array ('FPGA'). The memory device can provide the configuration data on a serial output lead or a parallel data bus.

Description

SYSTEM COMPRISING FIELD PROGRAMMABLE GATE ARRAY AND INTELLIGENT MEMORY
BACKGROUND OF THE INVENTION "The Programmable Logic Data Book" ("Xilinx Data Book"), published by Xilinx, Inc. ("Xilinx") in 1994, describes field programmable gate arrays ("FPGAs") manufactured and sold by Xilinx. (The Xilinx Data Book is incorporated herein by reference.) These FPGAs are capable of retrieving configuration data from a serial or parallel memory. For example, the Xilinx Data Book discusses a circuit in which an FPGA receives configuration data from a serial PROM when the FPGA is in a master serial configuration mode, e.g. as shown in Fig. 1. Referring to Fig. 1, an FPGA 1 generates a clock signal on a clock signal line 2. This clock signal is received by a serial PROM 3 , which generates in response thereto a serial data stream on an output line 4. The serial data is received by FPGA 1, which becomes configured in response thereto. When FPGA 1 is done configuring itself, it asserts a DONE signal on line 5, indicating that configuration is complete. This signal deselects PROM 3.
A variation of this system is shown in Fig. 2. The Fig. 2 system includes first and second FPGAs la and lb. During system initialization, FPGA la sends clock signals on line 2 to both PROM 3 and FPGA lb. PROM 3 responds to the clock signals by providing data signals to FPGA la on line 4. During configuration, FPGA la is in the "master serial configuration mode" and FPGA lb is in the "slave configuration mode". In this variation, when FPGA la is done configuring itself, it continues to send clock signals to serial PROM 3 and FPGA lb. Serial PROM 3 thus continues to send data to FPGA la via line 4. This data is passed from FPGA la to FPGA lb via a line 7. FPGA lb takes the data from line 7 and uses that data to configure
l- itself. FPGAs la and lb include open drain output buffers which drive leads 5a and 5b, respectively. Leads 5a and 5b are "AND-tied" together. When FPGAs la and lb are both done being configured, the signal on leads 5a and 5b goes high, indicating that both FPGAs are done being configured, and deselecting PROM 3.
Another variation of FPGA configuration is shown in Fig. 3, in which an FPGA 10 communicates address signals via an address bus 11 to a parallel EPROM 12. EPROM 12 responds by providing data signals on a data bus 13 (typically 8 bits wide) . These data signals are received by FPGA 10, which configures itself in accordance with this data. This type of programming mode is known as a master parallel configuration mode. Instead of relying on the FPGA to generate clock signals which are applied to a PROM during serial configuration mode, or relying on the FPGA to generate address signals during master parallel configuration mode, it is known to rely on an intelligent device, such as a microprocessor, to generate clock and/or address signals. Thus, as shown in Fig. 4, it is known to use a microprocessor 20 to address EPROM 21 via address lines 22. Microprocessor 20 retrieves configuration data via data bus 23, and passes that configuration data to FPGA 24 via a serial data line 25. Timing is controlled by a clock signal communicated on a clock signal line 26 by microprocessor 20. When FPGA 24 is programmed in this manner, it is in the slave serial mode. Other known modes for configuring FPGAs include a peripheral asynchronous mode and a peripheral synchronous mode. In these modes an intelligent device such as a microprocessor writes configuration data to the FPGA, typically a byte at a time. (See pages 2-38 to 2-41 of the Xilinx Data Book) .
Xilinx FPGAs can be configured in each of the foregoing modes. Each of these modes has its own advantages and disadvantages. Using a serial PROM is often advantageous because serial PROMs have a small number of pins and are relatively inexpensive. To use a serial PROM, at least one FPGA in the system must be capable of generating a clock signal for causing the serial PROM to provide configuration data. Since FPGAs are mass-produced, and support all these configuration modes, they all contain clock and oscillator circuitry, even though the devices in slave serial configuration mode never use this circuitry.
In master parallel mode, the FPGA must also have oscillator and clock circuitry, and circuitry for generating addresses. In any configuration mode that uses an intelligent device such as a microprocessor, the resources of that microprocessor must be used to initialize any FPGAs in the system.
SUMMARY
An FPGA system in accordance with this invention includes a circuit having a memory and capable of generating the necessary signals to program an FPGA integrated circuit without requiring external intelligent circuitry such as a microprocessor and without requiring the FPGA to contain clock or oscillator circuitry. In one embodiment, the memory circuit generates a clock signal and a serial data signal which is received by an FPGA during configuration. In another embodiment, the memory circuit sends several bits of configuration data in parallel to the FPGA (typically one byte at a time) during configuration. In either event, the resources of a microprocessor are not required, nor is it necessary for the FPGA to contain clock and oscillator circuitry. In one embodiment, the memory is an integrated circuit. The memory can employ PROM, EPROM, EEPROM, fuse, antifuse, ROM or other technology.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 schematically illustrates an FPGA in master serial configuration mode.
Fig. 2 schematically illustrates one FPGA in master serial configuration mode and one FPGA in slave serial configuration mode.
Fig. 3 schematically illustrates an FPGA during parallel configuration.
Fig. 4 schematically illustrates an FPGA being configured by a microprocessor. Fig. 5a schematically illustrates an FPGA being configured by a memory circuit in accordance with a first embodiment of the invention.
Fig. 5b illustrates a variation of the embodiment of Fig. 5a. Fig. 6 illustrates an FPGA.
Fig. 7a is a block diagram of the memory circuit of Fig. 5.
Fig. 7b is a block diagram of an alternate embodiment of the memory circuit of Fig. 7a including means for receiving an externally generated clock signal.
Fig. 7c to 7e are block diagrams of other embodiments of a memory circuit including means for ascertaining when the last bit of configuration data has been provided to an FPGA.
Fig. 8a schematically illustrates a plurality of FPGAs being configured by a memory circuit in accordance with a second embodiment of the invention. Fig. 8b schematically illustrates a variation of the embodiment Fig. 8a.
Fig. 9 schematically illustrates a plurality of FPGAs being configured by a pair of memory circuits in accordance with a third embodiment of the invention.
Fig. 10 schematically illustrates a plurality of FPGAs being configured by a memory circuit in accordance with a fourth embodiment of the invention.
Fig. 11 schematically illustrates an FPGA being configured by a parallel memory accordance with a fifth embodiment of the invention.
Fig. 12 is a block diagram of the parallel memory of Fig. 11.
Fig. 13 schematically illustrates a plurality of FPGAs being configured by a parallel memory in accordance with a sixth embodiment of the invention.
Fig. 14 schematically illustrates a seventh embodiment of the invention using a parallel memory having a data bus in which each line of the data bus is connected to an associated FPGA.
Fig. 15 schematically illustrates an eighth embodiment of the invention in which three FPGAs receive configuration data in parallel.
DETAILED DESCRIPTION
Referring to Fig. 5a, a memory integrated circuit 30 receives power signals Vcc (typically 5 volts) , ground and an optional reset signal on lines 31, 32 and 33, respectively. The reset signal can be generated by the circuitry in which the system of Fig. 5a is incorporated. In one embodiment, the reset signal is generated by a host microprocessor (not shown) , or a control button on the system.
Memory circuit 30 includes a data output signal lead 34, a clock output signal lead 35, and a reset signal output signal lead 36. Upon power up (or when the signal on reset signal line 33 goes active) , memory circuit 30 asserts a reset signal on lead 36, which is received by an FPGA integrated circuit 37. This reset signal puts FPGA 37 in a "configuration mode". During configuration, memory circuit 30 provides clock and data signals on leads 35 and 34, which are received by FPGA 37 and used to configure FPGA 37. When FPGA 37 is done configuring itself, it asserts a DONE signal on a lead 38, indicating that configuration is complete, and causing memory circuit 30 to cease transmitting configuration data.
In one embodiment, memory circuit 30 is an EPROM, but other memory technologies (fuses, antifuses, SRAMs, EEPROMs, mask-programmed ROMs, etc.) can also be used.
FPGA 37 is typically an integrated circuit comprising an array of configurable logic elements. These elements can have a structure such as the logic element structure used in the Xilinx XC2000, XC3000, XC4000 or XC5000 families of devices. These elements can also have a structure such as that disclosed in U.S. Patent Re 34,363 (incorporated herein by reference) or the structure used in the Flex series of FPGAs manufactured by Altera Corporation.
Configuration data can be routed from the FPGA serial data input lead (coupled to lead 34) to configuration memory cells within the FPGA in the same manner as in the Xilinx or Altera devices, or as described the '363 patent. However, in accordance with this invention, timing is typically controlled by the clock signal generated by memory circuit 30.
The exact details of the FPGA used in accordance with the invention are not critical. Generally, an FPGA contains an array of configurable logic elements, e.g. as shown in '363 Patent Figs. 2, 3a or 3b, or Xilinx Data Book Fig. 1 (page 2-20 of the Xilinx Data Book) . Fig. 6 shows a block diagram of an example of an FPGA, which contains an array of configurable logic elements, or cells 40, arranged in an array 41 of rows and columns. Each cell 40 can be programmed, or configured, to perform any of a number of logic functions. Interspersed about cells 40 is a wiring grid 42. The input and output leads of cells 40 can be programmably electrically coupled to the wires in grid 42. In one embodiment, this programmable electrical coupling is accomplished using pass transistors or tri¬ state buffers driven by SRAM memory cells. However, other techniques can be used. Fig. 6 shows one of the cells (cell 40a) coupled to wiring grid 42 via pass transistors 44. The other cells 40 are also coupled to the wiring grid via pass transistors and each cell input or output line may be coupled to more than one wire of grid 42, but this is not shown in Fig. 6 for the sake of clarity. Although grid 42 is illustrated as showing three wires between adjacent rows and columns of cells 40, other numbers of wires are typically provided between adjacent rows and columns of cells. Also, although the wires in grid 42 are shown as extending the entire length and width of the array, typically, wires within grid 42 have varying lengths, some extending a short distance, some extending a longer distance.
Although not shown for the sake of clarity, the horizontal wires in grid 42 are typically programmably connected to the vertical wires in grid 42 at some of the locations where the horizontal and vertical wires cross.
Surrounding array 41 is a set of programmable I/O cells 46, which can be programmably connected to wires 42. I/O cells 46 can receive signals from the I/O pins of the FPGA, and provide those signals onto selected wires within grid 42. In addition, I/O cells 46 can receive signals from grid 42 and provide those signals to the I/O pins. In this way, signals from outside the FPGA can be communicated via I/O cells 46 to wiring grid 42, and to selected cells 40 within array 41. Output signals from the various cells can be communicated via grid 42 to other cells 40 within array 41, and/or to I/O cells 46 via grid 42.
The programmable interconnections between the various structures shown in Fig. 6 and the configuration of cells 40 are typically controlled by SRAM memory cells within the FPGA (not shown) . The SRAM memory cells within the FPGA can be arranged as a shift register (see the '363 Patent) or arranged as described in the Xilinx Data Book, or as in the Xilinx XC2000, XC3000, XC4000 or XC5000 family of circuits, or as in the Altera Flex circuits. However, in lieu of using SRAM memory cells, other reprogrammable memory cells, e.g. EEPROM memory cells can be used in an FPGA in accordance with the invention.
Fig. 7a is a block diagram of memory circuit 30. As shown in Fig. 7a, a clock generator circuit 50 provides a clock signal on lead 35 via a tri-state buffer 51. (As mentioned above, the clock signal on lead 35 is used by FPGA 37 during configuration.)
Clock generator circuit 50 can contain a conventional oscillator. For example, in one embodiment, clock generator 50 may contain a multivibrator. Alternatively, clock generator 50 can contain an odd number of inverting circuits connected in the form of a feedback loop. Alternatively, clock generator 50 can be coupled to a crystal, LC circuit or other structure external to memory circuit 30. Clock generator 50 also provides a clock signal on a lead 52 which drives a sequential address select circuit 54. Upon power-up or receipt of a signal on reset line 33, a reset control circuit 56 applies a reset signal to FPGA 31 via lead 36, and a reset signal to address select circuit 54 via a lead 58. The reset signal on lead 58 causes circuit 54 to assert an active output signal on a select line
60a, which in turn causes the data in a selected row of memory cells 62a to be communicated via lines 64 to a shift register 66. The data from shift register 66 is shifted out onto data output lead 34 via a lead 67 and a tri-state buffer 68. The timing of this shifting function is controlled by a clock signal on a clock line 70 provided by clock generator circuit 50. The clock signals on lines 35 and 70 have identical frequencies. When all of the data from row 60a has been shifted out from shift register 66, clock generator 50 provides a clock signal to address select circuit 54 via clock line 52. Address select circuit 54 responds to this clock signal by holding select line 60a inactive and asserting an active output signal on the next select line 60b, which in turn causes data from a second row of memory cells 62b to be loaded into shift register 66. The process thus repeats itself until either a) all of the data from memory cells 66 has been shifted out; or b) FPGA 37 asserts a signal on line 38 indicating that configuration is complete. When memory circuit 30 receives this signal from line 38, a tri-state control circuit 71 tri-states buffers 51 and 68. In this way, memory circuit 30 controls the configuration of FPGA 37. (Because buffers 51 and 68 are tri-stated, the input pins of FPGA 37 driven by leads 34 and 35 during configuration can be used for other tasks after configuration is complete.
Fig. 7b illustrates an alternative embodiment of a memory circuit in accordance with my invention comprising a multiplexer 72 and a control lead 73. In this embodiment, when the signal on control lead 73 is low, multiplexer 72 passes clock signals from clock generator circuit 50 to shift register 66 via lead 70 as described above. These clock signals control the shifting of data from shift register 66. In addition, the clock signals from clock generator 50 are coupled to a divide by m circuit 74 via multiplexer 72. The output signal from divide by m circuit drives address selector circuit 54. Shift register 66 contains m bits, where m is an integer, e.g. 8. Thuε, address select circuit 54 is clocked by divide by m circuit 74 every time m bits from shift register 66 are provided to output lead 34, i.e. every time shift register 66 is emptied of its contents.
When the signal on control lead 73 is high clock generator circuit 50 is disabled, tri-state buffer 51 is put in a tri-state mode, and lead 35 serves as a clock input lead to memory circuit 30. In this mode, the clock signal received on lead 35 is coupled to shift register 66 via multiplexer 72 and lead 70. In addition, as mentioned above, the output signal from multiplexer 72 drives divide by m circuit 74, which is turn clocks address selector circuit 54. In this way, the memory circuit can use either an internally generated clock signal (from clock generator 50) or an externally generated clock signal (received from lead 35) , depending on the state of the signal on control lead 73. Of importance, the signal on control lead 73 can be received via an input pin from a device external to memory circuit 30. Alternatively, the signal on control lead 73 can be provided by a memory cell within memory circuit 30 that is programmed at the same time as the memory cells within rows 62a-62n.
Although Fig. 7b uses lead 35 as a bi-directional lead that can either receive or provide a clock signal, in other embodiments, lead 35 is not bi-directional, and a separate lead is used to receive an externally generated clock signal.
When power is first applied to the circuit of Fig. 5a, it may take time before the voltage levels within FPGA 37 reach proper values. Further, FPGA 37 may have to reset some or all of its internal memory cells to a known state prior to configuration. Thus, in one embodiment, memory circuit 30 provides a time delay between power-up and the time memory circuit 30 begins to provide configuration data, to ensure that FPGA 37 is ready to receive that configuration data. Alternatively, as shown in Fig. 5b, FPGA 37 may have an output lead 39 coupled to memory circuit 30. In this embodiment, memory circuit 30 commences sending configuration data upon receipt of an INIT signal on lead 39. The INIT signal is provided by FPGA 37 to indicate that it is ready to receive data.
Alternatively, if there is a momentary drop in the voltage applied to the Vcc pin of FPGA 37, FPGA 37 can contain circuitry which determines whether there is a risk that configuration data have been lost. In the event of such a risk, FPGA 37 can assert the INIT signal at that time to start reconfiguration.
Fig. 8a illustrates a variation of the embodiment of Fig. 5a, in which three FPGAs 37a, 37b and 37c are configured. All three devices receive the clock signal from memory 30 via lead 35. Of importance, FPGAs 37a and 37b include serial output leads 76a and 76b, respectively. At the start of configuration, memory circuit 30 provides preamble data to FPGA 37a via line 34, including a length count indicating how many bits of configuration data are going to be provided to FPGAs 37a-37c. This preamble data is stored in FPGA 37a, and passed on to FPGAs 37b and 37c via lines 76a and 76b, respectively. Thereafter, FPGA 37a receives configuration data from memory 30 via lead 34 and uses that data to configure itself, but holds its serial output lead 76a high. As soon as FPGA 37a is done configuring itself, FPGA 37a begins to pass the serial data from lead 34 to lead 76a. This data is then used by FPGA 37b to configure itself. While FPGA 37b is configuring itself, it holds serial output lead 76b high. As soon as FPGA 37b is done configuring itself, it begins to pass the serial data from lead 76a to lead 76b. FPGA 37c receives and uses the data from lead 76b to configure itself. Of importance, each FPGA 37a to 37c includes a counter which increments every time a clock signal is received on lead 35. When the number of counted clock signals equals the length count, then all of FPGAs 37a to 37c know that configuration is complete. Each FPGA 37a, 37b, 37c includes an associated open drain output line 38a, 38b, 38c which are "AND-tied" and coupled to memory circuit 30. When FPGAs 37a, 37b and 37c have counted a number of clock pulses equal to the length count, all of lines 38a, 38b and 38c are held active (e.g. high), which then causes memory circuit 30 to tri-state buffers 51 and 68 (Fig. 7a) , and to cease sending configuration data to the FPGAs. While Fig. 8a shows three FPGAs, the same principle can be applied to any other number of FPGAs. Of importance, in Fig. 8a, it is unnecessary that FPGAs 37a-37c contain clock or oscillator circuits. In an alternative variation of the embodiment of the Fig. 8a, FPGA 37a turns off the transistor driving open drain lead 38a when FPGA 37a is done being loaded with configuration data, FPGA 37b turns off the transistor driving lead 38b when FPGA 37b is done being loaded with configuration data, and so forth. In this alternative, FPGAs 37a to 37c do not rely on counting clock signals to determine when to assert a signal on leads 38a to 38c.
In another alternative, memory circuit 30 includes a counter 120 (Fig. 7c) that is reset by the signal provided on lead 58 by reset control circuit 56 at the start of configuration. Counter 120 counts the clock pulses on lead 70. Memory circuit 30 also includes a register 122 that contains the number of configuration bits stored in memory circuit 30. (The data in register 122 can be loaded into the memory circuit at the same time as the data in memory cells 62.) Of importance, a comparator 124 provides an output signal on an output lead 126 when the contents of counter 120 and register 122 are equal, indicating that the last bit of configuration data has been provided by memory circuit 30. This signal causes buffers 51 and 68 to be tri-stated. In this way, memory circuit 30 determines when configuration is complete without relying on a signal from the FPGAs. In another embodiment (Fig. 7d) , address select circuit 54 contains an address counter 58a and an address decoder 58b. (Counter 58a is reset by the reset signal on lead 58 and incremented by the signal on lead 52.) In Fig. 7d, comparator 124 compares the address in counter 58a with the contents of register 122 to determine when the last bit of data has been provided to the FPGAs.
In another embodiment (Fig. 7e) , when a word of data equalling a code value (for example, all ones) is loaded into shift register 66, a circuit 128 detects the presence of this code value and asserts an output signal on a lead 130 that tri-states buffers 51 and 66. In this way, the code value is programmed into memory cells 62 to mark the location of the last bit of configuration data.
Figure 8b illustrates a variation of the circuit Fig. 8a in which FPGAs 37a to 37c provide INIT signalε on output leads 39a to 39c, respectively. Of importance, the circuits driving leads 39a to 39c are open drain, and leads 39a to 39c are "AND-tied". FPGAs 37a to 37c provide INIT signals when they require and are ready to receive configuration data as described above. Each of FPGAs 37a to 37c also monitors leads 39a to 39c, and are put into configuration mode if any one of the other FPGAs assert an INIT signal.
Fig. 9 shows another embodiment of my invention containing an optional memory circuit 30b. Of importance, if a design calls for more data than can be stored in one serial memory, two or more memories such as memories 30a and 30b can be cascaded. In Fig. 9, data output leads 34a and 34b are coupled together to drive the data input lead of FPGA 37a. Upon power-up, memory circuit 30a asserts a deselect signal on a lead 77 that deselects memory circuit 30b, causing memory circuit 30b to tri-state the buffer driving output lead 34b. Memory circuit 30a then shifts the data stored therein onto lead 34a. When the last bit of data from memory circuit 30a has been shifted out onto lead 34a, memory circuit 30a tri-states the buffer driving output lead 34a, and asserts a select εignal on lead 77, which causes memory circuit 30b to begin sending data via lead 34b to FPGA 37a. In one embodiment, this is done under control of the clock signal provided on clock lead 35a by memory circuit 30a.
In an alternative embodiment, memory circuit 30b generates its own clock signal on a clock lead tied to lead 35a. When memory 30a is providing data, memory circuit 30b tri-states its clock output lead, whereas when memory circuit 30b is providing data, memory circuit 30a tri-states its clock lead. As in the previous embodiment, when all of FPGAs 37a to 37c are done being configured, an active signal is asserted on leads 38a to 38c. These leads are AND- tied, and are used to deselect memory circuits 30a and 30b upon completion of configuration. While Fig. 9 illustrates two memory circuits 30a, 30b, it should be noted that other numbers of εerial memory circuits can be used.
Fig. 10 illustrates a variation of my invention in which memory circuit 30 is used to configure FPGAs 37a' , 37b' and 37C . In Fig. 10, upon power-up, memory circuit 30 sends clock and data signals to FPGAs 37a' to 37c' via leads 34 and 35. Initially, FPGA 37a' and FPGA 37b' communicate inactive signals on leads 78a and 78b, respectively thereby causing FPGA 37b' and 37c' to ignore the clock and data signals on leads 35 and 34. FPGA 37a' then uses the data signals from memory circuit 30 to configure itself. When FPGA 37a' is done configuring itself, it holds lead 78a active, which causes FPGA 37b' to receive the data and clock signals from memory circuit 30 via leads 34 and 35 and use the data to configure itself. When FPGA 37b' is done being configured, it holds lead 78b active, and FPGA 37c' begins storing data from lead 34. As in the embodiments of Figs. 8 and 9, output leads 38a' to 38c' of FPGAs 37a' to 37c' are AND-tied together, and go active when all FPGAs are done configuring themselves, which in turn causes memory circuit 30 to tri-state the buffers driving its clock and data output leads.
In one embodiment, FPGA 37a' includes an input lead corresponding to the input lead in FPGA 37b' coupled to lead 78a. This input lead in FPGA 37a' is tied active, causing FPGA 37a' to make use of the configuration data provided by memory circuit 30 at the start of configuration.
Although Fig. 10 shows three FPGAs being configured, this technique can be used to configure other numbers of FPGAs.
Fig. 11 illustrateε another embodiment of the invention which uses a parallel memory integrated circuit 80 instead of serial memory circuit 30. In Fig. 11, memory circuit 80 provides to FPGA 81 words of n bits of data at a time via a data bus 82. (Typically, n equals 8.) Prior to configuration (e.g. upon power-up or system reset) , memory circuit 80 asserts a reset signal on a line 83, indicating to FPGA 81 that configuration is about to commence. Memory circuit 80 then provides a series of words of data on data bus 82, and a series of write control signals on a write control line 84. FPGA 81 responds to the write control signals by loading data from bus 82 into the configuration memory cells within FPGA 81. When FPGA 81 is done being configured, it asserts a signal on a line 85, thereby causing memory circuit 80 to tri-state the buffers driving data bus 82 and write control line 84.
Fig. 12 schematically illustrates memory circuit 80. Memory circuit 80 includes a clock generator 90 which provides a clock signal on a clock lead 92 to an address select circuit 94. Upon reset or power-up, a reset control circuit 96 applies a pulse to an address select circuit 94 via a lead 97, which asserts an active signal on a εelect lead 98a, thereby causing data from a first row of memory cells 100a to be provided to a tri-state driver circuit 102. Driver circuit 102 drives data bus 82 of memory 80. Clock generator 90 provideε the write control signal on line 84 via a tri-state buffer 106.
Thereafter, clock generator 90 applies a clock signal on lead 92, causing address select circuit 94 to hold lead 98a inactive, and to assert an active signal select lead 98b. The active signal on lead 98b causes data from memory cells 100b to be provided to driver circuit 102, which in turn drives this data onto data bus 82. Another write control signal is then applied to lead 84. In this way, data is provided to FPGA 81 until configuration is complete. When configuration is complete, FPGA 81 asserts a signal on lead 85, which causes a tri-state control circuit 108 to tri-state buffer 106 and driver circuit 102.
In the embodiment of Fig. 12, the signal on lead 84 goes active every time a word of data is ready on line 82. Thus, the timing for the signal on lead 84 is similar to a write strobe signal used in the asynchronouε peripheral mode configuration deεcribed on pages 2-40 and 2-41 in the Xilinx data book.
Alternatively, the frequency of the signal on lead 84 can be n times the frequency of the signal on lead 92, where n iε the width of data buε 82. Thuε, the signal on lead 84 is used by FPGA 81 in a manner similar to the clock signal in the synchronous peripheral mode configuration described on pages 2-38 and 2-39 of the Xilinx Data Book. Fig. 13, illustrates a variation of the structure of Fig. 12, in which a plurality of FPGAs 81a, 81b, and 81c are configured with data from memory circuit 80. In this embodiment, FPGA 81a includes a serial output lead 110a for providing serial data from FPGA 81a to FPGA 81b and FPGA 81b contains a serial output lead
110b for providing serial data to FPGA 81c. FPGAs 81a to 81c also receive a clock signal from memory circuit 80 via a clock lead 112. Of importance, FPGA 81a includes a shift register. After FPGA 81a is done configuring itself, it starts shifting data received from memory circuit 80 onto serial output lead 110a. The timing for shifting out data onto lead 110 is controlled by the clock εignal on lead 112, generated by memory circuit 80. FPGA 81b then configures itself with data received from lead 110a. As soon as FPGA 81b is done configuring itself, it shiftε configuration data out onto lead 110b εo FPGA 81c can be configured. Thuε, FPGA 81a receiveε itε configuration data in parallel whereas FPGAs 81b and 81c receive their configuration data in series.
As with the previous embodiments, FPGAs 81a to 81c include output leads 85a to 85c that are AND-tied together and used to indicate to memory circuit 80 that configuration is complete. Although Fig. 13 showε three FPGAs being configured using this technique, other numberε of FPGAs can be configured in this manner.
Fig. 14 illustrateε a variation of the εtructure of Fig. 13 in which a plurality of FPGAs 81a', 81b' are each coupled to an aεsociated lead of data bus 82'. During configuration, each FPGA 8la', 81b' receives a serial data stream from memory circuit 80' via its associated lead 82a', 82b' of bus 82', and uses that data to configure itself. Of importance, each FPGA 81a', 81b' also receives the write control signal from lead 84 to control timing. In this way, FPGAs 81a',
81b' are simultaneouεly configured in parallel. Aε in the previouε embodimentε, when configuration is complete, each FPGA 81a', 81b' asserts a signal on its asεociated lead 85a', 85b'. Leadε 85a' and 85b' are AND-tied together and are coupled to memory circuit 80'. Memory circuit 80' reεpondε to the εignal on leads 85a'and 85b' by tri-stating the circuitry that drives bus 82'. Although Fig. 14 shows only two FPGAs being programmed in thiε manner, data buε 82' can have more than two bus leadε (typically bus 82' contains eight bus leads) , and thus other numbers of FPGAs can be configured in parallel using this technique.
Fig. 15 illustrates an embodiment of the invention in which three FPGAs 81a" to 81c" are coupled to memory circuit 80 via a data bus 82" and write control lead 83". At the start of configuration, FPGAs 81a" and 81b" assert inactive signalε on leads 114a and 114b, respectively. At the start of configuration, FPGA 81a" receives configuration data from bus 82" and configureε itself in response thereto. When FPGA 81a" is done configuring itself, it holds lead 114a active and thereafter ignores the data on bus 82". FPGA 81b" responds to the signal on lead 114a by using the data from bus 82" to configure itself. When FPGA 81b" is done configuring itself it holds lead 114b active, and thereafter ignores the data on bus 82". FPGA 81c" then useε the data on bus 82" to configure itself.
While my invention has been described with reference to specific embodiments, those skilled in the art will realize that changes can be made in form and detail without departing from the spirit and scope of my invention. For example, the FPGAs in the embodiments of Figs. 9 to 15 can provide INIT signalε to initialize or permit configuration aε diεcuεεed above in relation to Figε 5b and 8b. It iε also noted various programmable logic devices having reprogrammable memory cells can be uεed in accordance with my invention. Thus, EEPROM or SRAM- based PLA and PAL-type architecture devices can be used with a memory in accordance with my invention. ("PAL" and "PLA" are well known terms. See, for example, the LSI Databook, publiεhed by Monolithic Memorieε, Inc. in 1985, incorporated herein by reference, and in particular, chapter 5.)
Further, the memories described above receive a signal from the FPGA or FPGAs indicating when configuration is complete (e.g. the signal on leads 38 and 85) . In another embodiment, the memories are programmed with information indicative of the location of the last bit of data needed to configure the FPGAs. In this embodiment, memory circuits 30 and 80 contain circuitry that tri-states clock and data output lines (or data and write control lines) without having to receive a signal from the FPGAs indicative of completion of configuration. In the embodiment of Figs. 5a, 8a, 9 and 10, memory circuit 30 provides a signal on line 36 indicating when configuration is about to commence. In an alternative embodiment, line 36 need not be present and FPGA 37 can rely on a clock pulse on line 35 to indicate when configuration is about to commence. In like manner, in a variation of the embodiment of Figs 11 to 15, lead 83 is eliminated, and FPGAs 81 rely on a write control signal on lead 84 for an indication as to when configuration is to begin.
In one modification of the embodiment of Fig. 12, memory circuit 80 can be programmable to either use the clock signal generated by clock generator 90 or to receive an externally generated clock circuit, e.g. as in Fig. 7b.
In Fig. 12, the memory circuit can contain means for determining when the last word of data has been provided to an FPGA, similar to Figs. 7c to 7e. The memory circuit can then communicate a DONE εignal to the FPGA or FPGAs receiving the configuration data.
The structures depicted in Fig. 7a are typically formed within a single integrated circuit. Similarly, the structures in the embodiments of Figs. 7b to 7e and
12 can also be formed within a single integrated circuit.
In one embodiment, the FPGAs can be configured in a number of the ways described above. In such an embodiment, the FPGAs contain one or more mode control pins which receive signals indicating how the FPGAs are to be configured (e.g. in series or parallel) .
The FPGAs and memories can be constructed using any appropriate technology, e.g. NMOS, PMOS, CMOS, bipolar, etc. The FPGAs can route data from their pins to configuration memory cellε aε diεcussed above or as described in U.S. Patent Application Serial No. 08/223,247, filed April 1, 1994 by Erickson, et al., incorporated herein by reference. Other modifications of the invention will be apparent to those of ordinary skill in the art in light of the foregoing description.

Claims

We claim:
1. A memory integrated circuit comprising: a plurality of memory cells; a clock output signal line; a clock generator circuit for generating a first clock signal and providing said first clock signal on εaid clock output signal line; and circuitry which obtains data from said memory cells and provides said data on at leaεt one memory circuit output lead in εynchronization with said first clock signal.
2. Circuit of Claim 1 wherein said memory integrated circuit is part of a logic system comprising a programmable logic device, said memory integrated circuit providing configuration data to said programmable logic device.
3. Circuit of Claim 2 wherein said programmable logic device is an FPGA, and wherein memory integrated circuit commences providing said data to said FPGA upon system power-up.
4. Circuit of Claim 3 wherein said FPGA comprises means for communicating an output εignal indicating when configuration of εaid FPGA iε complete, and wherein said memory integrated circuit comprises means for receiving said output εignal, εaid memory integrated circuit ceaεing providing said data in response to said output signal.
5. Circuit of Claim 4 wherein said FPGA comprises a serial output lead, εaid εyεtem further compriεing a εecond FPGA having a data input lead coupled to εaid εerial output lead and a clock input lead coupled to said clock output signal line.
6. Circuit of Claim 2 wherein said programmable logic device comprises means for communicating to said memory integrated circuit when said programmable logic device is in a state such that it can receive data from said memory integrated circuit.
7. Circuit of Claim 1 wherein said memory integrated circuit further comprises a clock input lead for receiving a second clock signal from a source external to εaid memory integrated circuit, and wherein said circuitry is operable in a mode wherein said data is provided on said memory circuit output lead in synchronization with said second clock signal.
8. Circuit of Claim 1 wherein said clock output signal line is bi-directional, and said memory integrated circuit is operable in a mode in which said memory integrated circuit can receive clock signals from a source external to said memory integrated circuit and provide data on said memory circuit output lead in synchronization with said received clock signals.
9. Circuit of Claim 1 wherein said memory integrated circuit further comprises means for indicating when a last selected bit from said memory cells has been provided by said memory integrated circuit.
10. Circuit of Claim 9 further comprising tri-state buffers for driving said clock output signal line and said memory circuit output lead, and wherein said means for indicating causes said tri-state buffers to go into a tri-state mode when said last selected bit has been provided by said memory integrated circuit.
11. Circuit of Claim 1 wherein said memory integrated circuit is a serial memory that provides a serial data stream on said memory circuit output lead.
12. Circuit of Claim 1 wherein said memory integrated circuit comprises: a power input pin; and means for detecting when power is applied to said power input pin and causing said clock generator to begin generating clock signals in response thereto.
13. System comprising: a memory integrated circuit for providing data on a data bus and for generating a write control signal and providing said write control εignal on a write control line; and a programmable logic device for receiving said data and said write control signal and using said data to configure itself.
14. System of Claim 13 wherein said memory integrated circuit comprises a clock oscillator for generating said write control signal.
15. System of Claim 13 wherein said write control signal iε a clock signal having a frequency equal to n times the rate at which words of data appear on said data bus, where n equals the width of said data bus.
16. System of Claim 13, wherein said write control signal haε a frequency equal to the rate at which words of data appear on said data bus.
17. Syεtem of Claim 13 wherein εaid programmable logic device is an FPGA.
18. A memory integrated circuit compriεing: a data buε; means for storing data and providing words of data on said data bus; and clock means for generating timing signalε which control the timing by which said words of data are provided on εaid data buε, and for providing control signals so that a device external to said memory integrated circuit can retrieve said data on said data bus.
19. System comprising: a memory integrated circuit for providing configuration data on a data lead; and a programmable logic device for receiving said configuration data from said data lead and using said configuration data to configure itself, wherein said memory integrated circuit includes means for determining when the laεt bit of configuration data haε been communicated to said programmable logic device.
20. System of Claim 18 wherein said means for determining includes: a counter for providing a value indicative of the amount of configuration data that has been provided to said programmable logic device; a regiεter for storing a value indicative of the total amount of configuration data to be provided to said programmable logic device; and means for causing said memory integrated circuit to cease providing configuration data when said value provided by said counter and said value stored in said register are equal.
21. System comprising: a data line; a first memory device comprising at least one memory output lead coupled to said data line, a clock output signal line, clock means for generating clock signals on said clock output signal line, a plurality of memory cells, circuitry which obtains data from said memory cells and provides said data on said memory output lead in synchronization with εaid clock εignalε, and circuitry for providing a last bit signal when the laεt bit of data has been provided by said first memory device; and a second memory device comprising a clock input lead for receiving said clock signalε, and a last bit input lead for receiving said laεt bit signal, said second memory device providing data on said data line in synchronization with said clock signalε received from said first memory device in response to receipt of said last bit signal.
22. System comprises: a data line; a clock line; a first memory device comprising at least one memory output lead coupled to said data line, a clock generator for generating a clock signal and providing said clock signal on said clock line, a plurality of memory cellε, and circuitry for obtaining data from said memory cells and providing said data on said data line in synchronization with said clock signal, said first memory device also including a last bit line for providing a last bit signal when the last bit of data is provided by said first memory device; and a second memory device comprising a last bit input lead coupled to said last bit line for receiving said last bit signal, at leaεt one output lead coupled to said data line, a clock generator for generating a clock signal and providing said clock signal on said clock line upon receipt of said last bit signal by said second memory device, a plurality of memory cellε, and circuitry which receives data from said memory cellε and provides said data on said data line in synchronization with said clock signal provided by said second memory device clock generator when said last bit signal has been received by said second memory device.
23. A memory integrated circuit comprising: a clock generator for generating a firεt clock signal and a second clock signal; an addresε counter for receiving said first clock signal and providing addresseε in reεponse thereto; a memory circuit for receiving εaid addreεεeε and providing a word of data in response thereto; a shift register for shifting said word of data onto a data output lead in synchronization with said second clock signal; and a clock output lead coupled to said clock generator for providing said second clock signal.
24. System comprising: a programmable logic device having a configuration data input lead, a configuration clock input lead, and an output lead for providing a signal indicating when said programmable logic device is finished being configured; and a memory integrated circuit having a data output lead coupled to said configuration data input lead, a clock output lead coupled to said configuration clock input lead, a clock generator for providing clock signalε on said clock output lead, said memory integrated circuit providing data on said data output lead in synchronization with said clock signalε, said memory integrated circuit tri-stating said data output lead and said clock output lead in responεe to said signal indicating when said programmable logic device is finished being configured.
PCT/US1996/011226 1995-07-10 1996-07-10 System comprising field programmable gate array and intelligent memory WO1997003444A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP50587497A JP3736855B2 (en) 1995-07-10 1996-07-10 System including field programmable gate array and intelligent memory
EP96923615A EP0780017A1 (en) 1995-07-10 1996-07-10 System comprising field programmable gate array and intelligent memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US50029495A 1995-07-10 1995-07-10
US500,294 1995-07-10

Publications (1)

Publication Number Publication Date
WO1997003444A1 true WO1997003444A1 (en) 1997-01-30

Family

ID=23988791

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/011226 WO1997003444A1 (en) 1995-07-10 1996-07-10 System comprising field programmable gate array and intelligent memory

Country Status (4)

Country Link
US (1) US5760607A (en)
EP (1) EP0780017A1 (en)
JP (1) JP3736855B2 (en)
WO (1) WO1997003444A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821776A (en) * 1997-01-31 1998-10-13 Actel Corporation Field programmable gate array with mask programmed analog function circuits
WO1999031803A1 (en) * 1997-12-15 1999-06-24 Tellabs Research Limited Clocking in electronic circuits
WO2001020784A1 (en) * 1999-09-15 2001-03-22 Thomson Licensing S.A. Multi-clock integrated circuit with clock generator and bi-directional clock pin arrangement
WO2003023602A1 (en) * 2001-09-07 2003-03-20 Ip Flex Inc. Data processing system and control method thereof
WO2003036652A1 (en) * 2001-10-25 2003-05-01 Xilinx, Inc. Using transfer bits during data transfer from non-volatile to volatile memories
CN101702326B (en) * 2009-10-30 2012-08-29 曙光信息产业(北京)有限公司 Memory controller

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7356620B2 (en) 2003-06-10 2008-04-08 Altera Corporation Apparatus and methods for communicating with programmable logic devices
US5959466A (en) 1997-01-31 1999-09-28 Actel Corporation Field programmable gate array with mask programmed input and output buffers
US6150837A (en) 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US5978862A (en) * 1997-08-08 1999-11-02 Toshiba America Information Systems, Inc. PCMCIA card dynamically configured in first mode to program FPGA controlling application specific circuit and in second mode to operate as an I/O device
US6057703A (en) * 1997-08-22 2000-05-02 Holoplex Inc. Reconfigurable programmable logic devices
US6898101B1 (en) * 1997-12-16 2005-05-24 Cypress Semiconductor Corp. Microcontroller with programmable logic on a single chip
US6034538A (en) * 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
US6198303B1 (en) * 1998-03-25 2001-03-06 Altera Corporation Configuration eprom with programmable logic
US6242944B1 (en) * 1998-04-01 2001-06-05 California Institute Of Technology Real-time reconfigurable vision computing system
US6347346B1 (en) 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
US6163377A (en) * 1999-07-23 2000-12-19 Cv Us, Inc. Colorimeter
US6438737B1 (en) 2000-02-15 2002-08-20 Intel Corporation Reconfigurable logic for a computer
US6912601B1 (en) 2000-06-28 2005-06-28 Cypress Semiconductor Corp. Method of programming PLDs using a wireless link
US20030036895A1 (en) * 2000-07-20 2003-02-20 John Appleby-Alis System, method and article of manufacture for software-designed internet reconfigurable hardware
WO2002009285A2 (en) * 2000-07-20 2002-01-31 Celoxica Limited System, method and article of manufacture for dynamic programming of one reconfigurable logic device from another reconfigurable logic device
US6549975B2 (en) * 2001-03-08 2003-04-15 Micron Technology, Inc. Tri-stating output buffer during initialization of synchronous memory
US7840777B2 (en) * 2001-05-04 2010-11-23 Ascenium Corporation Method and apparatus for directing a computational array to execute a plurality of successive computational array instructions at runtime
US6605962B2 (en) 2001-05-06 2003-08-12 Altera Corporation PLD architecture for flexible placement of IP function blocks
US7076595B1 (en) * 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US6472919B1 (en) 2001-06-01 2002-10-29 Sun Microsystems, Inc. Low voltage latch with uniform stack height
US6489804B1 (en) 2001-06-01 2002-12-03 Sun Microsystems, Inc. Method for coupling logic blocks using low threshold pass transistors
US6501295B1 (en) * 2001-06-01 2002-12-31 Sun Microsystems, Inc. Overdriven pass transistors
GB0122477D0 (en) * 2001-09-18 2001-11-07 Anadigm Ltd Methods and apparatus for reconfiguring programmable devices
US6784995B2 (en) * 2001-09-21 2004-08-31 Colorvision Administrative Ag Colorimeter
US6781407B2 (en) 2002-01-09 2004-08-24 Xilinx, Inc. FPGA and embedded circuitry initialization and processing
US7420392B2 (en) * 2001-09-28 2008-09-02 Xilinx, Inc. Programmable gate array and embedded circuitry initialization and processing
US6798239B2 (en) * 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US6983405B1 (en) 2001-11-16 2006-01-03 Xilinx, Inc., Method and apparatus for testing circuitry embedded within a field programmable gate array
US6996758B1 (en) 2001-11-16 2006-02-07 Xilinx, Inc. Apparatus for testing an interconnecting logic fabric
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US6605960B2 (en) 2002-01-03 2003-08-12 Altera Corporation Programmable logic configuration device with configuration memory accessible to a second device
US6801940B1 (en) * 2002-01-10 2004-10-05 Networks Associates Technology, Inc. Application performance monitoring expert
US7299277B1 (en) * 2002-01-10 2007-11-20 Network General Technology Media module apparatus and method for use in a network monitoring environment
US6820248B1 (en) 2002-02-14 2004-11-16 Xilinx, Inc. Method and apparatus for routing interconnects to devices with dissimilar pitches
US6754882B1 (en) 2002-02-22 2004-06-22 Xilinx, Inc. Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)
US6976160B1 (en) 2002-02-22 2005-12-13 Xilinx, Inc. Method and system for controlling default values of flip-flops in PGA/ASIC-based designs
US6934922B1 (en) 2002-02-27 2005-08-23 Xilinx, Inc. Timing performance analysis
US7007121B1 (en) 2002-02-27 2006-02-28 Xilinx, Inc. Method and apparatus for synchronized buses
US7111217B1 (en) 2002-02-28 2006-09-19 Xilinx, Inc. Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC)
US6839874B1 (en) 2002-02-28 2005-01-04 Xilinx, Inc. Method and apparatus for testing an embedded device
US7088767B1 (en) 2002-03-01 2006-08-08 Xilinx, Inc. Method and apparatus for operating a transceiver in different data rates
US7111220B1 (en) 2002-03-01 2006-09-19 Xilinx, Inc. Network physical layer with embedded multi-standard CRC generator
US7187709B1 (en) 2002-03-01 2007-03-06 Xilinx, Inc. High speed configurable transceiver architecture
US6961919B1 (en) 2002-03-04 2005-11-01 Xilinx, Inc. Method of designing integrated circuit having both configurable and fixed logic circuitry
US6973405B1 (en) 2002-05-22 2005-12-06 Xilinx, Inc. Programmable interactive verification agent
US6772405B1 (en) 2002-06-13 2004-08-03 Xilinx, Inc. Insertable block tile for interconnecting to a device embedded in an integrated circuit
US20040133709A1 (en) * 2002-07-09 2004-07-08 International Business Machines Corporation Method and system for personalized I/O device initialization
US7085973B1 (en) 2002-07-09 2006-08-01 Xilinx, Inc. Testing address lines of a memory controller
US7099426B1 (en) 2002-09-03 2006-08-29 Xilinx, Inc. Flexible channel bonding and clock correction operations on a multi-block data path
US7092865B1 (en) 2002-09-10 2006-08-15 Xilinx, Inc. Method and apparatus for timing modeling
US7111110B1 (en) * 2002-12-10 2006-09-19 Altera Corporation Versatile RAM for programmable logic device
AU2003288600A1 (en) * 2002-12-18 2004-07-09 Koninklijke Philips Electronics N.V. Code download in a system having multiple integrated circuits with jtag capability
US7421014B2 (en) * 2003-09-11 2008-09-02 Xilinx, Inc. Channel bonding of a plurality of multi-gigabit transceivers
FR2860313B1 (en) * 2003-09-30 2005-11-04 Commissariat Energie Atomique COMPONENT WITH RECONFIGURABLE ARCHITECTURE DYNAMICALLY
US7397272B1 (en) * 2006-02-28 2008-07-08 Xilinx, Inc. Parallel configuration of programmable devices
US7884672B1 (en) 2006-11-01 2011-02-08 Cypress Semiconductor Corporation Operational amplifier and method for amplifying a signal with shared compensation components
JP5363366B2 (en) * 2010-01-29 2013-12-11 富士通フロンテック株式会社 Display system, input / output device, and display device
CN104123234B (en) * 2013-04-27 2017-04-05 华为技术有限公司 Memory pool access method and memory system
JP7419764B2 (en) * 2019-11-20 2024-01-23 株式会社リコー Information processing device and configuration method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4893281A (en) * 1985-10-08 1990-01-09 Texas Instruments Incorporated Semiconductor memory system with programmable address decoder
US4940909A (en) * 1989-05-12 1990-07-10 Plus Logic, Inc. Configuration control circuit for programmable logic devices
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3473160A (en) * 1966-10-10 1969-10-14 Stanford Research Inst Electronically controlled microelectronic cellular logic array
US3553651A (en) * 1967-12-06 1971-01-05 Singer General Precision Memory storage system
BE755666A (en) * 1969-09-18 1971-02-15 Burroughs Corp BUFFER MEMORY FOR COMPUTER INPUT
US3816725A (en) * 1972-04-28 1974-06-11 Gen Electric Multiple level associative logic circuits
US3818452A (en) * 1972-04-28 1974-06-18 Gen Electric Electrically programmable logic circuits
GB1444084A (en) * 1972-06-21 1976-07-28 Honeywell Inf Systems Generalized logic device
US3849638A (en) * 1973-07-18 1974-11-19 Gen Electric Segmented associative logic circuits
US4020469A (en) * 1975-04-09 1977-04-26 Frank Manning Programmable arrays
DE2517565C3 (en) * 1975-04-21 1978-10-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Circuit arrangement for a data processing system
US4163291A (en) * 1975-10-15 1979-07-31 Tokyo Shibaura Electric Co., Ltd. Input-output control circuit for FIFO memory
JPS5247635A (en) * 1975-10-15 1977-04-15 Toshiba Corp Control method for transmitting informat ion
JPS5247638A (en) * 1975-10-15 1977-04-15 Toshiba Corp Information processing device
JPS6055848B2 (en) * 1975-10-15 1985-12-06 株式会社東芝 information processing equipment
JPS5255446A (en) * 1975-10-31 1977-05-06 Toshiba Corp Information transfer control system
FR2337376A1 (en) * 1975-12-31 1977-07-29 Honeywell Bull Soc Ind DEVICE ALLOWING THE TRANSFER OF BLOCKS OF VARIABLE LENGTH BETWEEN TWO INTERFACES OF DIFFERENT WIDTH
US4285038A (en) * 1976-10-15 1981-08-18 Tokyo Shibaura Electric Co., Ltd. Information transfer control system
US4270183A (en) * 1977-02-11 1981-05-26 Lockheed Aircraft Corp. Data dejittering apparatus
US4161778A (en) * 1977-07-19 1979-07-17 Honeywell Information Systems, Inc. Synchronization control system for firmware access of high data rate transfer bus
NL7713707A (en) * 1977-12-12 1979-06-14 Philips Nv INFORMATION BUFFER MEMORY OF THE "FIRST-IN, FIRST-OUT" TYPE WITH VARIABLE INPUT AND FIXED OUTPUT.
US4258418A (en) * 1978-12-28 1981-03-24 International Business Machines Corporation Variable capacity data buffer system
US4342081A (en) * 1979-12-12 1982-07-27 Honeywell Information Systems Inc. Tape device adapter
JPS6057090B2 (en) * 1980-09-19 1985-12-13 株式会社日立製作所 Data storage device and processing device using it
US4578771A (en) * 1980-12-29 1986-03-25 International Business Machines Corporation Dynamically reprogrammable array logic system
US4486854A (en) * 1981-10-15 1984-12-04 Codex Corporation First-in, first-out memory system
JPS58205870A (en) * 1982-05-26 1983-11-30 Nippon Telegr & Teleph Corp <Ntt> Simulation apparatus of logic circuit
US4527233A (en) * 1982-07-26 1985-07-02 Ambrosius Iii William H Addressable buffer circuit with address incrementer independently clocked by host computer and external storage device controller
US4507760A (en) * 1982-08-13 1985-03-26 At&T Bell Laboratories First-in, first-out (FIFO) memory configuration for queue storage
US4521874A (en) * 1982-09-28 1985-06-04 Trw Inc. Random access memory device
US4535427A (en) * 1982-12-06 1985-08-13 Mostek Corporation Control of serial memory
JPS6061992A (en) * 1983-09-14 1985-04-09 Nec Corp Pseudo static memory
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US5270981A (en) * 1985-07-30 1993-12-14 Kabushiki Kaisha Toshiba Field memory device functioning as a variable stage shift register with gated feedback from its output to its input
US4847812A (en) * 1986-09-18 1989-07-11 Advanced Micro Devices FIFO memory device including circuit for generating flag signals
DE68919404T2 (en) * 1988-09-20 1995-03-30 Fujitsu Ltd Semiconductor memory with serial input / serial output.
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5146577A (en) * 1989-04-10 1992-09-08 Motorola, Inc. Serial data circuit with randomly-accessed registers of different bit length
JPH04305889A (en) * 1991-04-02 1992-10-28 Mitsubishi Electric Corp Sequential access memory
DE4207226B4 (en) * 1992-03-07 2005-12-15 Robert Bosch Gmbh Integrated circuit
US5394031A (en) * 1993-12-08 1995-02-28 At&T Corp. Apparatus and method to improve programming speed of field programmable gate arrays
US5432741A (en) * 1994-03-17 1995-07-11 Texas Instruments Incorporated Circuit for permanently disabling EEPROM programming
US5493239A (en) * 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
US5543730A (en) * 1995-05-17 1996-08-06 Altera Corporation Techniques for programming programmable logic array devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4893281A (en) * 1985-10-08 1990-01-09 Texas Instruments Incorporated Semiconductor memory system with programmable address decoder
US4940909A (en) * 1989-05-12 1990-07-10 Plus Logic, Inc. Configuration control circuit for programmable logic devices

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821776A (en) * 1997-01-31 1998-10-13 Actel Corporation Field programmable gate array with mask programmed analog function circuits
WO1999031803A1 (en) * 1997-12-15 1999-06-24 Tellabs Research Limited Clocking in electronic circuits
WO2001020784A1 (en) * 1999-09-15 2001-03-22 Thomson Licensing S.A. Multi-clock integrated circuit with clock generator and bi-directional clock pin arrangement
US6639422B1 (en) 1999-09-15 2003-10-28 Thomson Licensing S.A. Multi-clock integrated circuit with clock generator and bi-directional clock pin arrangement
KR100755247B1 (en) 1999-09-15 2007-09-06 톰슨 라이센싱 Multi-clock integrated circuit with clock generator and bi-directional clock pin arrangement
WO2003023602A1 (en) * 2001-09-07 2003-03-20 Ip Flex Inc. Data processing system and control method thereof
CN100397331C (en) * 2001-09-07 2008-06-25 Ip菲力股份有限公司 Data processing system and control method thereof
WO2003036652A1 (en) * 2001-10-25 2003-05-01 Xilinx, Inc. Using transfer bits during data transfer from non-volatile to volatile memories
US6981091B2 (en) 2001-10-25 2005-12-27 Xilinx,Inc. Using transfer bits during data transfer from non-volatile to volatile memories
US7127552B2 (en) 2001-10-25 2006-10-24 Xilinx, Inc. Using transfer bits during data transfer from non-volatile to volatile memories
CN101702326B (en) * 2009-10-30 2012-08-29 曙光信息产业(北京)有限公司 Memory controller

Also Published As

Publication number Publication date
US5760607A (en) 1998-06-02
JP3736855B2 (en) 2006-01-18
EP0780017A1 (en) 1997-06-25
JPH10505993A (en) 1998-06-09

Similar Documents

Publication Publication Date Title
US5760607A (en) System comprising field programmable gate array and intelligent memory
US4940909A (en) Configuration control circuit for programmable logic devices
EP0450811B1 (en) Integrated circuit
JP3454834B2 (en) Integrated circuit with multiple pins
US5414377A (en) Logic block with look-up table for configuration and memory
US6198304B1 (en) Programmable logic device
EP0426283B1 (en) Programmable logic device with multi-function input pin
EP0678985B1 (en) A programmable logic device which stores more than one configuration and means for switching configurations
US5430687A (en) Programmable logic device including a parallel input device for loading memory cells
US6614259B2 (en) Configuration memory integrated circuit
US6512395B1 (en) Configurable memory for programmable logic circuits
US5493239A (en) Circuit and method of configuring a field programmable gate array
JP3210660B2 (en) Logic blocks for programmable logic devices
US5773993A (en) Configurable electronic device which is compatible with a configuration bitstream of a prior generation configurable electronic device
US5646544A (en) System and method for dynamically reconfiguring a programmable gate array
US6148390A (en) Techniques and circuits for high yield improvements in programmable devices using redundant logic
US5787007A (en) Structure and method for loading RAM data within a programmable logic device
US5600264A (en) Programmable single buffered six pass transistor configuration
US5764076A (en) Circuit for partially reprogramming an operational programmable logic device
WO1999034515A1 (en) Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ispav) capabilities for supporting in-system reconfiguring of pld&#39;s
US5099150A (en) Circuit block for programmable logic devices, configurable as a user-writable memory or a logic circuit
US6766505B1 (en) Parallel programming of programmable logic using register chains
US5995988A (en) Configurable parallel and bit serial load apparatus
US5789938A (en) Structure and method for reading blocks of data from selectable points in a memory device
EP0343968A2 (en) Programmable logic device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CA JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

WWE Wipo information: entry into national phase

Ref document number: 1996923615

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWP Wipo information: published in national office

Ref document number: 1996923615

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: CA

WWW Wipo information: withdrawn in national office

Ref document number: 1996923615

Country of ref document: EP