WO1997007538A1 - Method of making electrical connections to integrated circuit - Google Patents

Method of making electrical connections to integrated circuit Download PDF

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Publication number
WO1997007538A1
WO1997007538A1 PCT/CA1996/000501 CA9600501W WO9707538A1 WO 1997007538 A1 WO1997007538 A1 WO 1997007538A1 CA 9600501 W CA9600501 W CA 9600501W WO 9707538 A1 WO9707538 A1 WO 9707538A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
conductors
chip
integrated circuit
bonded
Prior art date
Application number
PCT/CA1996/000501
Other languages
French (fr)
Inventor
Jonathan H. Orchard-Webb
Original Assignee
Mitel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitel Corporation filed Critical Mitel Corporation
Priority to EP96923800A priority Critical patent/EP0846338A1/en
Priority to US09/011,899 priority patent/US6204164B1/en
Publication of WO1997007538A1 publication Critical patent/WO1997007538A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01084—Polonium [Po]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

A method of making electrical connections to an integrated circuit chip (1, 2, 3) comprises providing at least one chip having exposed conductors on its active surface, providing a substrate (4) having conductors (5) on its surface corresponding to said exposed conductors on the chip, mounting the chip on the substrate so that said conductors are in accurate alignment with the corresponding conductors on the substrate, bonding the chip to said substrate, and filling any voids between the conductors on the chip and the corresponding conductors on said substrate with a conductive material. This method removes the limitation imposed by the large pad size needed for conventional techniques.

Description

METHOD OF MAKING ELECTRICAL CONNECTIONS TO INTEGRATED
CIRCUIT
This invention relates to a method of making electrical connections to an integrated circuit (i.e.) chip.
Electrical connection between the chip circuitry and the integrated circuit package is most commonly accomplished by employing wire bonding techniques. For hermetic packages, the preferred technique is to ultrasonically bond aluminum wires to bonding pads on the i.e chip, and for plastic packages, the preferred method is to form balls on gold wire and to use thermal compression to attach these balls to bonding pads on the integrated circuit.
Since the bonding wires are about 1 mil or larger diameter, the pad size has to be a few mils across to accommodate the bond. Signal wires leading from the bonding pad to the i.e. circuitry may be 0.5 μm wide, and are projected to continue to get smaller as technology improves.
More recently, techniques have been developed whereby the chip is attached face downwards on the substrate using tiny solder balls. This technique is used in ball grid arrays which allow a very high number of connections to be made to the i.e. A large pad is still required for the solder ball, however, and multiple layers of substrate interconnect may be needed to access the pads.
An object ofthe invention is to remove the limitation imposed by the large pad size needed for conventional assembly techniques (e.g. wire bonding, ball grid arrays or beam lead), and to provide a high conductivity path for heat to flow from the chip active area to the substrate.
Accordingly the present invention provides a method of making electrical connections to an integrated circuit chip, comprising the steps of providing at least one chip having exposed conductors on its active surface, providing a substrate having conductors on its surface corresponding to said exposed conductors on the chip, mounting said at least one chip on said substrate so that said conductors are in accurate alignment with the corresponding conductors on the substrate, bonding said at least one chip to said substrate, and filling any voids between the conductors on the chip and the corresponding conductors on said substrate with a conductive material.
One or a plurality of chips can be mounted on the substrate. They are preferably bonded using fusion bonding techniques, although other techniques, such as epoxy bonding can be employed. Fusion bonding is a technique by which two materials are bonded together by bringing their oxide covered surfaces together under temperature and pressure. The process produces a very strong bond. The system can be made to provide almost perfect thermal expansion matching between the two silicon components and the attachment layer, which is silicon dioxide in the case of silicon based technologies.
The method also provides an extremely low thermal path for heat dissipation from the chip to the substrate (approximately 0.03 deg C/Watt chip to substrate, and less than 1 deg C/Watt spreading resistance into the bulk substrate for a 1 cm square chip).
An alternative, but less satisfactory technique is be to attach the chip with a polymer adhesive.
The electrical interconnection is made between narrow conductors on the chip and accurately aligned narrow conductors on the substrate. Both sets of conductors can be formed using i.e. photolithographic techniques, and chip to substrate alignment can be performed using through-the-chip infrared alignment techniques.
An important aspect ofthe invention the use of a fine gap between the chip conductor and the substrate conductor, which is subsequently bridged with a conductor. Bridging may be accomplished by capillary flow of a solder, or by surface wetting by a solder. Alternatively, a conductive plastic may be used to make the bridge.
The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:
Figure 1 is a plan view of an integrated circuit assembly;
Figure 2 is a cross section through the assembly shown in Figure 1 ;
Figure 3 is a detailed cross section of a single bonded chip; and
Figure 4 is a detail ofthe chip to substrate metallization connection.
Figure 1 shows a series of chips 1, 2, 3 bonded to a silicon substrate 4 having patterned conductors 5 forming lead wires on its upper surface. The substrate 4 is subsequently diced to form the individual i.e. packages, and the lead wires 5 can be fanned out and connected to external pins of an i.e. package in a conventional manner.
Figure 2 shows the chips 1, 2, 3 fusion bonded to the substrate 4 with the fusion bond 6.
In order to make the assembly shown, a silicon wafer containing a large number of chips is first prepared. The wafer has exposed narrow signal conductors, in the order of 0.5μ wide, on its active surface. These are the signal conductors that in a conventional arrangement would be attached to bonding pads.
A thick passivation layer of silicon dioxide is then formed on the active surface. The passivation layer is preferably doped to match its thermal expansion with silicon.
Next a mask is applied and the conductors exposed using conventional etching techniques. The exposed conductors can at this point be plated with an easily wettable metal, such as gold.
The active surface ofthe wafer is then lapped to give a very flat surface using techniques currently employed in multilevel metallization. The wafer is then diced to form the chips 1, 2, 3.
Meanwhile the silicon substrate 4 is prepared. The narrow leads 5 are first patterned onto the surface ofthe substrate 4 in positions matching corresponding conductors on the chips. The narrow leads have can have a width matching that ofthe signal conductors in the chips. A silicon dioxide bonding layer is then formed on the surface ofthe substrate.
The chips 1, 2, 3 are then mounted face downward on the substrate 5 and aligned using through-the-chip infrared techniques (for example, using a system manufactured by Karl Zeiss). Once aligned the chips 1, 2, 3 are fusion attached by applying heat and pressure at temperatures in the range of 300°C to 650°C.
Finally, an electrical connection is established between the chip and substrate leads by using a solder flow technique to fill the tiny voids between the chip and substrate metallizations sufficiently to establish an electrical connection between the circuit and substrate metallizations.
Figure 3 shows a conventional i.e. bonded to the substrate 4 in accordance with the invention. In Figure 3, signal wire 7 faces lead wire 5 on the substrate 4. The signal wire 7 is formed on the active surface 8 ofthe chip 1 in a conventional manner. The exposed signal wire 7 is plated with gold 9.
Thick silicon dioxide passivation layer 10 is located on the active surface 8 ofthe chip 1. This layer may, for example, 2 to 3 microns thick when deposited and then lapped down to about 1 micron thick.
The upper surface ofthe substrate 5 has a silicon dioxide layer 11 formed thereon that is used to form a fusion bond 12 with the passivation layer 10. Figure 4 is a part sectional view looking down onto the connection at the edge of the chip. Lead wire 5 can be seen terminating under plated metal portion 9, which is surrounded by a passivation window 12.
A key aspect of this invention is attachment ofthe front (active) surface ofthe chip to the substrate. While the preferred method is through fusion ofthe silicon oxides, other, more conventional chip attachment techniques such as epoxy bonding might be used. Many methods are available for producing the passivating dielectric that is bonded to the substrate, and the dielectric can be made of several different layers to meet the requirements of i.e. processing. In the example given, a borosilicate glass might be used as the passivation layer because the thermal expansion coefficient is well matched to silicon. Other glasses could be used. Several techniques are in use for planarizing oxides; it may be possible, especially for small chips, to dispense with the lapping processes.
Another key aspect is the small gap between the metallization layers, which is subsequently filled with a conductive material. In the example given, the chip oxide was etched back to expose the metal conductor. This is the same function as the pad etch used in conventional processing. Alternatively, the substrate could be recessed to provide a small gap between the conductors. Many metallization techniques are in use for i.e. processing, and the optimum metallization process may be tailored to fit a given i.e. process or application.
The example given is for the silicon on silicon multichip module (MCM). The technique is, however applicable to other materials used for hybrid assemblies, provided that the materials are chosen to produce acceptably low stress between the chip and substrate. For example, a glass coated ceramic substrate might be used. The technique could also be used for semiconducting materials other than silicon provided that a suitable oxide coating is used for the fusion bond. The technique might also find application in conventional single chip packaging where very high pin counts are needed.
The invention greatly alleviates four problems associated with i.e. technology, namely the pad-limited layout for submicro circuits, pin limited packaging due to the large area need for bonding plots and solder balls; stress generated between the i.e. and the package substrate; and the high thermal resistance between the i.e. and the substrate (An order of magnitude improvement can be achieved over prior art techniques).

Claims

Claims:-
1. A method of making electrical connections to an integrated circuit chip, comprising the steps of providing at least one chip having exposed conductors on its active surface, providing a substrate having conductors on its surface corresponding to said exposed conductors on the chip, mounting said at least one chip on said substrate so that said conductors are in accurate alignment with the corresponding conductors on the substrate, bonding said at least one chip to said substrate, and filling any voids between the conductors on the chip and the corresponding conductors on said substrate with a conductive material.
2. A method as claimed in claim 1, wherein prior to mounting said at least one chip on said substrate a passivation layer is applied thereto, a mask is applied, and the passivation layer is etched through the mask to expose the conductors.
3. A method as claimed in claim 2, wherein said passivation layer is doped to match its thermal expansion with the substrate and said at least one chip.
4. A method as claimed in any of claims 1 to 3, wherein said at least one chip is bonded to said substrate by fusion bonding.
5. A method as claimed in any of claims 1 to 3, wherein said at least one chip is bonded to said substrate with epoxy resin.
6. A method as claimed in claim 4, wherein said voids are filled with a conductive material using a solder flow technique.
7. A method as claimed in claim 6, wherein said fusion bonding takes place at temperatures in the range of 300°C to 600°C.
8. A method as claimed in claim 1, wherein the conductors are plated with an easily wettable material.
9. A method as claimed in claim 1 , wherein said material is gold.
10. A method as claimed in claim 1, wherein said active surface is lapped to from a flat surface.
11. A method as claimed in claim 1 , wherein said at least one chip is aligned using through-the-chip infrared techniques.
12. A method as claimed in claim 1, wherein said conductors are provided on said substrate by patterning a metal deposition layer.
13. An integrated circuit package comprising an integrated circuit having conductors on its active surface, a substrate having conductors on its surface corresponding to said exposed conductors on the chip, said integrated circuit being surface bonded to said substrate so that said conductors are in accurate alignment with the corresponding conductors on the substrate, and any voids between the conductors on the integrated circuit and the corresponding conductors on said substrate being filled with a conductive material.
14. An integrated circuit package as claimed in claim 13, further comprising a passivation layer on its active surface.
15. An integrated circuit package as claimed in claim 14, wherein said passivation layer is doped to match its thermal expansion with the substrate and said integrated circuit.
16. An integrated circuit package as claimed in claim 13, wherein said integrated circuit is fusion bonded to said substrate.
17. An integrated circuit package as claimed in claim 13, wherein said integrated circuit is bonded to said substrate with epoxy resin.
18. An integrated circuit package as claimed in claim 13, wherein said voids are filled with solder.
PCT/CA1996/000501 1995-08-21 1996-07-24 Method of making electrical connections to integrated circuit WO1997007538A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP96923800A EP0846338A1 (en) 1995-08-21 1996-07-24 Method of making electrical connections to integrated circuit
US09/011,899 US6204164B1 (en) 1995-08-21 1996-07-24 Method of making electrical connections to integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA002156941A CA2156941A1 (en) 1995-08-21 1995-08-21 Method of making electrical connections to integrated circuit
CA2,156,941 1995-08-21

Publications (1)

Publication Number Publication Date
WO1997007538A1 true WO1997007538A1 (en) 1997-02-27

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US (1) US6204164B1 (en)
EP (1) EP0846338A1 (en)
CA (1) CA2156941A1 (en)
WO (1) WO1997007538A1 (en)

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US20030113947A1 (en) * 2001-12-19 2003-06-19 Vandentop Gilroy J. Electrical/optical integration scheme using direct copper bonding
US7829994B2 (en) * 2007-09-24 2010-11-09 Sixis, Inc. Semiconductor substrate elastomeric stack

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WO1987001509A1 (en) * 1985-09-10 1987-03-12 Plessey Overseas Limited Manufacture of a hybrid electronic or optical device
EP0264122A2 (en) * 1986-10-17 1988-04-20 Hitachi, Ltd. Method of producing a composite structure for a semiconductor device
JPH0198235A (en) * 1987-10-12 1989-04-17 Matsushita Electric Ind Co Ltd Method of mounting semiconductor device
DE4008624A1 (en) * 1989-04-05 1990-10-11 Bosch Gmbh Robert Mfg. hybrid semiconductor structure - depositing insulating, photo-hardenable adhesive film of surface(s) of support plate substrate

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Title
PATENT ABSTRACTS OF JAPAN vol. 013, no. 338 (E - 795) 28 July 1989 (1989-07-28) *

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US6204164B1 (en) 2001-03-20
EP0846338A1 (en) 1998-06-10

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