WO1997025743A1 - Laser antifuse using gate capacitor - Google Patents
Laser antifuse using gate capacitor Download PDFInfo
- Publication number
- WO1997025743A1 WO1997025743A1 PCT/US1997/000168 US9700168W WO9725743A1 WO 1997025743 A1 WO1997025743 A1 WO 1997025743A1 US 9700168 W US9700168 W US 9700168W WO 9725743 A1 WO9725743 A1 WO 9725743A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductive plate
- laser
- antifuse
- layer
- fabricated
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
- H01L23/5254—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates generally to integrated circuits and in particular the present invention relates to a laser antifuse fabricated in an integrated circuit.
- Integrated circuits commonly use programmable elements such as fusible links to allow custom programming ofthe integrated circuits after fabrication. While fusible links can be used for a variety of applications, they can be particularly useful in replacing defective circuits with redundant circuits. For example, integrated circuit memories are often fabricated with redundant memory cells. These memory cells can be selectively enabled after fabrication to replace defective memory cells which are detected during test operations.
- fusible link which could be used is a standard polysilicon fuse. The fuse comprises a polysilicon conductor approximately 1 ⁇ thick which is fabricated on the integrated circuit such that in its normal state there is a complete electrical path through the fuse. To program the fuse, a high power laser is used to open the electrical path by evaporating a portion ofthe polysilicon.
- a type of fusible link which has been used in integrated circuits is an antifuse.
- the antifuse is electrically opposite ofthe fuse in that the antifuse is a normally open circuit. To program the antifuse, its connections are shorted together to form an electrical path through the antifuse.
- One type of antifuse which is commonly used in integrated circuits is an oxide-nitride-oxide (ONO) antifuse.
- ONO oxide-nitride-oxide
- a typical ONO antifuse has a layer of nitride sandwiched between two layers of oxide, where the bottom layer of oxide is in contact with polysilicon and the top layer of oxide is also in contact with polysilicon.
- the ONO sandwich is a dielectric such that the un-programmed antifuse functions as a capacitor.
- ONO antifuses are currently used in integrated circuits, their continued use in high density integrated circuits is questionable. This is primarily due to the material used to fabricate the high density integrated circuits. The nitride needed for the ONO sandwich will not be available in standard fabrication and will require extra processing steps. Any extra step in the fabrication of integrated circuits is both time consuming and expensive.
- the present invention describes a laser antifuse fabricated in an integrated circuit.
- the laser antifuse has first and second physical states, and comprises a first conductive plate, a second conductive plate, and a layer of dielectric material located between the first conductive plate and the second conductive plate.
- the first conductive plate and the second conductive plate are electrically isolated by the layer of dielectric material in the first physical state.
- the first conductive plate and the second conductive plate are electrically connected through the layer of dielectric material in the second physical state in response to a focused external radiation source.
- the first conductive plate comprises a layer of polysilicon fabricated on the layer of dielectric material.
- the second conductive plate comprises an N-well fabricated in a P-substrate of the integrated circuit.
- the focused external radiation source can comprise a laser.
- a laser antifuse which is fabricated in an integrated memory circuit, and as two physical states.
- the laser antifuse comprises a first conductive plate, the first conductive plate being a layer of polysilicon, a second conductive plate, the second conductive plate being a well fabricated in a substrate ofthe integrated memory circuit, and a layer of dielectric material located between the first conductive plate and the second conductive plate.
- the first conductive plate and the second conductive plate are electrically isolated by the layer of dielectric material in the first physical state, and the first conductive plate and the second conductive plate are electrically connected through the layer of dielectric material in the second physical state in response to a focused external radiation source.
- Figure 1 is a cross-section of a laser antifuse ofthe present invention
- Figure 2 is a cross-section of an alternate embodiment of a laser antifuse of the present invention
- FIG. 3 is a block diagram of a DRAM incorporating the present invention.
- Figure 4 is a schematic diagram of circuitry ofthe DRAM of Figure 3; and Figure 5 is a block diagram ofa portion of PROM incorporating the present invention.
- a laser antifuse 10 wherein the laser antifuse is fabricated as a capacitor using standard transistor fabrication techniques.
- the preferred capacitor is physically large and referred to as a "fat" capacitor.
- the fat capacitor is fabricated in an N-well 12 which has been formed in a P-substrate 14 ofthe integrated circuit.
- the capacitor has two N+ contact regions 16 and 18 formed into the N-well.
- the N+ contact regions are produced during transistor source and drain fabrication steps.
- a layer of dielectric 20, preferably oxide, is fabricated on the N-well and a polysilicon gate 22 is fabricated on the oxide layer.
- the oxide layer is preferably about 100 A thick.
- the laser antifuse 10 is electrically connected as a capacitor where the gate 22 is the first capacitor plate and the N-well 12 is the second capacitor plate. Circuit connections can be made to the second plate through either N+ region 16 or 18. It will be appreciated that the laser antifuse can be fabricated using a P-well 13, as illustrated in Figure 2. Further, the oxide preferably used in dielectric layer 20 can be replaced with a suitable dielectric material. For example, Barium Strontium Titanium (BaSrTi(03))can be used in place ofthe oxide layer. This material has dielectric properties at low voltage levels, and exhibits conductive properties at higher voltage levels. It will be appreciated that BaSrTi(03) can not be used in place of the ONO sandwich dielectric described above. That is, BaSrTi(03) can not be readily ruptured merely using higher voltage levels.
- BaSrTi(03) can not be used in place of the ONO sandwich dielectric described above. That is, BaSrTi(03) can not be readily ruptured merely using higher
- a laser beam is directed through gate 22 such that the dielectric is ruptured and the gate and N-well 12 are shorted together.
- the energy level of the laser therefore, needs to be sufficient to merely punch through about 100 A of oxide. This energy level is substantially lower than the energy level needed to program the polysilicon fuse described above.
- Any type of laser or focused radiation source used on integrated circuits can be used to program laser antifuse 10.
- a NDYAG laser having a 1064 nanometer wavelength and .5 joule of energy was used with success during experimentation to produce holes having areas of 1 to 2 ⁇ meter 2 in gate 22. These holes provided a reliable contact between the gate 22 and N-well 12.
- FIG. 3 illustrates a sixteen megabit memory device incorporating the present invention.
- the device is organized as a 2 Meg x 8 Burst EDO DRAM having an eight bit data input/output path 24 providing data storage for 2,097,152 bytes of information in the memory array 26.
- U.S. Patent No. 5,526,320 entitled BURST EDO MEMORY DEVICE, by Zager et al., and assigned to the assignee of the present invention describes a burst EDO memory in detail.
- An active-low Row Address Strobe (RAS*) signal 28 is used to latch a first portion of a multiplexed memory address, from address inputs 30, in latch 32.
- the latched row address 33 is decoded in row decoder 34.
- the decoded row address is used to select a row ofthe memory array 26.
- a Column Address Strobe (CAS*) signal 36 is used to latch a second portion of a memory address from address inputs 30 into address generation circuit 38.
- the latched column address 40 is decoded in column address decoder 42.
- the decoded column address is used to select a column ofthe memory array 26.
- a burst read cycle data within the memory array located at the row and column address selected by the row and column address decoders is read out of the memory array and sent along data path 44 to output latches.
- the output drivers 46 will continue to drive the data lines without tri-stating the data outputs during CAS* high intervals dependent on the state ofthe Output Enable and Write Enable (OE* and WE*) control lines, thus allowing additional time for the system to latch the output data.
- the data outputs remain valid throughout the burst read cycles with the exception of brief periods of data transition.
- the laser antifuses are used to indicate memory cell addresses of memory cells which have been determined to be defective such that redundant memory cells can be used.
- a comparator 50 is provided which compares the external memory addresses 30 to the laser antifuses and produces an appropriate memory cell output address 52. The output address can then be used to access redundant memory cells when appropriate.
- the laser antifuse is coupled to both a power-up circuit 54 and a latch circuit 56. The power-up circuit is used to read the laser antifuse when the memory is first turned on, and the latch circuit is used to latch the state ofthe laser antifuse during normal operations. It will be appreciated that the laser antifuse 10 can be inco ⁇ orated into the memory circuit for any desired pu ⁇ ose and is not limited to redundant memory cell circuitry.
- FIG. 5 illustrates a portion of another integrated circuit inco ⁇ orating the present invention.
- the integrated circuit is a programmable read only memory (PROM) 60 wherein the laser antifuses 10 are used as memory cells.
- the PROM includes laser antifuse memory cells 10 which are coupled between ground and an access transistor 62.
- the gate of the access transistor is connected to a word line 64 which can be selectively activated to couple the memory cell to digit line 66.
- the digit line can be coupled to the output lines 68 ofthe memory through a buffer 70.
- the laser antifuse memory cells are programmed using the laser as described above.
- the digit line is first pre-charged to a predetermined voltage level using pre-charge circuit 72.
- a word line 64 is then activated to coupled a memory cell 10 to the digit line 66. If the memory cell has been programmed using a laser, the digit line is discharged through the memory cell. If the laser antifuse has not been programmed, the digit line voltage remains substantially unchanged. Sensing circuitry 74 is used to sense the digit line voltage and amplify the signal for outputting on the external communication lines via buffer 70. It will be appreciated that the laser antifuse can be inco ⁇ orated into the PROM for any desired pu ⁇ ose and is not limited to programmable memory cells.
- a laser antifuse has been described which can be fabricated on an integrated circuit which does not require additional fabrication steps.
- the laser antifuse in its normal physical state, operates as a capacitor having two conductive plates separated by a layer of dielectric material.
- the physical state ofthe laser antifuse is changed by using an external radiation source, such as a laser, to rupture the dielectric layer and create an electrical short between the conductive plates.
- the laser antifuse has been described as being fabricated as a fat capacitor which could have either an N-type or P-type well as one of the conductive plates. Two ofthe numerous applications of the laser antifuse have been described: redundant circuitry enable, and programmable memory cells.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97901359A EP0956591A1 (en) | 1996-01-04 | 1997-01-03 | Laser antifuse using gate capacitor |
KR1019980705143A KR100323174B1 (en) | 1996-01-04 | 1997-01-03 | Laser antifuse using gate capacitor |
AU15274/97A AU1527497A (en) | 1996-01-04 | 1997-01-03 | Laser antifuse using gate capacitor |
JP09525331A JP3122470B2 (en) | 1996-01-04 | 1997-01-03 | Laser antifuse using gate capacitor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/582,652 US5811869A (en) | 1996-01-04 | 1996-01-04 | Laser antifuse using gate capacitor |
US08/582,652 | 1996-01-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997025743A1 true WO1997025743A1 (en) | 1997-07-17 |
Family
ID=24329951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/000168 WO1997025743A1 (en) | 1996-01-04 | 1997-01-03 | Laser antifuse using gate capacitor |
Country Status (6)
Country | Link |
---|---|
US (2) | US5811869A (en) |
EP (1) | EP0956591A1 (en) |
JP (1) | JP3122470B2 (en) |
KR (1) | KR100323174B1 (en) |
AU (1) | AU1527497A (en) |
WO (1) | WO1997025743A1 (en) |
Families Citing this family (32)
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TWI355046B (en) * | 2007-07-10 | 2011-12-21 | Nanya Technology Corp | Two bit memory structure and method of making the |
KR20110120044A (en) | 2010-04-28 | 2011-11-03 | 삼성전자주식회사 | Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse |
US8330189B2 (en) * | 2010-06-21 | 2012-12-11 | Kilopass Technology, Inc. | One-time programmable memory and method for making the same |
US9230813B2 (en) | 2010-06-21 | 2016-01-05 | Kilopass Technology, Inc. | One-time programmable memory and method for making the same |
KR20130095554A (en) | 2012-02-20 | 2013-08-28 | 삼성전자주식회사 | Anti-fuse circuit and semiconductor device having the same |
KR101488616B1 (en) | 2013-09-06 | 2015-02-06 | (주) 아이씨티케이 | Apparatus and method for generating identification key |
US10529436B1 (en) | 2017-01-17 | 2020-01-07 | Synopsys, Inc. | One-time programmable bitcell with diode under anti-fuse |
KR20180085120A (en) | 2017-01-17 | 2018-07-26 | 삼성전자주식회사 | Semiconductor memory device |
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1996
- 1996-01-04 US US08/582,652 patent/US5811869A/en not_active Expired - Lifetime
-
1997
- 1997-01-03 WO PCT/US1997/000168 patent/WO1997025743A1/en not_active Application Discontinuation
- 1997-01-03 KR KR1019980705143A patent/KR100323174B1/en not_active IP Right Cessation
- 1997-01-03 JP JP09525331A patent/JP3122470B2/en not_active Expired - Fee Related
- 1997-01-03 AU AU15274/97A patent/AU1527497A/en not_active Abandoned
- 1997-01-03 EP EP97901359A patent/EP0956591A1/en not_active Withdrawn
-
1998
- 1998-07-02 US US09/109,605 patent/US6252293B1/en not_active Expired - Lifetime
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Also Published As
Publication number | Publication date |
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JP3122470B2 (en) | 2001-01-09 |
JPH11502068A (en) | 1999-02-16 |
US5811869A (en) | 1998-09-22 |
EP0956591A1 (en) | 1999-11-17 |
AU1527497A (en) | 1997-08-01 |
US6252293B1 (en) | 2001-06-26 |
KR19990077012A (en) | 1999-10-25 |
KR100323174B1 (en) | 2002-03-08 |
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