WO1997032253A1 - Semiconductor memory device having faulty cells - Google Patents
Semiconductor memory device having faulty cells Download PDFInfo
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- WO1997032253A1 WO1997032253A1 PCT/JP1996/003501 JP9603501W WO9732253A1 WO 1997032253 A1 WO1997032253 A1 WO 1997032253A1 JP 9603501 W JP9603501 W JP 9603501W WO 9732253 A1 WO9732253 A1 WO 9732253A1
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- semiconductor memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
Definitions
- the present invention relates to a semiconductor storage device using an electrically rewritable non-volatile semiconductor memory as a storage medium, and more particularly to a semiconductor storage device using a semiconductor memory which partially contains a defect and which becomes defective if frequent rewriting is performed.
- a semiconductor storage device using a semiconductor memory which partially contains a defect and which becomes defective if frequent rewriting is performed.
- Electrically rewritable non-volatile memory has advantages such as low power, resistance to vibration and shock, and high speed, which are more advantageous than other storage devices such as magnetic storage devices and optical disk devices as storage devices for information equipment. ing.
- the manufacturing process is complicated, and in principle, irreversible action is repeatedly performed on the semiconductor, so that there is a problem that defective parts are generated and the use is significantly deteriorated. As a result, the production yield is low, the cost is high, and reliability during use is also an issue.
- a memory for recording an address conversion table indicating a comparison between a logical address and a physical address, that is, a correspondence between a logical address specified by a host and a physical address on the memory.
- the number of erasures is managed, and when the number of erasures reaches a certain value, the data is replaced with other areas, and at the same time, the address value on the address conversion table is rewritten, so that the logical address and the physical address are Register the correspondence again so that correct correspondence can be obtained.
- the above address conversion table registers all logical address values used.
- a high-speed volatile memory such as DRAM [or SRAM] is used.
- the reason for using high-speed volatile memory is that address conversion can be performed at high speed, and when addresses are changed, registration can be partially rewritten at high speed. And that the memory can be realized with relatively inexpensive memory.
- the access time of the non-volatile memory is generally long, so that the access time of the storage device itself becomes long.
- An object of the present invention is to provide a large-capacity semiconductor memory device which solves the above-mentioned problems, can be reduced in size and cost, and has a short startup time and short access time.
- a specific object of the present invention is to provide a large-capacity semiconductor memory device in which the start-up time and the access time are short by reducing the external registration memory capacity or eliminating the external registration memory.
- a specific object of the present invention is to provide an access method with a short start-up time and access time in a large-capacity semiconductor memory device in which the external registration memory capacity is reduced or the external registration memory is eliminated. It is.
- Another object of the present invention is to provide a controller which realizes a short start-up time and an access time in a large-capacity semiconductor memory device in which the memory capacity for external registration is reduced or the memory for external registration is eliminated.
- a semiconductor memory device that uses a semiconductor memory partially having a storage cell having a defective data storage function as a storage medium and performs data holding or reading of stored data in units of blocks of a plurality of data.
- Defective location registering means for registering the address value of a defective area including a memory cell having a defective storage function in ascending order or descending order according to the magnitude of the address value in the above-mentioned block unit;
- An alternative storage area that is a storage area for replacement in units, an alternative location registration unit that registers a replacement address value when the address value of the defective area registered in the defect location registration means is replaced with the alternative area, It is determined whether or not the address value of the area where data is retained or read out corresponds to the address value of the defective area.
- bad registration search means for searching the defect location registration means for, Adoresu value of the region holding or reading of data is performed
- Access control means for controlling access to the alternative area by referring to the alternative location registering means when the defective location is registered in the defective location registering means; and raising the defective location registering means when a new defect occurs. It is provided with registration updating means for performing rewriting according to a power order or descending power order rule, determining an alternative location, and updating the alternative location registering means.
- defect registration and retrieval means of the defect location registration means of the semiconductor memory device first divides the area of the defect location registration means into halves, estimates which area exists, and then determines which area exists. Is divided into two halves, which is guessed, and by continuing this work, it is finally determined whether or not the defective location is registered in the defective location registration means, and the search is speeded up. .
- a semiconductor memory partially having storage cells having a defective data storage function is used as a storage medium to store a certain amount of data to be continuously transferred when storing or reading stored data.
- a semiconductor storage device that is treated as a management unit has a management information storage area for storing management information for each data management unit inside the semiconductor memory, and has use frequency management means for monitoring the use frequency of the data management unit.
- a management address which is a logical address determined for convenience, is registered, and the management address is basically a physical address of the semiconductor memory.
- an alternative address registration area for the entire data storage area and an alternative area are provided inside the semiconductor memory, and the alternative address registration area is registered according to the physical order of data storage on the memory. In order to search for the replacement address, the registered location is uniquely identified from the physical position of the replacement area.
- a management information area is provided for each data management unit.
- the management information area stores at least address information of stored data, a specific code indicating that the data is not defective, and an error correction code of the management information. If an access request is received from outside, error detection and correction using the error correction code in the corresponding area are compared with a specific code indicating that it is not defective, and if both are normal, it is used. Judge as an available area and execute access processing. If either of them is not normal, perform processing as an unusable area.
- a storage area for temporarily storing the data of the data management unit is provided. Two units are provided.
- data transfer with the outside and data transfer with the semiconductor memory are alternately performed to enable simultaneous transfer, and control for avoiding and accessing the defective storage cell is performed with the outside. Process in parallel with the data transfer.
- the address value of the non-defective area is not registered, and only the address value of the defective area is registered, the amount of registered data can be reduced, and the memory capacity for registration can be reduced. Also, by registering bad addresses in ascending or descending order, when searching for a certain address value, if you refer to an arbitrary location in the registered memory, it will be registered in the smaller address value side. It is possible to quickly determine whether the power is registered and whether it is registered on the larger address value side, and it is possible to judge whether or not it is registered, or where it is registered, at a relatively high speed from a large number of registered values.
- each block of the memory of the storage medium has an area for storing management information
- a logical address value can be registered here, and physical rewriting is frequently performed due to frequent rewriting. When it is necessary to replace a new location, it can be easily handled by rewriting the logical address value in the management information.
- there is no need to register the table in an external memory there is no need to provide another volatile memory, and there is no need to rebuild the table when the power is turned on.
- the present invention uses a partially defective semiconductor memory for part or all of a storage medium, and writes or retains or reads a certain amount of data to or from the storage medium.
- a semiconductor memory device as a management unit, a storage area for storing data of a data management unit, a replacement area thereof, and an address registration area of the replacement area are provided in the semiconductor memory, and an address value indicating the replacement area is: It is characterized in that the address is stored in the address according to the address value of the storage area in the alternative address registration area.
- each of the storage areas has management information, and stores failure determination information for determining whether the storage area is defective as the management information. If there is a request for access to the storage area, the storage area has failure information.
- the storage area is used to determine whether it is a usable area by using the defect determination information. If it is a usable area, access processing is performed. If it is not a usable area, an alternative address registration area is accessed and the address is accessed. It is characterized by acquiring and accessing alternative areas.
- the present invention provides a method for storing a partially defective semiconductor memory in a storage medium. Or, when writing, holding, or reading data to or from the storage medium, a certain amount of data is used as the data management unit, and the data of the data management unit is stored inside the semiconductor memory.
- the storage area includes a storage area for storing data, an alternative area thereof, and an address registration area of the alternative area.
- Each of the storage areas includes management information.
- As the management information error detection of data stored in the storage area is performed.
- the different data is characterized in that the bits of the data are all ones or all zeros.
- error detection and correction are performed using the correction information, and if an uncorrectable error is detected, it is determined that the area is unusable, and if there is no error, Alternatively, if a correctable error is corrected, the detection information is used to detect whether or not the error is a defect. If the error is not a defect, the area is determined to be usable and access processing is performed. In this case, processing is performed as an unusable area.
- the present invention uses a partially defective semiconductor memory for part or all of a storage medium, and writes or retains or reads a certain amount of data to or from the storage medium.
- a semiconductor storage device that is a management unit
- transfer data is stored in response to transfer data accompanying a data storage request.
- the present invention also relates to a method for accessing a semiconductor memory device using a partially defective semiconductor memory for a part or all of a storage medium, wherein the semiconductor memory device has a storage area for storing data inside the semiconductor memory. Access to determine the good / bad // of the storage area, if it is not bad, access it as it is; if it is bad, access the address registration area of the replacement area and get the address of the replacement area, An alternative area is accessed based on the address.
- the present invention provides a semiconductor memory device using a partially defective semiconductor memory for part or all of a storage medium, wherein a storage area for storing data of a data management unit is provided inside the semiconductor memory; And the address registration area of the replacement area, and when accessing data stored in the semiconductor memory, the access time to the semiconductor memory when the data storage area is not replaced by the replacement area is replaced.
- the access time is shorter than the access time in the case.
- the present invention provides a semiconductor memory device using a partially defective semiconductor memory for part or all of a storage medium, wherein a storage area for storing data of a data management unit is provided inside the semiconductor memory; And an address registration area of an alternative area, and stores data stored in the semiconductor memory.
- the number of accesses to the semiconductor memory when the data storage area is not replaced by the replacement area is smaller than the number of accesses when the data storage area is replaced.
- the present invention provides a semiconductor memory storage medium having a partially defective storage area for storing data of a data management unit, a replacement area thereof, and an address registration area of the replacement area.
- a semiconductor memory control device for controlling writing and reading of data, wherein when there is an access request for a storage area, whether the data stored in the storage area is defective is provided in the storage area. It is characterized in that it is determined whether or not the area is an available area by using the indicated defect determination information, and if it is an available area, an access process is executed.
- the storage area when an access request to a storage area is made, error detection and correction are performed using correction information of data stored in the storage area provided in the storage area, and an uncorrectable error is detected. If it is detected, it is judged to be an unusable area, and if there is no error or if a correctable error has been corrected, the storage area has a detection function to detect whether the storage area is defective. It is characterized by detecting whether or not it is defective, determining that it is a usable area if it is not defective, and performing access processing if it is defective, and processing it as an unusable area if it is defective. It is. BRIEF DESCRIPTION OF THE FIGURES
- FIG. 1 is an overall configuration diagram of a semiconductor memory device according to a first embodiment of the present invention
- FIG. 2 is a memory map of a storage medium
- FIG. 3 is an explanatory diagram of block replacement.
- FIG. 4 is a flowchart of an address search process for an access request
- FIG. 5 is a flowchart of an address replacement process in a write access
- FIG. 6 is a flowchart of a second embodiment of the present invention.
- Example semiconductor FIG. 7 is an example of data stored in a management information area
- FIG. 8 is a flowchart for determining an access point
- FIG. 9 is a failure registration area.
- FIG. 10 is a flow chart for judging pass / fail of the access block.
- FIG. 1 is an overall configuration diagram of the present invention, and 1 is an electrically rewritable nonvolatile memory chip which is a storage medium of the semiconductor memory device of the present invention, and a flash memory is the most suitable memory for this. It is conceivable that. It is assumed that the memory chip 1 includes a defective area in a ratio having a predetermined upper limit. It is also assumed that data stored in the memory chip is divided into blocks each having a plurality of data as a unit and managed, and a management information area is provided for each block.
- These storage capacities include, for example, a Hitachi 32 Mbit (4 Mbyte) flash memory chip with a capacity of one block of 512 bytes and a management information area of 16 bytes per block. Have been. Therefore, one chip has 8192 blocks, and has 128 Kbytes as the management information area.
- a memory chip 1 can be used as an example of an optimal memory.
- the total storage capacity, the number of bytes in one block, and the data amount in the management information area are not limited to the above.
- Reference numeral 2 denotes a control circuit of the semiconductor memory device of the present invention, which responds to an external access request or accesses the memory chip 1 and performs processing and control in the device such as management of a defective area and the number of rewrites. It is what you do.
- Reference numeral 3 denotes a memory element for registering a defect, which is rewritable, and DRAM or SRA IV [is optimal for enabling high-speed access.
- ROMs that can be electrically rewritten in byte units can be used, although rewriting takes time and is somewhat expensive. When the power is turned on, the usability is improved because there is no need to load data.
- Reference numeral 5 denotes a system bus for requesting access to the semiconductor memory device 4.
- This bus 5 is generally a peripheral bus for information equipment such as a personal computer.
- 6 and 7 show examples of data stored in the defect registration memory 3, where 6 is an address value of a defective area, and 7 is a replacement address value of a replacement destination of the defective area.
- the adjacent address values correspond to each other, for example, indicating that the area of the defective area address 8H is replaced by the area of the replacement address 0H. In this example, it is assumed that registration of defective area addresses is arranged in ascending order.
- the system bus 5 transmits an access request from the connected information device to the control circuit 2.
- the control circuit 2 decodes the content of the access request and calculates the address of data transmitted with the access request.
- the obtained address value is recognized as the management address.
- the control circuit 2 divides the area in which the defect is registered in the defect registration memory 3 into two parts, and determines which one may be stored. For example, if the number of defective registrations is 10 2 4, access the 5 1 2nd registered address, and if that address is smaller than the previously obtained management address, the management address is stored below it May be stored, and vice versa. Next, the side that may be stored is further divided into two to determine which one may be registered. Similarly, the 256th or 768th registered address is read out and compared with the management address. In this way, the data to be compared is reduced by half. It is finally registered, or if it is, asks for some replacement address values. Of course, when you reduce the registered data by half, if you come across data that is equal to the management address, you can stop the search at that point.
- this method for example, when searching from 102 4 registered data overnight, a simple search requires a maximum of 102 4 searches, and an average of 5 12 searches is required.
- this method can reliably determine the presence and location of management data in up to nine searches. If the management address value is not registered, the data of this management address value does not correspond to a defective area, and can be accessed as normal block data. If the defect is registered, the desired access can be executed by accessing the area of the replacement address value. If the last area of the data storage area is used as the replacement area, execution of access becomes easier.
- FIG. 2 shows a use map of the storage area in this case. 11 is the entire storage area, which includes the normal storage area, the bad block, and the replacement area.
- 1 and 2 is a normal data area, which includes a normal block and a bad block.
- a replacement area 13 occupies the lowest area of the entire storage area.
- 14 is a defective block in the normal data area.
- 15 is a defective block in the replacement area. This indicates that a defective block in the normal data area is replaced in correspondence with a non-defective block in the replacement area.
- the number of blocks is 16 3 8 4 There are 0 blocks. This address value is 18 bits, so bad address registration requires 18 bits more for one registration.
- the upper limit of the number of defects is 5% of the total, up to 8 1 9 There are 2 blocks of defects. This can be expressed in 14 bits.
- FIG. 3 is a diagram for explaining a method of using the management information area in the nonvolatile memory 1.
- 21 is a diagram showing data storage contents of a nonvolatile memory as a storage medium of the storage device of the present invention
- 22 is a physical address of the nonvolatile memory, which is assumed to be 1 (starting from 0).
- 23 is the block at physical address 2, but this block is a bad block.
- 24 is a block of physical address 4
- 25 is a block of physical address 7.
- 30 is the data of the management address 1 stored in the block of the physical address 1
- 31 is the data of the management address 7 stored in the block of the physical address 4
- 32 is the data of the management address 7.
- This is the data of the management address 4 stored. That is, the data of management addresses 4 and 7 have been replaced. This is because the data of the management address 7 was replaced with the data of the physical address 4 in order to suppress the progress of the deterioration of the block of the physical address 7 because the data of the management address 7 was frequently rewritten.
- Reference numerals 26, 27, 28, and 29 denote management information areas corresponding to the blocks of the respective physical addresses, and the management addresses of the data stored in the blocks are registered.
- the control circuit 2 of this semiconductor memory device When the access of the address 1 is requested, the management information area 26 of the physical address 1 is accessed, and if the management address value registered there is 1, by accessing the data of the block, Desired access can be performed. If the management address 4 is accessed in the state of this example, the management information area 28 of the physical address 4 is accessed, and the physical address 7 is accessed from the management address value 7 registered therein. It can be seen that access to the desired management address 4 can be executed.
- management address 4 is rewritten. Move the data to physical address 4, restore it, and then replace it with the next block to be replaced.
- management address 1 is selected as the target. The state after the replacement is shown in Fig. 3 (b).
- management addresses 1, 4, and 7. For example, if access to management address 1 is attempted, management information area 26 of physical address 1 will be accessed first. Then, the management address 7 is obtained, and then the management information area 29 of the physical address 7 is accessed to obtain the management address value 4 and the desired access can be performed. If the replacement continues to occur, the access to the management information area is circulated to perform the desired access, and the access processing performance is significantly reduced.
- FIG. 4 and FIG. 5 show an operation flow of the semiconductor memory device of the present invention.
- FIG. 4 shows a flow for grasping a physical address for knowing where the data of the address of the access request is physically stored when the access request is made.
- the bad address registration memory is divided into two equal parts. For example, if the memory is 64 Kbytes, it is divided into 32 Kbytes.
- the lower head address is accessed. In a 64K byte memory, the address value at that time is 800H.
- the data at the time of accessing this address in the memory (the number of bits in the stored data depends on the total number of defective registered addresses) is compared with the address of the access request, and if the address is larger than the requested address, the address of the request is compared.
- the dress may be on the side where the smaller address of the two is stored, and vice versa.
- the address values in the failure registration memory are arranged in ascending or descending order. Also, at this time, the two address values may match. In this case, since it has been found that a defective address has been registered, the alternative address can be read and accessed as the physical address for which it is requested. Now, the area on the side where the existence is estimated next is divided into two equal parts, and the same is compared with the address of the access request in the same way to estimate which side is located.
- the area is further divided into two equal parts, but eventually the area cannot be divided into two parts. If it does not match the requested address even if it cannot be divided, it means that the address is not registered as defective, and the management area of that physical address is accessed to obtain the management address. If the addresses match, the area is the area for which access was requested, and if they do not match, the area of the physical address equal to the acquired management address value is the area for which access was requested. The processing of this flow is performed both at the lead and at the light. In the read, the physical address obtained by this process is accessed, and the data is sent out, the access process is completed. However, in the write, the process of FIG.
- the data stored in the obtained physical address (1) is unnecessary and is deleted because new data already exists. At this time, it is checked whether or not the physical address (1) needs to be replaced due to frequent rewriting. As an example of this method, the number of rewrites is recorded, and when a certain number of times is reached, it is determined that replacement is necessary. If there is no need to replace the data, the access is completed by writing the given data to the physical address (1). If it is determined that replacement is necessary, the physical address (2) to be replaced is selected next. As an example of the selection method, it is conceivable to search the record of the number of rewrites and select an area with a small number of rewrites.
- the management address value (1) of the physical address (1) to be written next is compared with the physical address value (1), and if they match, the sector is replaced. Since the sector is not in the erased state, the data stored in the physical address (2) to be replaced is written to the erased physical address (1), and the management address given by erasing the physical address (2) is given. If the data of (1) is written therein, the access is completed.
- the replacement must first be canceled. Since the management address value (1) indicates the physical address value (3) to be replaced, the data stored here is transferred to the erased physical address (1), and the replacement is canceled. I do.
- FIG. 6 is a configuration diagram of a flash memory device to which the present invention is applied.
- reference numeral 50 denotes the flash memory card
- 51 denotes a controller to which the present invention is applied
- 52 denotes an electrically rewritable nonvolatile memory as a storage medium (hereinafter referred to as a memory).
- the inside of the memory 52 is divided into regions each having a predetermined size (hereinafter, referred to as blocks in this embodiment), but each block stores a storage data region 5 for storing storage data from a host. 3 and a management information area 54 for storing management information for managing the storage data area 53.
- the storage data area 53 and the management information area 54 are collectively called a block. In the present embodiment, the description is made on the assumption that the memory 52 has a configuration in which the storage data area 53 has 512 bytes and the management information area 54 has 16 bytes. Need not be. 5 5 generates an error correction code for part or all of the data in the storage data area 53, and detects errors occurring in transfer or storage using the generated error correction code.
- the storage data area to be corrected 53 is an ECC (Error Correcting Code) circuit (hereinafter referred to as the data ECC circuit) for 53, and 56 is the ECC circuit for the management information area 54 (hereinafter referred to as the management ECC circuit). ).
- the ECC may include the data to be corrected itself, but in this embodiment, it is treated separately from the data to be corrected.
- Reference numeral 57 denotes an IZF control circuit for exchanging data with the host via the system bus 5 in response to access from a host (not shown) such as a personal computer.
- the system bus 5 refers to a standard interface such as a PC Card Standard and an AT Attachment Interface.
- 5 8 is a host, memory 52, data ECC circuit 5 5 management ECC circuit 56, C is a data transfer control circuit that controls data transfer between buffers to be described later.
- Numeral 59 is a data buffer for temporarily storing data when the stored data 53 is transferred
- 60 is a buffer for the management information area 54
- a buffer for the management information area 54 respectively. Eight sets of 60 and two sets of B are provided.
- Reference numeral 61 denotes a host-side buffer switching circuit that switches between two sets of buffers 59 and 60
- 62 denotes a memory-side buffer switching circuit
- 63 denotes a CPU that controls all of them.
- FIG. 7 shows an example of the contents of the management information area 54.
- Reference numeral 66 denotes an error correction code for data stored in the storage data area 53 generated by the data ECC circuit 55.
- ECC error correction code
- 67 is the type of data stored in the storage data area 53 corresponding to this management information area 54, for example, configuration information data, drive information data, or a normal file.
- An identification code indicating identification such as data, a storage block code for recording a replacement address for deterioration averaging, and 68, which records the degree of deterioration of the block in a predetermined numerical value For the deterioration record, for example, the number of times the block is deleted is appropriate.
- 6 9 is a good block code for storing a predetermined code in each block and examining it at the time of reading to identify whether or not it is defective.70 is an error for the management information area 54.
- This is the correction code (hereinafter referred to as ECC for management).
- ECC correction code
- the management ECC 70 does not need to deal with all data in the management information area 54.
- the data ECC 66 itself is subject to error correction, There is no need to target 70.
- the good block code 69 desirably has excellent error detection capability, and need not have correction capability.
- a host (not shown) connects to the designated address through the system bus 5.
- Command and write data to the host In this embodiment, the flash memory card 50 is made compatible with the hard disk, and writing can be instructed by a cylinder, a head, a sector number, etc. similar to the hard disk. I can do it.
- the data transfer control circuit 58 temporarily stores the write data in the data buffer 59.
- the CPU 63 analyzes the write command and the set value set in advance by the host, performs an address calculation, and searches for a corresponding block in the memory 52 by a method described later.
- the erasure processing is performed.
- the data transfer control circuit 58 writes the storage data in the data buffer 59 to the storage data area 53 of the corresponding block.
- the data ECC 66 is generated by the data ECC circuit 55, and the deterioration record 68 in the management information read from the management information area 54 when searching for a write block is changed according to the new storage.
- the corresponding management ECC 70 is generated by the management ECC circuit 56.
- the data transfer control circuit 58 stores these management information in the management information area 54 of the same block following the writing of the stored data. The stored data and management information are collectively written to the memory 52 as one block.
- the host-side buffer switching circuit 61 and the memory-side buffer switching circuit 62 use the storage data sent from the host and the management information read from the memory 52 in different sets. If control is performed so that the data is stored in the buffer, the time can be reduced by the parallel processing.
- the CPU 63 and the data transfer control circuit 58 search for the corresponding block from the memory 52 according to the read command and store the data in the same manner as when storing. Stored from 5 to 2 overnight Is read and stored in buffer 59. Next, an error in the data in the storage data area 53 is detected using the data ECC 66, and if there is no error, the data is transferred to the host as it is. If an error is detected, the error is corrected and transferred to the host. At the same time, the CPU 63 treats the block as a bad block and performs an alternative process. If an uncorrectable error is detected, the error is reported to the host.
- two sets of data buffers A and B are alternately used to read data from the memory 52 and simultaneously transfer data to the host.
- the deterioration record 68 is examined, and if replacement is necessary, a replacement block is selected by a known method, its contents are read, the storage block code 67 is rewritten, the storage data area 53 and the management information are The contents of area 54 are replaced except for deterioration record 68.
- the deterioration record 68 is updated based on a predetermined method, if necessary.
- the data transfer from the memory 52 is faster than the transfer with the host, it is possible to search for a bad chip / alternate address, which will be described later, using two data buffers for the next block to be accessed in the extra time. And contribute to higher performance.
- FIG. 8 shows the processing from when the access request is received from the host until the CPU 63 determines the physical address value in the memory 52 from the access command.
- the host is aware of the data storage location in memory when accessing. Access without.
- the memory card is assumed to be replaced with a hard disk, the host issues an access command similar to that of the hard disk as described above.
- the CPU 63 receives the above command from the I / F control circuit 57, and calculates a logical address value corresponding to the data storage arrangement in the memory (step 801). Next, the corresponding address in the memory 52 is accessed with the calculated logical address value (step 802), and the management information stored in the management information area 54 is read. In the memory 52, the contents of one block are all read out to the buffer in the memory 52 according to the address, and only the management information or the stored data is sent from the buffer to the controller 51. . From this management information, it is determined whether or not the block is a usable good block (step 803). This determination method will be described later with reference to FIG.
- the process branches to the following process according to the determination result.
- the CPU 63 acquires the storage block code 67 in the management information area 54 read into the buffer 60. (Step 804).
- the replacement address value stored in the storage block code 67 is compared with the logical address value that led to access to this block (step 805), and if they match, the block has not been replaced. Therefore, the block is determined to be an access block and access is made (step 806).
- the read access the stored data is read from the buffer in the memory 52.
- the management information corresponding to the storage data already set in the buffer 59 is generated and written.
- a replacement has occurred and the block corresponding to the replacement address value in the storage block code 67 is an access block. Since it can be determined, the block of the physical address value indicated by the storage block code 67 is newly accessed (step 807). When accessing the replaced block, a good block check may be performed.
- step 803 if it is determined in step 803 that the block is a defective block, a defective registration area described later is newly accessed (step 808). If registered in the defective registration area (step 809), the registration value, that is, the substitute address is obtained, and the block of the corresponding physical address value is accessed (step 810).
- the defect is not registered here, it is a newly generated defective block (step 811), and the block cannot be accessed.
- CPU 63 reports an access error to the host.
- write access since the data is rewritten, there is no need to report the error to the host. Instead, an alternative block is allocated and the data is stored there.
- the CPU 63 writes the substitute block address in the area corresponding to the bad block in the bad registration area 84.
- defect registration information since flash memory access is performed on a block-by-block basis, in order to obtain individual defect registration information, the defect registration information must be read at once and a single access must be made. Therefore, it takes time to access the information at the end of the defect registration area.
- the above method solves this. First, instead of searching for a defective registration area, the corresponding block is accessed using a logical address. According to the present invention, information obtained from the management information area is used to access the defective registration area for the first time when it is determined that the block is defective. W
- the present invention is a method for accessing according to the address information in the storage block code 67 when the block is not defective and has been replaced for the purpose of averaging the number of rewrites.
- the present invention does not store the substitute block information in the storage block code 67 or the like. This is a method of placing it in a separate defect registration area.
- the access to the defect registration area is affected by the above-mentioned single access, but does not pose a problem because the defect occurrence rate is low.
- FIG. 9 shows an example of a memory map inside the memory 52 and the contents registered in the storage data area 53 of one block in the defect registration area.
- 81 is the entire storage area or a part of the storage area, that is, a memory map such as one chip of the memory
- 82 is a group of general storage blocks that store data corresponding to the logical address value in the memory map.
- Reference numeral 83 denotes an alternative block group for storing data in place of a defective block existing or generated in a general storage block
- reference numeral 84 denotes a defective registration area for registering an alternative address when the replacement is performed.
- an alternative address is registered in the storage data area 53.
- the defect registration area 84 has a registration area for all blocks of the general storage block group 82, and each block of the general storage block group 82 and the corresponding registration area in the defect registration area 84 have the same registration area. Are associated.
- the addresses are assigned to the defect registration area in the order of the address of the general storage block.
- the present invention is not limited to this.
- two bytes are assigned to one block for defect registration, and 85 is the block (address 0000) of the general storage block 82.
- the value indicating non-defectiveness may be any value that cannot be used as a substitute block address, but in order to simplify the determination as to whether or not a defect has been registered in step 809 in FIG. It is desirable to set all bits to 1 or 0.
- the general storage block addresses 0000 and 007 indicate that they are replaced with the alternative block addresses 004 and 005, respectively.
- the alternative address the address allocation within the alternative block group 83 is sufficient, so that registration can be performed with a small number of bytes. It is possible to determine whether or not a defect is registered based on whether the registered value is FFFF or an address value other than FFFF is stored. It is desirable to generate ECC also in the defect registration area 84 to improve reliability.
- the ECC circuit can be applied in the same procedure as a general storage block.
- FIG. 10 is a flow chart for judging whether a block is good or bad, and explains in detail the good block check (step 803) in the entire flow chart of FIG.
- the CPU 63 accesses the corresponding block according to the obtained logical address, and reads the management information in the management information area 54 (step 1001).
- Management information obtained using ECC 70 for management of read management information (Step 1002).
- the good block code 69 stores a specific code common to all blocks as described in FIG. If no error was detected in the check by the management ECC 70 but the good block code 69 did not match, it is determined that an erroneous detection has occurred. In other words, it is a phenomenon that occurs when the occurrence of an error happens to coincide with the code without an error.
- the good block code 69 does not match despite the error correction processing, the error occurrence coincides with the correctable code by accident and the error is corrected. Then, it is considered that a defective block has been performed, and the process proceeds to the search processing of the defective registration area 84. Otherwise, it is judged that there is no error and that the block is a corrected good block.
- the management information of the block corresponding to the logical address is checked to determine whether it is good or not. Therefore, compared to the method of searching for the failure registration information first, the controller 51 and the memory 52 are used. The number of accesses to the data is reduced, and the access time from the viewpoint of the host until obtaining the target data is shortened.
- the buffer in the memory 52 and the buffers 59, 60 in the controller 51 can be integrated.
- the effect that the circuit scale can be reduced is obtained.
- a signal line between the controller 51 and the memory 52 is not required, a package having a smaller number of terminals can be used.
- the capacity of a memory used for registering a conversion address due to replacement or replacement of an address can be reduced or deleted. Fast search for defects. Therefore, high-speed access and low cost can be achieved.
- addresses can be searched at high speed, and access performance can be improved.
Description
Claims
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
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US09/125,547 US6031758A (en) | 1996-02-29 | 1996-11-29 | Semiconductor memory device having faulty cells |
AU38322/97A AU3832297A (en) | 1996-02-29 | 1996-11-29 | Semiconductor memory device having faulty cells |
JP53077897A JP3614173B2 (ja) | 1996-02-29 | 1996-11-29 | 部分不良メモリを搭載した半導体記憶装置 |
KR1019980706636A KR100308173B1 (ko) | 1996-02-29 | 1996-11-29 | 부분불량메모리를탑재한반도체기억장치 |
US09/477,665 US6236601B1 (en) | 1996-02-29 | 2000-01-05 | Semiconductor memory device having faulty cells |
US09/824,778 US6317371B2 (en) | 1996-02-29 | 2001-04-04 | Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory |
US11/931,881 US7616485B2 (en) | 1996-02-29 | 2007-10-31 | Semiconductor memory device having faulty cells |
US12/615,502 US8064257B2 (en) | 1996-02-29 | 2009-11-10 | Semiconductor memory device having faulty cells |
US13/298,548 US8503235B2 (en) | 1996-02-29 | 2011-11-17 | Nonvolatile memory with faulty cell registration |
US13/960,140 US9007830B2 (en) | 1996-02-29 | 2013-08-06 | Semiconductor memory device having faulty cells |
Applications Claiming Priority (2)
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JP4245196 | 1996-02-29 | ||
JP8/42451 | 1996-02-29 |
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US09/125,547 A-371-Of-International US6031758A (en) | 1996-02-29 | 1996-11-29 | Semiconductor memory device having faulty cells |
US09/477,665 Continuation US6236601B1 (en) | 1996-02-29 | 2000-01-05 | Semiconductor memory device having faulty cells |
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US (11) | US6031758A (ja) |
JP (3) | JP3614173B2 (ja) |
KR (1) | KR100308173B1 (ja) |
AU (1) | AU3832297A (ja) |
WO (1) | WO1997032253A1 (ja) |
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US8793555B2 (en) | 2008-02-29 | 2014-07-29 | Kabushiki Kaisha Toshiba | Method of controlling a semiconductor storage device |
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US9176816B2 (en) | 2008-03-01 | 2015-11-03 | Kabushiki Kaisha Toshiba | Memory system configured to control data transfer |
US8787101B2 (en) | 2008-10-07 | 2014-07-22 | Micron Technology, Inc. | Stacked device remapping and repair |
JP2012505491A (ja) * | 2008-10-07 | 2012-03-01 | マイクロン テクノロジー, インク. | スタック型デバイスの再マッピングおよび補修 |
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Also Published As
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US6728138B2 (en) | 2004-04-27 |
US20010036114A1 (en) | 2001-11-01 |
US20140185380A1 (en) | 2014-07-03 |
US6388920B2 (en) | 2002-05-14 |
AU3832297A (en) | 1997-09-16 |
JP2008204475A (ja) | 2008-09-04 |
US6317371B2 (en) | 2001-11-13 |
US20030128585A1 (en) | 2003-07-10 |
US20010015908A1 (en) | 2001-08-23 |
US8064257B2 (en) | 2011-11-22 |
JP3614173B2 (ja) | 2005-01-26 |
US20020097604A1 (en) | 2002-07-25 |
US6236601B1 (en) | 2001-05-22 |
US6542405B2 (en) | 2003-04-01 |
US9007830B2 (en) | 2015-04-14 |
US20100177579A1 (en) | 2010-07-15 |
US20080055986A1 (en) | 2008-03-06 |
US20040022249A1 (en) | 2004-02-05 |
US6031758A (en) | 2000-02-29 |
KR100308173B1 (ko) | 2001-11-02 |
JP2010192002A (ja) | 2010-09-02 |
US20120213002A1 (en) | 2012-08-23 |
JP4563465B2 (ja) | 2010-10-13 |
US8503235B2 (en) | 2013-08-06 |
KR19990087236A (ko) | 1999-12-15 |
JP5095777B2 (ja) | 2012-12-12 |
US7616485B2 (en) | 2009-11-10 |
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