WO1997034233A1 - Method and apparatus for performing direct memory access (dma) byte swapping - Google Patents
Method and apparatus for performing direct memory access (dma) byte swapping Download PDFInfo
- Publication number
- WO1997034233A1 WO1997034233A1 PCT/US1997/003357 US9703357W WO9734233A1 WO 1997034233 A1 WO1997034233 A1 WO 1997034233A1 US 9703357 W US9703357 W US 9703357W WO 9734233 A1 WO9734233 A1 WO 9734233A1
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- WO
- WIPO (PCT)
- Prior art keywords
- dma
- memory
- data
- bytes
- command
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000002093 peripheral effect Effects 0.000 claims abstract description 9
- 230000004044 response Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Definitions
- the present invention pertains to the field of computer systems. More particularly, the present invention relates to performing byte swapping during data transfers in a computer system.
- Computer systems generally operate upon binary data items that are anywhere between one and eight bytes in length, where a "byte” is defined as eight bits.
- a "byte” is defined as eight bits.
- the smallest data item that a modern computer system will operate on is either a "word”, which is two bytes, or a “double-word” (“dword”), which is four bytes.
- dword double-word
- One possible reason byte swapping may be desirable, for example, is to switch back and forth between different methods of addressing data, such as between "little- endian” addressing, in which a memory address refers to the lowest- order byte of a data item, and "big-endian” addressing, in which an address specifies the highest-order byte of a data item.
- byte swapping is generally performed by the host processor in response to software commands.
- a new location i.e., a different location in memory or a peripheral device
- the host processor would typically read the data from the memory, rearrange the bytes, and then write back the rearranged data words to the first block of memory- Then, the host would write the modified data words into the new location.
- This method has the disadvantage of being time-consuming, because the host processor must write back the modified data before transferring the data to the new location. Hence, what is needed is a faster and more efficient way to perform byte swapping during memory access operations.
- the apparatus comprises a direct memory access (DMA) controller coupled to a bus interface.
- the bus interface provides a connection to a bus, to which a memory is also coupled.
- the DMA controller accesses data words stored in the memory, wherein each data word includes at least two bytes, and swaps the bytes of at least one of the data words according to a control input.
- Figure 1 illustrates a computer system in which the present invention is implemented.
- Figure 2 illustrates circuitry on a graphics accelerator card in the computer system of Figure 1.
- Figure 3 illustrates control flow between a DMA controller and a host system during a DMA operation.
- Figure 4A illustrates a direct memory access (DMA) command pair.
- DMA direct memory access
- Figure 4B is a table illustrating a byte swapping scheme.
- Figure 5 is a flow diagram illustrating a technique for performing DMA byte swapping.
- Figure 6 illustrates circuitry in a DMA controller for performing DMA byte swapping during memory read operations.
- Figure 7 illustrates circuitry in DMA controller for performing DMA byte swapping during memory write operations.
- DMA direct memory access
- FIG. 1 illustrates a computer system 1 in which the present invention is implemented.
- the computer systems includes a central processing unit (CPU) 10 coupled to a memory 20 by a system bus 30.
- the system bus 30 is coupled to a PCI (peripheral component interconnect) bus 40 by a bus interface 50.
- PCI peripheral component interconnect
- Coupled the PCI bus 40 are a graphics accelerator card 60, which is coupled to a monitor 70, as well as a number of other peripheral devices 80 and 90.
- the present invention is implemented within graphics accelerator card 60.
- FIG. 2 illustrates the graphics accelerator card 60 is shown in greater detail.
- Graphics accelerator card 60 includes a graphics processor 102, which is designed to control and perform various graphics functions.
- Graphics processor 102 is coupled to a local memory 106 through a memory interface 105 and to a pixel engine 104.
- Local memory 106 includes a frame buffer for storing pixel color values that are to be displayed on the monitor 70. Color values stored in the frame buffer are provided to the monitor in the form of RGB (red, green, blue) analog signals via display interface 107.
- the graphics accelerator card 60 is coupled to the PCI bus 40 by a PCI interface 100.
- a direct memory access (DMA) controller 101 which is coupled to PCI interface 100, controls DMA operations performed on any memory within the computer system 1, such as main memory 20, that are required to support operation of card 60.
- Information received by the graphics accelerator card 60 over PCI bus 40 is provided to the graphics processor via an input FIFO 103, while information to be output onto the PCI bus 40 by the graphics processor 102 is provided to the PCI interface 100 via an output FIFO 108.
- byte swapping is performed by DMA controller 101 under the control of a state machine in the PCI interface 100.
- the DMA controller is a PCI bus master which executes DMA operations that are specified by command pairs in a chained DMA command list.
- Figure 3 illustrates an example of a chained command list 24, which is stored in memory 20.
- the command list 24 is generated by graphics driver software 22 supporting the graphics accelerator card 60 and is also stored in memory 20.
- Each DMA command pair consists of an Address field in the even dword and a Length field in the odd dword.
- Figure 4A illustrates a DMA command pair, including Address field 211 and Length field 212.
- the Address field provides a word-aligned physical byte address of either: 1) the first dword of data in the data array 26 that is to be accessed for that command, or 2) the (link) address of the next DMA command to be executed.
- the Length field specifies the size of the DMA transfer when the Address field specifies an address in the data array 26.
- the most significant bit of the Length field, bit L31 is used to indicate whether the address specifies the location of data or a link to another DMA command. Specifically, a value of 1 for bit L31 indicates that the Address field specifies a link to another DMA command.
- bits Lo and Li of each DMA command are not required for addressing data. Therefore, the two least significant bits of the Length field, bits Lo and Li (where Lo is the least significant bit), are used in the present invention to indicate the byte swapping scheme for a memory access. For each DMA command, the values of bits Lo and Li are set by the graphics driver software 22 based on the graphics requirements of whatever application software is currently nmning in the computer system 1. Note that bits Lo and Li are ignored if bit L31 is set to 1, since the Address field specifies a link to another DMA command in such cases.
- Figures 4A and 4B illustrate how DMA commands are used to implement a byte swapping scheme.
- a DMA command consists of an Address field 211 and a Length field 212.
- the Length field 212 includes the bit pair 'LlLo'.
- the value of bit pair 'LlLo' determines the byte swapping scheme, as shown in Figure 4B.
- each data item is a dword consisting of four bytes, Bo through B3, where byte Bo is the lowest order byte and byte B3 is the highest order byte.
- FIG. 3 illustrates the control flow during a DMA operation.
- the DMA controller 101 includes a DMA command pointer register 220 and a DMA command register 222.
- the DMA command pointer register 220 stores the physical byte address of the current DMA command pair.
- the DMA command register 222 holds the values of the DMA command pair currently being executed.
- a DMA operation is initiated by the graphics driver 22 writing the address of the first DMA command of the DMA command list to the DMA command pointer register 220.
- the DMA controller 101 begins executing DMA commands (i.e., command pairs) in the chained DMA command list 24.
- a null value in the Address field terminates the DMA operation.
- the value in the DMA command pointer register 220 is incremented by eight bytes to correspond to the byte location of the next DMA command pair.
- the DMA controller 101 first checks the DMA command pointer register 220 to determine if an address of a DMA command pair has been written to the register 200 (step 501). If an address has been written to the DMA command pointer register 220, then the DMA controller 101 gets from the command list the DMA command pair pointed to by the DMA command pointer register 220 and stores that command pair in register 222 (step 502). A determination is then made (step 503) as to whether the value of the Address field of the current DMA command pair is null. If the value of the Address field is null, then the operation is terminated. If the value is not null, then bit L31 of the Length field is examined (step 504).
- bit L31 is 1 (i.e., the Address field specifies a link to the next DMA command pair), then the DMA controller 101 replaces the value in the DMA command pointer register with the link address specified by the Address field (step 505) and replaces the contents of the DMA command register 222 with the command pair at the link address (step 502).
- bit L31 is 0 (i.e., the Address field specifies an address in the data array 26)
- the DMA controller reads the data addressed by the current DMA command (step 506) and swaps the bytes within each dword of data according to bits Lo and Li of the current Length field (step 507). Byte swapping occurs as each data item (dword) is transferred from memory 20 to graphics accelerator card 60.
- the DMA command pointer register 220 is incremented once again by eight bytes (step 508) in order to load the next command pair.
- FIG. 6 illustrates circuitry for implementing DMA byte swapping as described above.
- the DMA controller 101 includes a multiplexor 110 having inputs coupled to the PCI bus 40 and an output which is provided to FIFO 103 via the PCI interface 100.
- Multiplexor 110 has four inputs which are selected based on bits LQ and Li of the Length field of the current DMA command.
- Each input of multiplexor 110 receives the same 32 bit lines from the PCI bus 40. However, the arrangement of the bit lines is different for each input and corresponds to one of the four byte swapping formats described with reference to Figure 4B.
- each bit position applied to input '00' receives the corresponding bit position of the PCI bus 40; however, for input '01', the eight least significant bit positions receive bits 24 through 31 of the PCI bus (i.e., PCI[31:24]), and the eight most significant bit positions of input '01' receive bits 0 through 7 of the PCI bus 40 (i.e., PCI[7:0]).
- Figure 7 shows circuitry in an embodiment capable of performing DMA byte swapping during memory write operations.
- a second multiplexor 112 is provided within the DMA controller 101. Multiplexor 112 receives four 32-bit inputs, each from output FIFO 108. The ordering of the bit lines for each input is arranged according to one of the four byte swapping formats illustrated in Figure 4B, as explained with respect to Figure 6. Multiplexor 112 provides one 32-bit output to PCI bus 40. Selection of the four inputs of multiplexor 112 is again determined by the values of bits 'LlLo' of the current DMA command.
- multiplexors such as those illustrated in Figures 6 and 7 is only one possible way of implementing byte swapping within a DMA controller. Other ways of selecting byte ordering within a DMA controller may be utilized within the scope of the present invention.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002249389A CA2249389C (en) | 1996-03-15 | 1997-03-04 | Method and apparatus for performing direct memory access (dma) byte swapping |
AU19859/97A AU1985997A (en) | 1996-03-15 | 1997-03-04 | Method and apparatus for performing direct memory access (dma) byte swapping |
JP53265897A JP3940435B2 (en) | 1996-03-15 | 1997-03-04 | Method and apparatus for performing direct memory access (DMA) byte swapping |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/616,594 US5862407A (en) | 1996-03-15 | 1996-03-15 | System for performing DMA byte swapping within each data element in accordance to swapping indication bits within a DMA command |
US08/616,594 | 1996-03-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997034233A1 true WO1997034233A1 (en) | 1997-09-18 |
Family
ID=24470170
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/003357 WO1997034233A1 (en) | 1996-03-15 | 1997-03-04 | Method and apparatus for performing direct memory access (dma) byte swapping |
Country Status (6)
Country | Link |
---|---|
US (1) | US5862407A (en) |
JP (1) | JP3940435B2 (en) |
CN (1) | CN1105360C (en) |
AU (1) | AU1985997A (en) |
CA (1) | CA2249389C (en) |
WO (1) | WO1997034233A1 (en) |
Families Citing this family (19)
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EP0837397B1 (en) * | 1996-10-18 | 2006-04-05 | Matsushita Electric Industrial Co., Ltd. | Data transfer apparatus and data transfer system for arbitrating a plurality of I/O ports in DMA |
US6711636B1 (en) * | 1999-09-29 | 2004-03-23 | Silicon Graphics, Inc. | Transfer attribute encoding within an address on a bus |
AU6420001A (en) * | 2000-06-02 | 2001-12-11 | Mellanox Technologies Ltd. | Dma doorbell |
US6678755B1 (en) * | 2000-06-30 | 2004-01-13 | Micron Technology, Inc. | Method and apparatus for appending memory commands during a direct memory access operation |
JP4514173B2 (en) * | 2000-10-13 | 2010-07-28 | キヤノン株式会社 | Data processing method and image processing apparatus |
US7016987B2 (en) * | 2001-06-21 | 2006-03-21 | Integrated Device Technology, Inc. | Transaction aligner microarchitecture |
US6799232B1 (en) | 2001-12-05 | 2004-09-28 | Zarlink Semiconductor V.N., Inc. | Automatic byte swap and alignment for descriptor-based direct memory access data transfers |
US20050038946A1 (en) * | 2003-08-12 | 2005-02-17 | Tadpole Computer, Inc. | System and method using a high speed interface in a system having co-processors |
JP2005092742A (en) * | 2003-09-19 | 2005-04-07 | Toshiba Corp | Video output controller and video card |
KR101034493B1 (en) * | 2004-01-09 | 2011-05-17 | 삼성전자주식회사 | Image transforming apparatus, dma apparatus for image transforming, and camera interface supporting image transforming |
US7904943B2 (en) * | 2004-12-28 | 2011-03-08 | O'connor Dennis M | Secure controller for block oriented storage |
CN100357871C (en) * | 2005-06-30 | 2007-12-26 | 华为技术有限公司 | Apparatus and method for supporting external storage device interface mode switching |
JP4747077B2 (en) * | 2006-11-16 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | Arithmetic circuit |
CN101482853B (en) * | 2008-01-10 | 2010-10-27 | 松翰科技股份有限公司 | Direct memory access system and method |
US8694701B2 (en) | 2011-12-15 | 2014-04-08 | Mellanox Technologies Ltd. | Recovering dropped instructions in a network interface controller |
CN104516840B (en) * | 2013-09-29 | 2017-08-29 | 联想(北京)有限公司 | Information processing method and message processing device |
DE102016211768A1 (en) * | 2016-06-29 | 2018-01-04 | Robert Bosch Gmbh | Memory direct access control device and method of operation therefor |
CN111240581B (en) * | 2018-11-29 | 2023-08-08 | 北京地平线机器人技术研发有限公司 | Memory access control method and device and electronic equipment |
CN115237962A (en) * | 2022-09-20 | 2022-10-25 | 南京芯驰半导体科技有限公司 | Data searching method and device |
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US5168561A (en) * | 1990-02-16 | 1992-12-01 | Ncr Corporation | Pipe-line method and apparatus for byte alignment of data words during direct memory access transfers |
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1996
- 1996-03-15 US US08/616,594 patent/US5862407A/en not_active Expired - Lifetime
-
1997
- 1997-03-04 JP JP53265897A patent/JP3940435B2/en not_active Expired - Fee Related
- 1997-03-04 AU AU19859/97A patent/AU1985997A/en not_active Abandoned
- 1997-03-04 WO PCT/US1997/003357 patent/WO1997034233A1/en active Application Filing
- 1997-03-04 CA CA002249389A patent/CA2249389C/en not_active Expired - Fee Related
- 1997-03-04 CN CN97194399.0A patent/CN1105360C/en not_active Expired - Lifetime
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US5317715A (en) * | 1987-12-15 | 1994-05-31 | Advanced Micro Devices, Inc. | Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics |
US5168561A (en) * | 1990-02-16 | 1992-12-01 | Ncr Corporation | Pipe-line method and apparatus for byte alignment of data words during direct memory access transfers |
Also Published As
Publication number | Publication date |
---|---|
AU1985997A (en) | 1997-10-01 |
CA2249389C (en) | 2002-07-09 |
JP2000510973A (en) | 2000-08-22 |
JP3940435B2 (en) | 2007-07-04 |
CN1218564A (en) | 1999-06-02 |
US5862407A (en) | 1999-01-19 |
CN1105360C (en) | 2003-04-09 |
CA2249389A1 (en) | 1997-09-18 |
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