WO1997042706A1 - Circuit arrangement for generating random bit sequences - Google Patents

Circuit arrangement for generating random bit sequences Download PDF

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Publication number
WO1997042706A1
WO1997042706A1 PCT/DE1997/000831 DE9700831W WO9742706A1 WO 1997042706 A1 WO1997042706 A1 WO 1997042706A1 DE 9700831 W DE9700831 W DE 9700831W WO 9742706 A1 WO9742706 A1 WO 9742706A1
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WO
WIPO (PCT)
Prior art keywords
oscillator
circuit arrangement
random bit
controlled
voltage
Prior art date
Application number
PCT/DE1997/000831
Other languages
German (de)
French (fr)
Inventor
Hans-Heinrich Viehmann
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to EP97924868A priority Critical patent/EP0897613A1/en
Priority to JP9539414A priority patent/JPH11509707A/en
Priority to BR9708977A priority patent/BR9708977A/en
Publication of WO1997042706A1 publication Critical patent/WO1997042706A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B29/00—Generation of noise currents and voltages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator

Definitions

  • random bit sequences In many data processing operations, in particular in the case of such a cryptographic type, bit sequences with a random distribution of ones and zeros, hereinafter referred to as random bit sequences, are required. Such a random bit sequence of defined length can be regarded as a random number.
  • pseudo-random numbers that are generated with feedback shift registers.
  • pseudo-random numbers are only random to the extent that even with a large number of successive output values from a pseudo-random generator, the next value cannot be concluded.
  • they have a periodicity that depends on the length of the shift register used.
  • the output data of the shift register are clearly dependent on the input data and the architecture of the shift register.
  • the object of the present invention is therefore to provide a circuit arrangement for generating real random bit sequences.
  • the relative phase position of the output signals of two oscillators is evaluated digitally.
  • One of the oscillators vibrates at an almost constant frequency, while the other oscillator is modulated in frequency. With a sufficient frequency hub dominates the quantization noise. This creates a random bit sequence that can be used as a random number.
  • frequency modulation is carried out in a particularly advantageous manner by a further oscillator, which preferably oscillates at a different frequency. Its output signal advantageously has a sawtooth profile.
  • this further oscillator can also be provided by an additional one
  • Oscillator can be frequency modulated and this can also be frequency modulated, etc.
  • the frequency-modulated oscillators are designed as voltage-controlled oscillators, so that they can be controlled directly from the output of another oscillator.
  • phase position can advantageously be detected in a particularly simple manner by means of a shift register, the data input of which is preferably supplied with the frequency-modulated oscillator signal and the clock input of which is supplied with the oscillator signal of constant frequency.
  • the oscillator with constant frequency can be replaced by a frequency-modulated oscillator.
  • the sliding register is fed back.
  • FIG. 1 shows a basic circuit diagram of a circuit arrangement according to the invention and FIG. 2 shows a basic circuit diagram of a voltage-controlled oscillator.
  • a second input signal out2 of a first oscillator OSZ1 is applied to a first input of a phase detector PD.
  • the second input of the phase detector PD is acted upon by the second output signal out2 of a first voltage-controlled oscillator VCOI.
  • the respective second output signals out2 of the oscillators OSZl, VCOI have an approximately rectangular course.
  • the oscillators OSZl, VCOI also deliver first output signals outl with an approximately sawtooth-shaped course.
  • the first voltage-controlled oscillator VCOI is controlled by a second voltage-controlled oscillator VC02 and this possibly via further voltage-controlled oscillators, which are not shown but are indicated by a dashed line, by a freely oscillating second oscillator OSZ2 with its first output signal outl.
  • the first oscillator OSZ1 can also be designed as a voltage-controlled oscillator and in turn can be controlled via one or a chain of several oscillators or voltage-controlled oscillators with their first output signals outl. This is indicated in FIG. 1 by an oscillator OSZ shown in broken lines.
  • the phase detector PD can advantageously be formed with a shift register familiar to the person skilled in the art.
  • the second output signal out2 of the first oscillator OSZ1 is preferably fed to the data input of the shift register and the second output signal out2 of the first voltage-controlled oscillator VCOI is fed to the clock input of the shift register.
  • the shift register acting as a phase detector PD can be designed to be feedback.
  • the output signal of the shift register is logically combined with the data input signal and only then fed to the input of the shift register. It is also possible to logically link intermediate taps of the shift register with one another and to return them to the input.
  • FIG. 2 shows the basic structure of a digital voltage controlled oscillator.
  • the output of an inverter INV is connected via a capacitor C to ground and also to the input of a comparator ST designed as a Schmitt trigger.
  • the output out2 of the comparator ST provides an approximately rectangular signal shape and is fed back to the input of the inverter INV. For example, if the state at the output of the inverter INV corresponds to a logic "1", the capacitor C is charged. If the voltage across capacitor C exceeds the threshold of comparator ST, it switches: at its output out2, which also forms the oscillator output, a logical "1" also appears. This is fed back to the input of the inverter INV, so that the state at its output changes to a logic "0". As a result, the capacitor C discharges again, so that the comparator ST switches over again after a certain time. This gives a periodic
  • Vibration occurs, the frequency of which is essentially determined by the capacitance of the capacitor C and resistances in the load paths of the inverter INV.
  • These resistors can be designed to be controllable, for example, as shown in FIG. 2, by p- and n-MOS transistors, which in each case between the positive supply voltage connection and the p-MOS transistor of the actual inverter or between the n-MOS transistor of the inverter and the negative supply voltage connection.
  • Two complementary control signals in1, in2 must be supplied to this controllable inverter INV.
  • the basic frequency of the voltage-controlled oscillator is determined by the size of the capacitance of the capacitor C.
  • the frequency is varied by means of the control signals in1, in2 by varying the resistances of the load paths of the inverter INV.
  • the circuit arrangement according to the invention can be used to generate real random bit sequences which can be used as random numbers in cryptographic data processing operations.

Abstract

A circuit arrangement for generating random bit sequences has a first oscillator (OSZ1) and a second oscillator (VCO1) whose outputs are connected to the inputs of a phase detector (PD) that generates the random bit sequence. The second oscillator (VCO1) is frequency modulated.

Description

Beschreibungdescription
Schaltungsanordnung zum Erzeugen zufälliger BitfolgenCircuit arrangement for generating random bit sequences
Bei vielen Datenverarbeitungsvorgängen, insbesondere bei sol¬ chen kryptografischer Art, werden Bitfolgen mit zufälliger Verteilung der Einsen und Nullen, im folgenden zufällige Bit¬ folgen genannt, benötigt. Eine solche zufällige Bitfolge de¬ finierter Länge kann als Zufallszahl angesehen werden.In many data processing operations, in particular in the case of such a cryptographic type, bit sequences with a random distribution of ones and zeros, hereinafter referred to as random bit sequences, are required. Such a random bit sequence of defined length can be regarded as a random number.
Es ist üblich, sogenannte Pseudozufallszahlen zu verwenden, die mit rückgekoppelten Schieberegistern erzeugt werden. Pseudozufallszahlen sind aber nur insofern zufällig, als auch bei einer großen Zahl aufeinanderfolgender Ausgangswerte ei- nes Pseudozufallsgenerators nicht auf den nächsten Wert ge¬ schlossen werden kann. Sie weisen aber eine Periodizität auf, die von der Länge des verwendeten Schieberegisters abhängt . Außerdem sind die Ausgangsdaten des Schieberegisters eindeu¬ tig von den Eingangsdaten und der Architektur des Schiebere- gisters abhängig.It is common to use so-called pseudo-random numbers that are generated with feedback shift registers. However, pseudo-random numbers are only random to the extent that even with a large number of successive output values from a pseudo-random generator, the next value cannot be concluded. However, they have a periodicity that depends on the length of the shift register used. In addition, the output data of the shift register are clearly dependent on the input data and the architecture of the shift register.
Echte Zufallszahlen sind in digitalen Schaltungen bisher noch nicht bekannt.True random numbers are not yet known in digital circuits.
Die Aufgabe vorliegender Erfindung ist es daher, eine Schal¬ tungsanordnung zum Erzeugen echter zufälliger Bitfolgen anzu¬ geben.The object of the present invention is therefore to provide a circuit arrangement for generating real random bit sequences.
Die Aufgabe wird durch eine Schaltungsanordnung gemäß An- spruch 1 gelöst. Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen angegeben.The object is achieved by a circuit arrangement according to claim 1. Advantageous developments of the invention are specified in the subclaims.
Bei der erfindungsgemäßen Schaltungsanordnung wird die rela¬ tive Phasenlage der Ausgangssignale zweier Oszillatoren digi- tal ausgewertet. Einer der Oszillatoren schwingt mit einer nahezu konstanten Frequenz, während der andere Oszillator in der Frequenz moduliert ist. Bei einem ausreichenden Frequenz- hub dominiert das Quantisierungsrauschen. So entsteht eine zufällige Bitfolge, die als Zufallszahl verwendet werden kann.In the circuit arrangement according to the invention, the relative phase position of the output signals of two oscillators is evaluated digitally. One of the oscillators vibrates at an almost constant frequency, while the other oscillator is modulated in frequency. With a sufficient frequency hub dominates the quantization noise. This creates a random bit sequence that can be used as a random number.
Die Frequenzmodulation erfolgt in Weiterbildung der Erfindung in besonders vorteilhafter Weise durch einen weiteren Oszil¬ lator, der bevorzugt mit einer anderen Frequenz schwingt. Sein Ausgangssignal weist in vorteilhafter Weise einen Säge¬ zahnverlauf auf. Auch dieser weitere Oszillator kann in wei- terer Weiterbildung der Erfindung durch einen zusätzlichenIn a further development of the invention, frequency modulation is carried out in a particularly advantageous manner by a further oscillator, which preferably oscillates at a different frequency. Its output signal advantageously has a sawtooth profile. In a further development of the invention, this further oscillator can also be provided by an additional one
Oszillator frequenzmoduliert werden und auch dieser kann fre¬ quenzmoduliert sein usw.Oscillator can be frequency modulated and this can also be frequency modulated, etc.
Die frequenzmodulierten Oszillatoren sind in vorteilhafter Ausbildung als spannungsgesteuerte Oszillatoren ausgeführt, so daß sie direkt vom Ausgang eines anderen Oszillators ange¬ steuert werden können.In an advantageous embodiment, the frequency-modulated oscillators are designed as voltage-controlled oscillators, so that they can be controlled directly from the output of another oscillator.
Die Detektion der Phasenlage kann in vorteilhafter da beson- ders einfacher Weise durch ein Schieberegister erfolgen, des¬ sen Dateneingang bevorzugt mit dem frequenzmodulierten Oszil¬ latorsignal und dessen Takteingang mit dem Oszillatorsignal konstanter Frequenz beaufschlagt ist.The phase position can advantageously be detected in a particularly simple manner by means of a shift register, the data input of which is preferably supplied with the frequency-modulated oscillator signal and the clock input of which is supplied with the oscillator signal of constant frequency.
Der Oszillator mit konstanter Frequenz kann in Weiterbildung der Erfindung durch einen frequenzmodulierten Oszillator er¬ setzt werden.In a development of the invention, the oscillator with constant frequency can be replaced by a frequency-modulated oscillator.
In vorteilhafter Weiterbildung der Erfindung ist das Schiebe- register rückgekoppelt.In an advantageous development of the invention, the sliding register is fed back.
Die Erfindung wird nachfolgend anhand eines Ausführungsbei- spieles mit Hilfe von Figuren näher erläutert. Dabei zeigenThe invention is explained in more detail below on the basis of an exemplary embodiment with the aid of figures. Show
Figur 1 ein Prinzipschaltbild einer erfindungsgemäßen Schal¬ tungsanordnung und Figur 2 ein Prinzipschaltbild eines spannungsgesteuerten Os¬ zillators.1 shows a basic circuit diagram of a circuit arrangement according to the invention and FIG. 2 shows a basic circuit diagram of a voltage-controlled oscillator.
Gemäß Figur 1 ist ein erster Eingang eines Phasendetektors PD mit dem zweiten Ausgangssignal out2 eines ersten Oszillators OSZl beaufschlagt. Der zweite Eingang des Phasendetektors PD ist mit dem zweiten Ausgangssignal out2 eines ersten span¬ nungsgesteuerten Oszillators VCOI beaufschlagt.According to FIG. 1, a second input signal out2 of a first oscillator OSZ1 is applied to a first input of a phase detector PD. The second input of the phase detector PD is acted upon by the second output signal out2 of a first voltage-controlled oscillator VCOI.
Die jeweiligen zweiten Ausgangssignale out2 der Oszillatoren OSZl, VCOI haben einen etwa rechteckigen Verlauf. Die Oszil¬ latoren OSZl, VCOI liefern auch erste Ausgangssignale outl mit etwa sägezahnförmigem Verlauf.The respective second output signals out2 of the oscillators OSZl, VCOI have an approximately rectangular course. The oscillators OSZl, VCOI also deliver first output signals outl with an approximately sawtooth-shaped course.
Der erste spannungsgesteuerte Oszillator VCOI wird von einem zweiten spannungsgesteuerten Oszillator VC02 und dieser even¬ tuell über weitere ≤pannungsgesteuerte Oszillatoren, die nicht dargestellt sind jedoch durch eine strichlierte Linie angedeutet sind, von einem freischwingenden zweiten Oszilla- tor OSZ2 mit dessen erstem Ausgangssignal outl angesteuert. Prinzipiell kann auch der erste Oszillator OSZl als span¬ nungsgesteuerter Oszillator ausgebildet sein und seinerseits über einen oder über eine Kette von mehreren Oszillatoren bzw. spannungsgesteuerten Oszillatoren mit deren ersten Aus- gangssignalen outl angesteuert werden. Dies ist in Figur 1 durch einen strichliert dargestellten Oszillator OSZ angedeu¬ tet.The first voltage-controlled oscillator VCOI is controlled by a second voltage-controlled oscillator VC02 and this possibly via further voltage-controlled oscillators, which are not shown but are indicated by a dashed line, by a freely oscillating second oscillator OSZ2 with its first output signal outl. In principle, the first oscillator OSZ1 can also be designed as a voltage-controlled oscillator and in turn can be controlled via one or a chain of several oscillators or voltage-controlled oscillators with their first output signals outl. This is indicated in FIG. 1 by an oscillator OSZ shown in broken lines.
Der Phasendetektor PD kann in vorteilhafter Weise mit einem dem Fachmann geläufigen Schieberegister gebildet sein. Dabei wird in bevorzugter Weise das zweite Ausgangssignal out2 des ersten Oszillators OSZl dem Dateneingang des Schieberegisters und das zweite Ausgangssignal out2 des ersten spannungsge¬ steuerten Oszillators VCOI dem Takteingang des Schieberegi- sters zugeführt. Prinzipiell ist es jedoch auch möglich, das zweite Ausgangssignal out2 des ersten spannungsgesteuerten Oszillators VCOI an den Dateneingang und das zweite Ausgangs- signal out2 des ersten Oszillators OSZl an den Takteingang des als Phasendetektor PD fungierenden Schieberegisters anzu¬ legen.The phase detector PD can advantageously be formed with a shift register familiar to the person skilled in the art. In this case, the second output signal out2 of the first oscillator OSZ1 is preferably fed to the data input of the shift register and the second output signal out2 of the first voltage-controlled oscillator VCOI is fed to the clock input of the shift register. In principle, however, it is also possible to send the second output signal out2 of the first voltage-controlled oscillator VCOI to the data input and the second output signal out2 of the first oscillator OSZ1 to the clock input of the shift register functioning as phase detector PD.
Das als Phasendetektor PD wirkende Schieberegister kann in vorteilhafter Weiterbildung der Erfindung rückgekoppelt aus¬ gebildet sein. Hierbei wird das Ausgangssignal des Schiebere¬ gisters mit dem Dateneingangssignal logisch verknüpft und erst dann dem Eingang des Schieberegisters zugeführt. Es ist außerdem möglich, Zwischenabgriffe des Schieberegisters mit¬ einander logisch zu verknüpfen und auf den Eingang zurückzu¬ führen.In an advantageous development of the invention, the shift register acting as a phase detector PD can be designed to be feedback. Here, the output signal of the shift register is logically combined with the data input signal and only then fed to the input of the shift register. It is also possible to logically link intermediate taps of the shift register with one another and to return them to the input.
Figur 2 zeigt den prinzipiellen Aufbau eines digitalen span- nungsgesteuerten Oszillators. Der Ausgang eines Inverters INV ist über einen Kondensator C mit Masseanschluß und außerdem mit dem Eingang eines als Schmitt-Trigger ausgebildeten Kom- parators ST verbunden. Der Ausgang out2 des Komparators ST liefert eine etwa rechteckige Signalform und wird auf den Eingang des Inverters INV zurückgeführt. Wenn beispielsweise der Zustand am Ausgang des Inverters INV einer logischen "1" entspricht, wird der Kondensator C aufgeladen. Wenn die Span¬ nung am Kondensator C die Schwelle des Komparators ST über¬ schreitet, schaltet dieser: an seinem Ausgang out2, der auch den Oszillatorausgang bildet, erscheint ebenfalls eine logi¬ sche "1". Diese wird auf den Eingang des Inverters INV zu¬ rückgeführt, so daß sich der Zustand an dessen Ausgang zu ei¬ ner logischen "0" ändert. Dadurch entlädt sich der Kondensa¬ tor C wieder, so daß der Komparator ST nach einer gewissen Zeit wieder umschaltet. Hierdurch kommt eine periodischeFigure 2 shows the basic structure of a digital voltage controlled oscillator. The output of an inverter INV is connected via a capacitor C to ground and also to the input of a comparator ST designed as a Schmitt trigger. The output out2 of the comparator ST provides an approximately rectangular signal shape and is fed back to the input of the inverter INV. For example, if the state at the output of the inverter INV corresponds to a logic "1", the capacitor C is charged. If the voltage across capacitor C exceeds the threshold of comparator ST, it switches: at its output out2, which also forms the oscillator output, a logical "1" also appears. This is fed back to the input of the inverter INV, so that the state at its output changes to a logic "0". As a result, the capacitor C discharges again, so that the comparator ST switches over again after a certain time. This gives a periodic
Schwingung zustande, deren Frequenz im wesentlichen durch die Kapazität des Kondensators C sowie Widerstände in den Lastpfaden des Inverters INV bestimmt ist. Diese Widerstände können steuerbar ausgebildet sein, beispielsweise wie in Fi- gur 2 dargestellt durch p- und n-MOS-Transistoren, die je¬ weils zwischen den positiven Versorgungsspannungsanschluß und dem p-MOS-Transistor des eigentlichen Inverters bzw. zwischen dem n-MOS-Transistors des Inverters und dem negativen Versor- gungsspannungsanschluß geschaltet sind. Diesem steuerbaren Inverter INV müssen zwei komplementäre Steuersignale inl, in2 zugeführt werden.Vibration occurs, the frequency of which is essentially determined by the capacitance of the capacitor C and resistances in the load paths of the inverter INV. These resistors can be designed to be controllable, for example, as shown in FIG. 2, by p- and n-MOS transistors, which in each case between the positive supply voltage connection and the p-MOS transistor of the actual inverter or between the n-MOS transistor of the inverter and the negative supply voltage connection. Two complementary control signals in1, in2 must be supplied to this controllable inverter INV.
Die Grundfrequenz des spannungsgesteuerten Oszillators wird durch die Größe der Kapazität des Kondensators C festgelegt. Eine Variation der Frequenz erfolgt mittels der Steuersignale inl, in2 durch Variation der Widerstände der Laststrecken des Inverters INV.The basic frequency of the voltage-controlled oscillator is determined by the size of the capacitance of the capacitor C. The frequency is varied by means of the control signals in1, in2 by varying the resistances of the load paths of the inverter INV.
Es ist außerdem ein weiterer Ausgang vorhanden, der ein er¬ stes Ausgangssignal outl mit etwa sägezahnförmigem Verlauf liefert und mit dem Kondensator C verbunden ist.There is also a further output which supplies a first output signal outl with an approximately sawtooth shape and is connected to the capacitor C.
Durch die erfindungsgemäße Schaltungsanordnung lassen sich echte zufällige Bitfolgen erzeugen, die als Zufallszahlen in kryptografischen Datenverarbeitungsvorgängen verwendet werden können. The circuit arrangement according to the invention can be used to generate real random bit sequences which can be used as random numbers in cryptographic data processing operations.

Claims

Patentansprüche claims
1. Schaltungsanordnung zum Erzeugen zufälliger Bitfolgen, die mit einem ersten Oszillator (OSZl) und einem zweiten Oszilla- tor (VCOI) , deren Ausgänge mit den Eingängen eines die zufäl¬ lige Bitfolge bereitstellenden Phasendetektors (PD)- verbunden sind, gebildet ist, wobei der zweite Oszillator (VCOI) fre¬ quenzmoduliert ist.1. A circuit arrangement for generating random bit sequences, which is formed with a first oscillator (OSZl) and a second oscillator (VCOI), the outputs of which are connected to the inputs of a phase detector (PD) providing the random bit sequence the second oscillator (VCOI) is frequency modulated.
2. Schaltungsanordnung nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß der zweite Oszillator (VCOI) als spannungsgesteuerter Os¬ zillator ausgebildet ist und von einem dritten Oszillator (VC02) angesteuert ist.2. Circuit arrangement according to claim 1, so that the second oscillator (VCOI) is designed as a voltage-controlled oscillator and is controlled by a third oscillator (VC02).
3. Schaltungsanordnung nach Anspruch 2, d a d u r c h g e k e n n z e i c h n e t , daß der dritte Oszillator (VC02) als spannungsgesteuerter Os¬ zillator ausgebildet ist und von einem vierten Oszillator (OSZ2) angesteuert ist.3. Circuit arrangement according to claim 2, so that the third oscillator (VC02) is designed as a voltage-controlled oscillator and is controlled by a fourth oscillator (OSZ2).
4. Schaltungsanordnung nach einem der vorhergehenden Ansprü¬ che, d a d u r c h g e k e n n z e i c h n e t , daß der Phasendetektor (PD) mit einem Schieberegister gebil¬ det ist .4. Circuit arrangement according to one of the preceding claims, that the phase detector (PD) is formed with a shift register.
5. Schaltungsanordnung nach Anspruch 4, d a d u r c h g e k e n n z e i c h n e t , daß das Schieberegister rückgekoppelt ist.5. Circuit arrangement according to claim 4, d a d u r c h g e k e n n z e i c h n e t that the shift register is fed back.
6. Schaltungsanordnung nach einem der Ansprüche 2 - 5, d a d u r c h g e k e n n z e i c h n e t , daß der erste Oszillator (OSZl) und der zweite Oszillator (VCOI) etwa mit derselben Frequenz, der dritte Oszillator (VC02) und vierte Oszillator (OSZ2) mit anderen Frequenzen schwingen. 6. Circuit arrangement according to one of claims 2-5, characterized in that the first oscillator (OSZl) and the second oscillator (VCOI) oscillate at approximately the same frequency, the third oscillator (VC02) and fourth oscillator (OSZ2) at different frequencies.
7. Schaltungsanordnung nach einem der vorangehenden Ansprü¬ che, d a d u r c h g e k e n n z e i c h n e t , daß auch der erste Oszillator (OSZl) als spannungsgesteuerter Oszillator ausgebildet und frequenzmoduliert ist. 7. Circuit arrangement according to one of the preceding claims, d a d u r c h g e k e n e z e i c h n e t that the first oscillator (OSZl) is designed as a voltage-controlled oscillator and frequency modulated.
PCT/DE1997/000831 1996-05-06 1997-04-25 Circuit arrangement for generating random bit sequences WO1997042706A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP97924868A EP0897613A1 (en) 1996-05-06 1997-04-25 Circuit arrangement for generating random bit sequences
JP9539414A JPH11509707A (en) 1996-05-06 1997-04-25 Circuit device for generating a random bit string
BR9708977A BR9708977A (en) 1996-05-06 1997-04-25 Circuit to produce random bit strings

Applications Claiming Priority (2)

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DE19618098.8 1996-05-06
DE19618098A DE19618098C1 (en) 1996-05-06 1996-05-06 Random bit sequence generation circuit

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KR (1) KR20000010804A (en)
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2325361B (en) * 1997-05-16 2001-06-27 Motorola Inc Random number generator arrangement and method of generation thereof
DE19744586A1 (en) * 1997-10-09 1999-04-15 Guenther Dipl Phys Magens Coding digital data for distant transmission
US6522210B1 (en) * 2000-02-16 2003-02-18 Honeywell International Inc. Random pulse generator
US20070255777A1 (en) * 2004-11-18 2007-11-01 Niigata Tlo Corporation Method for Generating Random Number and Random Number Generator
WO2019030667A1 (en) 2017-08-08 2019-02-14 Politechnika Warszawska Random number generator
PL237196B1 (en) * 2017-08-08 2021-03-22 Politechnika Warszawska Random generator

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3713142A (en) * 1972-01-17 1973-01-23 Signatron Alarm system
DE3020481A1 (en) * 1980-05-29 1982-02-18 Siemens AG, 1000 Berlin und 8000 München Adjustable pseudo-random generator with shift register - has one or more prom(s), storing pseudo-random binary data as words of specified bit length
FR2621191A3 (en) * 1987-09-29 1989-03-31 Cit Alcatel Generator of jittery signals
DE4002569A1 (en) * 1990-01-30 1991-08-01 Sensys Ag Electrically armed mine with sequential signal state generator - effects combination of slow and fast pulse trains into random binary sequence of active and inactive states
US5153532A (en) * 1989-05-24 1992-10-06 Honeywell Inc. Noise generator using combined outputs of two pseudo-random sequence generators

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4644299A (en) * 1986-02-14 1987-02-17 Hughes Aircraft Company Multimode noise generator using digital FM

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3713142A (en) * 1972-01-17 1973-01-23 Signatron Alarm system
DE3020481A1 (en) * 1980-05-29 1982-02-18 Siemens AG, 1000 Berlin und 8000 München Adjustable pseudo-random generator with shift register - has one or more prom(s), storing pseudo-random binary data as words of specified bit length
FR2621191A3 (en) * 1987-09-29 1989-03-31 Cit Alcatel Generator of jittery signals
US5153532A (en) * 1989-05-24 1992-10-06 Honeywell Inc. Noise generator using combined outputs of two pseudo-random sequence generators
DE4002569A1 (en) * 1990-01-30 1991-08-01 Sensys Ag Electrically armed mine with sequential signal state generator - effects combination of slow and fast pulse trains into random binary sequence of active and inactive states

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BR9708977A (en) 1999-08-03
EP0897613A1 (en) 1999-02-24
CN1217834A (en) 1999-05-26
JPH11509707A (en) 1999-08-24
KR20000010804A (en) 2000-02-25
DE19618098C1 (en) 1997-06-05

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