WO1998004004A1 - High density trench dmos transistor with trench bottom implant - Google Patents

High density trench dmos transistor with trench bottom implant Download PDF

Info

Publication number
WO1998004004A1
WO1998004004A1 PCT/US1997/012046 US9712046W WO9804004A1 WO 1998004004 A1 WO1998004004 A1 WO 1998004004A1 US 9712046 W US9712046 W US 9712046W WO 9804004 A1 WO9804004 A1 WO 9804004A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
region
transistor structure
conductivity type
drift region
Prior art date
Application number
PCT/US1997/012046
Other languages
French (fr)
Inventor
Fwu-Iuan Hshieh
Brian H. Floyd
Mike Chang
Danny Nim
Daniel Ng
Original Assignee
Siliconix Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Incorporated filed Critical Siliconix Incorporated
Priority to AU37241/97A priority Critical patent/AU3724197A/en
Priority to DE69739206T priority patent/DE69739206D1/en
Priority to JP10506999A priority patent/JP2000515684A/en
Priority to EP97934104A priority patent/EP0948818B1/en
Publication of WO1998004004A1 publication Critical patent/WO1998004004A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Definitions

  • This invention relates to transistors and more specifically to a high density trenched DMOS transistor.
  • DMOS diffused metal oxide semiconductor
  • Some DMOS transistors are trenched transistors; a conductive gate electrode, typically polycrystalline silicon (polysilicon) , is located in a trench in the transistor substrate, and the sidewalls and bottom of the trench are insulated with silicon dioxide.
  • the trenched structure increases transistor density by reducing the chip surface area consumed by the polysilicon gate of each transistor.
  • transistors are used in low to medium voltage applications, and each transistor includes a large number (thousands) of cells. Each cell is defined by a source region diffused into the substrate and by the gate electrode trenches.
  • the provision of the trenches advantageously increases cell density and also reduces the undesirable parasitic JFET (junction field effect transistor) resistance which typically is present between adjacent cells.
  • the parasitic JFET resistance is one component of the total on-state resistance, R DSON» which is characteristic of such transistors in their conductive (on) state; it is desirable to minimize the on- resistance.
  • trenches do not completely eliminate parasitic JFET resistance.
  • a new parasitic JFET phenomenon gradually appears between the adjacent deep body P+ regions which extend alongside the trench and are typically used to protect the trench regions and ensure reliability.
  • this new JFET resistance becomes a significant component of on- resistance as cell density increases.
  • avalanche breakdown occurs in the P+ doped regions away from the trench bottom.
  • the deep body P+ region extends deeper than does the bottom of the trench. Rather than the destructive breakdown occurring at the trench bottom, therefore instead the avalanche breakdown occurs from the lowest portion of this deep body P+ region into the underlying relatively nearby drain region.
  • the trenched DMOS transistor structure is superior to a planar DMOS transistor in terms of drain-source specific on-resistance, which is resistance times the cross-sectional area of the substrate carrying the current.
  • the JFET resistance inherent in planar DMOS transistors, is significantly reduced and cell density is enhanced by reducing the length of the gate electrode.
  • An example of a planar DMOS transistor is disclosed in Lidow et al. U.S. Patent No. 4,642,666 issued February 10, 1987 which discloses as shown in present Figure 1 (similar to Figure 2 of Lidow et al.) a high power MOSFET in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip, controlled by the same gate.
  • the epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain is of relatively high conductivity (is highly doped) , thereby substantially reducing the on-resistance of the device without affecting the device breakdown voltage.
  • the Lidow et al. MOSFET is formed in a chip of monocrystalline silicon 20.
  • Two source electrodes 22 and 23 are separated by a metallized gate electrode 24 which is fixed to but spaced apart from the semiconductor device surface by a silicon dioxide layer 25.
  • Each of source electrodes 22 and 23 supply current to a drain electrode 26 which is fixed to the bottom of the wafer.
  • An N- doped epitaxial layer is deposited on N+ doped substrate 20.
  • P+ doped regions 30 and 31 each include a curved lower portion which serves as a deep body region.
  • N+ regions 32 and 33 are formed at the source electrodes 22 and 23 respectively and define, with the P doped regions 34 and 35, channel regions 36 and 37 which are disposed beneath the gate oxide 25 and can be inverted from P-type to N-type by the appropriate application of a bias voltage to the gate 24 in order to permit conduction from the source electrodes 22 and 23 through the inversion layers into the central region disposed beneath the gate 24 and then to the drain electrode 26.
  • a bias voltage to the gate 24 in order to permit conduction from the source electrodes 22 and 23 through the inversion layers into the central region disposed beneath the gate 24 and then to the drain electrode 26.
  • the N+ region 40 has a depth of about 4 ⁇ m.
  • Region 40 is relatively highly doped compared to the N- doped region immediately beneath it. By making region 40 of relatively highly conductive N+ material by a diffusion or other operation, the device characteristics are significantly improved and the forward on-resistance of the device is reduced by a factor greater than two. Provision of the high conductivity region 40 does not interfere with the reverse voltage characteristics of the device. Accordingly the forward on-resistance of the ultimate high power switching device is significantly reduced.
  • Lidow et al. device is a planar (non- trenched) transistor structure and has the accompanying drawbacks of relatively low cell density and relatively high inherent JFET resistance.
  • a trenched DMOS transistor includes a trench bottom implant region which is of the same doping type, but more heavily doped, than is the surrounding drift region.
  • the doping concentration in the area at the trench bottom is increased.
  • the new parasitic JFET observed by the present inventors at the trench bottom is substantially eliminated.
  • trench corner electrical breakdown at high voltage is avoided, and avalanche still occurs in the P+ regions.
  • the trench bottom implant region is fabricated in one embodiment by etching the trench in the substrate, lining the trench with oxide, and then performing a blanket implant of a dopant at a vertical angle, to form a doped region extending from the bottom of the trench into the surrounding drift region. This is accomplished prior to formation of the gate electrode itself in the trench, and also prior to forming the source, body and deep body regions.
  • U.S. Patent No. 4,983,160 issued January 9, 1990, to Blanchard depicts (see Figure 3) a trenched DMOS transistor with an N+ doped region at the lower sides and bottom of the trench. The purpose of this N+ region is to increase breakdown voltage. Hence the doping level of this N+ region is fairly high.
  • Figure 1 shows a prior art planar MOSFET.
  • Figure 2 shows a transistor in accordance with the present invention.
  • Figures 3A to 3D shows steps for forming a transistor in accordance with the present invention.
  • Figure 2 shows a cross-section of a transistor in accordance with the present invention.
  • This cros ⁇ - section is drawn conventionally and shows only portions of several cells of a typical transistor, which may include thousands of such cells. However, a single cell transistor is also possible.
  • the present disclosure is directed to a transistor having an N type (N doped) substrate, a P type (P doped) body region and an N type source region, it is to be understood that complementary devices are also possible wherein each conductivity type is reversed.
  • the cross-sections shown here are not drawn to scale but are intended to be illustrative. While the various transistor doped regions shown here are conventionally delineated by lines, this is also illustrative rather than representative. In the figures, identical reference numbers used in various figures denote similar structures. Also, the various parameters disclosed herein for thickness, depths, widths, doping concentrations, dosages, and implantation energies are illustrative rather than limiting. Also, various materials may be used for the positive and negative type dopants. While the substances conventionally used for these dopant types may be used, this is not limiting.
  • top side geometries for the various transistors herein are not depicted since these are conventional in terms of the cell arrangement and terminations.
  • the terminations are generally not shown here but are e.g. those conventionally used with DMOSFETS .
  • Figure 2 therefore shows in cross-section one cell (and a portion of adjoining cells) of the present transistor which includes drain region 50 N+ doped to a resistivity of e.g. 1 to 5 milliohm «cm and having a conventional thickness.
  • a metallized drain electrode 80 is formed on the bottom surface of this drain region 50 as an electrical contact thereto.
  • Formed on the drain region 50 (substrate) is an N- doped (e.g. epitaxial) layer (this need not be an epitaxial layer but is conventionally so formed) which typically has a resistivity of 0.3 to 1.0 ohm*cm.
  • the N- doped portion 54 of the epitaxial layer is conventionally referred to as a drift region.
  • the epitaxial layer has a total thickness (extending to the principal surface of the transistor structure) of e.g. 8 to 12 ⁇ m.
  • a P doped body region 56 is formed in the upper portion of the epitaxial layer.
  • a typical dopant level of the body region 56 at the principal surface is 5 x 10 15 /cm 3 .
  • a lower deep body P+ doped portion 57 having a total depth from the principal surface of the semiconductor body of about 2.5 ⁇ m and extending below the bottom of the trenches as shown.
  • a typical doping level of the deep body P+ portion 57 is 2 x 10 1 /cm 3 .
  • Penetrating from the principal surface of the semiconductor body into the drift region 54 is a set of trenches which defines the transistor cells. (Only one such trench 62 is shown here, in cross-section.)
  • Trench 62 is lined with gate oxide layer 66 which is typically 0.05 to 0.07 ⁇ m thick, and each trench 62 is then filled with a conductive doped polysilicon gate electrode 64.
  • a typical width of trench 62 is 0.8 to l.O ⁇ .
  • a typical cell pitch is 6.0 ⁇ .
  • a typical depth of trench 62 is 1 to 2 ⁇ m (less than that of deep body portion 57) . Typically therefore the P+ deep body portion 57 extends 0.5 ⁇ m below the bottom (floor) of the trench 62.
  • Formed in the upper portion of the epitaxial layer are N+ doped source regions 58, having a typical depth of 0.5 ⁇ .
  • a typical doping level of the N+ source regions 58 is 6 x lO-'/cm ** at the principal surface.
  • Penetrating through the middle of each source region 58 is the trench 62 in which is formed the conductive electrode gate 64.
  • Insulating the upper portion of each conductive gate electrode 64 is a BPSG (boro- phosphosilicate glass) insulating layer 74 formed over gate electrode 64.
  • Contacting the source regions 58 and body regions 56 is a source-body metallization layer 76.
  • each transistor active portion is typically surrounded by a termination, typically including doped regions and sometimes an additional filled-in trench.
  • Conventional terminations are suitable in accordance with the present invention and hence the termination is not illustrated or described further herein.
  • a feature of the structure of Figure 2 in accordance with the present invention is the trench bottom implant region 70, which is N doped to a concentration in a range of e.g. 1 x 10 16 to 8 x 10 16 /cm 3 .
  • the trench bottom implant region 70 is of higher doping concentration than is the surrounding drift region 54 but of much lower doping concentration than drain region 50.
  • Trench bottom implant region 70 advantageously eliminates the above-described parasitic JFET, which in prior art MOSFETS appears between deep body P+ regions at the trench bottoms.
  • Region 70 as shown extends as deep into drift region 54 as does the lowest part of deep body region 57, in this embodiment.
  • the parasitic JFET resistance is thereby significantly reduced. Breakdown at the corners of the trench due to the local electric field concentration is also prevented by optimizing the implant dose.
  • the typical thickness (height) of the trench bottom implant region 70 is 0.5 ⁇ .
  • the width is typically that of the trench, i.e. it extends from one side of the trench to the other including the trench corners, and extends a slight distance laterally from the trench corners, as a result of its fabrication by diffusion.
  • a typical distance from the bottom portion of trench bottom implant region 70 to the substrate 50 is l.O ⁇ , but this distance is not limiting; trench bottom implant region 70 can extend to substrate 50.
  • N+ substrate 50 conventionally doped to have a resistivity in the range described above.
  • An epitaxial layer 54 is then grown thereon having a higher resistivity (as described above) and a thickness of e.g. 6 to 12 ⁇ m.
  • the principal surface of the semiconductor body including the epitaxial layer 54 then has a conventional active mask layer (not shown) formed thereon and patterned.
  • This active mask layer may be oxide or other suitable material, and defines the active portion of the transistor and masks off the termination thereof. It is to be understood that the present figures show only the active portion, with the termination not being shown as being outside the area of the drawings.
  • a P+ region mask layer (not shown) is formed and patterned, masking off all portions of the principal surface of the semiconductor body except for where the P+ deep body portions (tubs) 57 are to be formed.
  • a P+ solid source diffusion is performed using boron nitride.
  • the P-t- dopant is boron; the diffusion 57 is to a depth of about 1.5 ⁇ m.
  • a trench mask layer (not shown) is then formed and conventionally patterned. Using the trench mask layer as a pattern, the trenches are then anisotropically etched.
  • the trenches, e.g. trench 62 are then subject to a sacrificial oxide step to smooth their sidewalls and bottoms.
  • This sacrificial oxide step involves growing a layer of oxide and then removing it by etching.
  • the gate oxide layer 66 is then grown conventionally, as shown in Figure 3B, to a thickness of e.g. 0.05 to 0.07 microns.
  • a blanket N ion implant is carried out over the entire principal surface and into the trench 62. This is a vertical implant at an angle directly perpendicular to the plane defined by the principal surface of the semiconductor body.
  • the implant energy is e.g. in the range of 30 to 100 KeV and a dose of 10 n to l ⁇ 13 /cm 2 .
  • This trench bottom implant step results in the formation of an N doped region 70 the bottom of trench 62, and also the formation of corresponding N doped regions 80 extending from the principal surface.
  • a layer of polysilicon 64 is formed on the principal surface of the semiconductor body and filling the trench 62.
  • This polysilicon layer is doped with an N type dopant to achieve maximum conductivity.
  • a gate mask layer (polymask) is formed over the entire surface of the polysilicon layer and patterned. (This step is not depicted.) This gate mask layer is then used to etch away the polysilicon layer 64, except in the trench 62, and also leaving gate contact fingers (not shown) on the principal surface connecting the gate electrodes in the various trenches.
  • a blanket P-type implant forms the P doped body regions 56 to provide a channel alongside the trench sidewalls.
  • This step uses a dosage of e.g. 10 13 to 10 14 per/cm 2 and an energy of 50 to 60 KeV, typically using boron as the dopant for an N channel device.
  • N+ source region mask layer is formed and patterned to define the N+ source regions 58.
  • the N+ source region implant is then performed at an energy level of e.g. 60 to 100 KeV at a dosage of 5 x 10 15 to 8 x 10 15 /cm 2 , the dopant being arsenic.
  • the N+ source mask is then stripped.
  • a layer of borophosphosilicate glass is conventionally formed (not shown) to a thickness of 1 to 1.5 ⁇ .
  • a BPSG mask layer is then formed and patterned over the BPSG layer, and then the BPSG mask layer is used to etch the BPSG, defining BPSG region 74 of Figure 2 insulating the top side of conductive gate electrode 64.
  • conventional steps are used to complete the device, i.e. stripping the BPSG mask layer, depositing the source-body metal layer, and masking the metal layer to define the source-body contact 76 of Figure 2.
  • a passivation layer is formed thereover and a pad mask is formed thereon and patterned to define the pad contacts through the passivation layer.
  • the formation of the metal layer 76 has a corresponding step to form the contact 80 (see Figure 2) to the drain layer 50 on the backside of the substrate.

Abstract

A trenched DMOS transistor overcomes the problem of a parasitic JFET at the trench bottom (caused by deep body regions (57) extending deeper than the trench) by providing a doped trench (62) and extending into the surrounding drift region (54). This trench bottom implant region (70) has the same doping type, but is more highly doped, than the surrounding drift region (54). The trench bottom implant region (70) significantly reduces the parasitic JFET resistance by optimizing the trench bottom implant dose, without creating reliability problems.

Description

HIGH DENSITY TRENCH DMOS TRANSISTOR WITH TRENCH BOTTOM IMPLANT
BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to transistors and more specifically to a high density trenched DMOS transistor.
Description of the Prior Art
DMOS (diffused metal oxide semiconductor) transistors are well known. Typically these transistors are used in integrated circuits or for power transistors. Some DMOS transistors are trenched transistors; a conductive gate electrode, typically polycrystalline silicon (polysilicon) , is located in a trench in the transistor substrate, and the sidewalls and bottom of the trench are insulated with silicon dioxide. The trenched structure increases transistor density by reducing the chip surface area consumed by the polysilicon gate of each transistor. Typically such transistors are used in low to medium voltage applications, and each transistor includes a large number (thousands) of cells. Each cell is defined by a source region diffused into the substrate and by the gate electrode trenches.
The provision of the trenches advantageously increases cell density and also reduces the undesirable parasitic JFET (junction field effect transistor) resistance which typically is present between adjacent cells. The parasitic JFET resistance is one component of the total on-state resistance, RDSON» which is characteristic of such transistors in their conductive (on) state; it is desirable to minimize the on- resistance. However, trenches do not completely eliminate parasitic JFET resistance. When cell density is high in a trenched DMOS transistor, a new parasitic JFET phenomenon gradually appears between the adjacent deep body P+ regions which extend alongside the trench and are typically used to protect the trench regions and ensure reliability. Unfortunately, this new JFET resistance becomes a significant component of on- resistance as cell density increases. By design, avalanche breakdown occurs in the P+ doped regions away from the trench bottom. In a typical DMOS transistor having a trenched gate electrode, in order to avoid destructive breakdown occurring at the bottom of the trench into the underlying drain region, the deep body P+ region extends deeper than does the bottom of the trench. Rather than the destructive breakdown occurring at the trench bottom, therefore instead the avalanche breakdown occurs from the lowest portion of this deep body P+ region into the underlying relatively nearby drain region.
It is well known that the trenched DMOS transistor structure is superior to a planar DMOS transistor in terms of drain-source specific on-resistance, which is resistance times the cross-sectional area of the substrate carrying the current. The JFET resistance, inherent in planar DMOS transistors, is significantly reduced and cell density is enhanced by reducing the length of the gate electrode. An example of a planar DMOS transistor is disclosed in Lidow et al. U.S. Patent No. 4,642,666 issued February 10, 1987 which discloses as shown in present Figure 1 (similar to Figure 2 of Lidow et al.) a high power MOSFET in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip, controlled by the same gate. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain is of relatively high conductivity (is highly doped) , thereby substantially reducing the on-resistance of the device without affecting the device breakdown voltage.
Thus as shown in present Figure 1 , the Lidow et al. MOSFET is formed in a chip of monocrystalline silicon 20. Two source electrodes 22 and 23 are separated by a metallized gate electrode 24 which is fixed to but spaced apart from the semiconductor device surface by a silicon dioxide layer 25. Each of source electrodes 22 and 23 supply current to a drain electrode 26 which is fixed to the bottom of the wafer. An N- doped epitaxial layer is deposited on N+ doped substrate 20. P+ doped regions 30 and 31 each include a curved lower portion which serves as a deep body region. Two N+ regions 32 and 33 are formed at the source electrodes 22 and 23 respectively and define, with the P doped regions 34 and 35, channel regions 36 and 37 which are disposed beneath the gate oxide 25 and can be inverted from P-type to N-type by the appropriate application of a bias voltage to the gate 24 in order to permit conduction from the source electrodes 22 and 23 through the inversion layers into the central region disposed beneath the gate 24 and then to the drain electrode 26. (Reference numbers used herein referring to Figure 1 differ somewhat from those in the Lidow et al. disclosure.) In the central region beneath the gate 24 is located a highly conductive N+ doped region 40 disposed immediately beneath the gate oxide 25. The N+ region 40 has a depth of about 4μm. Region 40 is relatively highly doped compared to the N- doped region immediately beneath it. By making region 40 of relatively highly conductive N+ material by a diffusion or other operation, the device characteristics are significantly improved and the forward on-resistance of the device is reduced by a factor greater than two. Provision of the high conductivity region 40 does not interfere with the reverse voltage characteristics of the device. Accordingly the forward on-resistance of the ultimate high power switching device is significantly reduced.
However the Lidow et al. device is a planar (non- trenched) transistor structure and has the accompanying drawbacks of relatively low cell density and relatively high inherent JFET resistance.
SUMMARY In accordance with the present invention, a trenched DMOS transistor includes a trench bottom implant region which is of the same doping type, but more heavily doped, than is the surrounding drift region. Thereby, the doping concentration in the area at the trench bottom is increased. This results in significant reduction of the JFET resistance otherwise characteristic of trenched DMOS transistors, by optimizing the concentration of the trench bottom implant region, without creating any reliability problems. Thus, in effect the new parasitic JFET observed by the present inventors at the trench bottom (where the deep body regions extend deeper than the trench) is substantially eliminated. Also, in accordance with the invention, trench corner electrical breakdown at high voltage is avoided, and avalanche still occurs in the P+ regions. The trench bottom implant region is fabricated in one embodiment by etching the trench in the substrate, lining the trench with oxide, and then performing a blanket implant of a dopant at a vertical angle, to form a doped region extending from the bottom of the trench into the surrounding drift region. This is accomplished prior to formation of the gate electrode itself in the trench, and also prior to forming the source, body and deep body regions. U.S. Patent No. 4,983,160 issued January 9, 1990, to Blanchard depicts (see Figure 3) a trenched DMOS transistor with an N+ doped region at the lower sides and bottom of the trench. The purpose of this N+ region is to increase breakdown voltage. Hence the doping level of this N+ region is fairly high.
Moreover, in this transistor the P+ body regions are much shallower than is the trench, hence there being no parasitic JFET problem.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows a prior art planar MOSFET. Figure 2 shows a transistor in accordance with the present invention.
Figures 3A to 3D shows steps for forming a transistor in accordance with the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 2 shows a cross-section of a transistor in accordance with the present invention. This crosε- section is drawn conventionally and shows only portions of several cells of a typical transistor, which may include thousands of such cells. However, a single cell transistor is also possible. Also, while the present disclosure is directed to a transistor having an N type (N doped) substrate, a P type (P doped) body region and an N type source region, it is to be understood that complementary devices are also possible wherein each conductivity type is reversed.
Also, the cross-sections shown here are not drawn to scale but are intended to be illustrative. While the various transistor doped regions shown here are conventionally delineated by lines, this is also illustrative rather than representative. In the figures, identical reference numbers used in various figures denote similar structures. Also, the various parameters disclosed herein for thickness, depths, widths, doping concentrations, dosages, and implantation energies are illustrative rather than limiting. Also, various materials may be used for the positive and negative type dopants. While the substances conventionally used for these dopant types may be used, this is not limiting.
The top side geometries for the various transistors herein are not depicted since these are conventional in terms of the cell arrangement and terminations. The terminations are generally not shown here but are e.g. those conventionally used with DMOSFETS .
Figure 2 therefore shows in cross-section one cell (and a portion of adjoining cells) of the present transistor which includes drain region 50 N+ doped to a resistivity of e.g. 1 to 5 milliohm«cm and having a conventional thickness. Conventionally a metallized drain electrode 80 is formed on the bottom surface of this drain region 50 as an electrical contact thereto. Formed on the drain region 50 (substrate) is an N- doped (e.g. epitaxial) layer (this need not be an epitaxial layer but is conventionally so formed) which typically has a resistivity of 0.3 to 1.0 ohm*cm. The N- doped portion 54 of the epitaxial layer is conventionally referred to as a drift region. The epitaxial layer has a total thickness (extending to the principal surface of the transistor structure) of e.g. 8 to 12μm.
A P doped body region 56 is formed in the upper portion of the epitaxial layer. A typical dopant level of the body region 56 at the principal surface is 5 x 1015/cm3. Included as part of body region 56 is a lower deep body P+ doped portion 57 having a total depth from the principal surface of the semiconductor body of about 2.5μm and extending below the bottom of the trenches as shown. A typical doping level of the deep body P+ portion 57 is 2 x 101/cm3.
Penetrating from the principal surface of the semiconductor body into the drift region 54 is a set of trenches which defines the transistor cells. (Only one such trench 62 is shown here, in cross-section.)
Trench 62, as are the other trenches, is lined with gate oxide layer 66 which is typically 0.05 to 0.07μm thick, and each trench 62 is then filled with a conductive doped polysilicon gate electrode 64. A typical width of trench 62 is 0.8 to l.Oμ. A typical cell pitch is 6.0μ. A typical depth of trench 62 is 1 to 2μm (less than that of deep body portion 57) . Typically therefore the P+ deep body portion 57 extends 0.5μm below the bottom (floor) of the trench 62. Formed in the upper portion of the epitaxial layer are N+ doped source regions 58, having a typical depth of 0.5μ. A typical doping level of the N+ source regions 58 is 6 x lO-'/cm** at the principal surface. Penetrating through the middle of each source region 58 is the trench 62 in which is formed the conductive electrode gate 64. Insulating the upper portion of each conductive gate electrode 64 is a BPSG (boro- phosphosilicate glass) insulating layer 74 formed over gate electrode 64. Contacting the source regions 58 and body regions 56 is a source-body metallization layer 76.
The depiction herein is of the active portion only of the transistor. Each transistor active portion is typically surrounded by a termination, typically including doped regions and sometimes an additional filled-in trench. Conventional terminations are suitable in accordance with the present invention and hence the termination is not illustrated or described further herein.
A feature of the structure of Figure 2 in accordance with the present invention is the trench bottom implant region 70, which is N doped to a concentration in a range of e.g. 1 x 1016 to 8 x 1016/cm3. Intentionally, the trench bottom implant region 70 is of higher doping concentration than is the surrounding drift region 54 but of much lower doping concentration than drain region 50. Trench bottom implant region 70 advantageously eliminates the above-described parasitic JFET, which in prior art MOSFETS appears between deep body P+ regions at the trench bottoms. Region 70 as shown extends as deep into drift region 54 as does the lowest part of deep body region 57, in this embodiment. The parasitic JFET resistance is thereby significantly reduced. Breakdown at the corners of the trench due to the local electric field concentration is also prevented by optimizing the implant dose.
Also, unlike the prior art planar transistor of Lidow et al., there is no punchthrough problem since there is no additional doping added in the channel region between the source and body regions. In the planar transistor structure of Lidow et al., there is an enhanced chance of lateral punchthrough from source regions 32 and 33 through the respective body regions
34 and 35. Such punchthrough would occur at the principal surface of the P body regions 34 and 35. Thus in the structure of Figure 2 , the blocking characteristics are not degraded while advantageously the on-resistance is reduced.
The typical thickness (height) of the trench bottom implant region 70 is 0.5μ. The width is typically that of the trench, i.e. it extends from one side of the trench to the other including the trench corners, and extends a slight distance laterally from the trench corners, as a result of its fabrication by diffusion. A typical distance from the bottom portion of trench bottom implant region 70 to the substrate 50 is l.Oμ , but this distance is not limiting; trench bottom implant region 70 can extend to substrate 50. An exemplary process flow for fabricating the transistor of Figure 2 is described hereinafter. It is to be understood that this process flow is not the only way to fabricate the structure of Figure 2, but is illustrative. The various parameters given herein may be varied and still be in accordance with the present invention.
One begins as shown in Figure 3A with an N+ substrate 50 conventionally doped to have a resistivity in the range described above. An epitaxial layer 54 is then grown thereon having a higher resistivity (as described above) and a thickness of e.g. 6 to 12μm.
The principal surface of the semiconductor body including the epitaxial layer 54 then has a conventional active mask layer (not shown) formed thereon and patterned. This active mask layer may be oxide or other suitable material, and defines the active portion of the transistor and masks off the termination thereof. It is to be understood that the present figures show only the active portion, with the termination not being shown as being outside the area of the drawings.
Next (see Figure 3B) a P+ region mask layer (not shown) is formed and patterned, masking off all portions of the principal surface of the semiconductor body except for where the P+ deep body portions (tubs) 57 are to be formed. After patterning this mask layer, a P+ solid source diffusion is performed using boron nitride. Hence the P-t- dopant is boron; the diffusion 57 is to a depth of about 1.5μm. A trench mask layer (not shown) is then formed and conventionally patterned. Using the trench mask layer as a pattern, the trenches are then anisotropically etched. The trenches, e.g. trench 62, are then subject to a sacrificial oxide step to smooth their sidewalls and bottoms. This sacrificial oxide step involves growing a layer of oxide and then removing it by etching. The gate oxide layer 66 is then grown conventionally, as shown in Figure 3B, to a thickness of e.g. 0.05 to 0.07 microns. Then in a departure from the conventional process flow and as shown in Figure 3C, a blanket N ion implant is carried out over the entire principal surface and into the trench 62. This is a vertical implant at an angle directly perpendicular to the plane defined by the principal surface of the semiconductor body. The implant energy is e.g. in the range of 30 to 100 KeV and a dose of 10n to lθ13/cm2.
This trench bottom implant step results in the formation of an N doped region 70 the bottom of trench 62, and also the formation of corresponding N doped regions 80 extending from the principal surface.
Then as shown in Figure 3D, a layer of polysilicon 64 is formed on the principal surface of the semiconductor body and filling the trench 62. This polysilicon layer is doped with an N type dopant to achieve maximum conductivity. Then conventionally a gate mask layer (polymask) is formed over the entire surface of the polysilicon layer and patterned. (This step is not depicted.) This gate mask layer is then used to etch away the polysilicon layer 64, except in the trench 62, and also leaving gate contact fingers (not shown) on the principal surface connecting the gate electrodes in the various trenches.
Then a blanket P-type implant forms the P doped body regions 56 to provide a channel alongside the trench sidewalls. This step uses a dosage of e.g. 1013 to 1014 per/cm2 and an energy of 50 to 60 KeV, typically using boron as the dopant for an N channel device.
As depicted in Figure 3D, the combined effects of the P body implant 56 and the P+ tub 57 effectively eliminate the N doped regions 80 of Figure 3C.
Then an N+ source region mask layer is formed and patterned to define the N+ source regions 58. The N+ source region implant is then performed at an energy level of e.g. 60 to 100 KeV at a dosage of 5 x 1015 to 8 x 1015/cm2, the dopant being arsenic. The N+ source mask is then stripped.
Next, a layer of borophosphosilicate glass (BPSG) is conventionally formed (not shown) to a thickness of 1 to 1.5 μ . A BPSG mask layer is then formed and patterned over the BPSG layer, and then the BPSG mask layer is used to etch the BPSG, defining BPSG region 74 of Figure 2 insulating the top side of conductive gate electrode 64. Then conventional steps are used to complete the device, i.e. stripping the BPSG mask layer, depositing the source-body metal layer, and masking the metal layer to define the source-body contact 76 of Figure 2. Then a passivation layer is formed thereover and a pad mask is formed thereon and patterned to define the pad contacts through the passivation layer. The formation of the metal layer 76 has a corresponding step to form the contact 80 (see Figure 2) to the drain layer 50 on the backside of the substrate.
This disclosure is illustrative and not limiting; further variations and modifications will be apparent to one skilled in the art in light of this disclosure and are intended to fall within the scope of the appended claims.

Claims

We claim:
1. A transistor structure comprising: a substrate of a first conductivity type; a drift region overlying the substrate and of the first conductivity type and doped to a concentration less than that of the substrate; a body region of a second conductivity type opposite that of the first conductivity type overlying the drift region, and defining a principal surface of the transistor structure; a conductive gate electrode extending in a trench from the principal surface through the body region and into the drift region to a depth less than that of the body region; a source region of the first conductivity type extending into the body region from the principal surface; and a trench bottom region of the first conductivity type and of a higher doping concentration than the drift region, and extending from a bottom of the trench into the drift region.
2. The transistor structure of Claim 1, wherein the trench bottom region has a doping concentration in a range of 1 x 1016/cm3 to 8 x 1016/c*m3.
3. The transistor of Claim 1, wherein the trench bottom region has a doping concentration at least four times that of the drift region.
4. The transistor structure of Claim 1, wherein the body region includes a channel portion in contact with a side of the trench near the principal surface, and a deep body portion more heavily doped than the channel portion and spaced apart from a side of the trench and nearer the bottom of the trench than is the channel portion.
5. The transistor structure of Claim 4, wherein the trench bottom region is spaced apart from the deep body portion.
6. The transistor structure of Claim 1, wherein the trench bottom region extends at least 0.5μm into the drift region from the bottom of the trench.
7. The transistor structure of Claim 1, wherein the trench bottom region is spaced apart from the substrate by at least lμm.
8. A method of forming a transistor structure, comprising the steps of: providing a substrate of a first conductivity type ; forming a drift region on an upper portion of the substrate, the drift region being of the first conductivity type and doped to a concentration lower than that of the substrate; forming a body region of a second conductivity type opposite to the first conductivity type and extending from a principal surface of the drift region into the drift region; forming a trench extending into the drift region to a depth less than that of the body region; implanting through a bottom of the trench, and into the drift region, a trench bottom region of the first conductivity type and having a doping concentration greater than that of the drift region; filling the trench with a conductive gate electrode, after the step of implanting the trench bottom region; and forming a source region of the first conductivity type and extending into the body region from the principal surface.
9. The method of Claim 8, further comprising the steps of: after forming the trench, and before the step of implanting, forming an oxide layer lining the trench; and etching away at least a predetermined thickness of the oxide layer.
10. The method of Claim 8, wherein the step of implanting comprises implanting negatively charged ions at an energy in a range of 30 to 100 KeV, and a dose of 1012 to 1013/cm2.
11. The method of Claim 8, wherein the step of implanting comprises directing ions at an angle of 90° to a plane defined by the principal surface.
12. The transistor structure of Claim 8, wherein the trench bottom region has a doping concentration in a range of 1 x 1016/cm3 to 8 x 1016/cm3.
13. The transistor of Claim 8, wherein the trench bottom region has a doping concentration at least four times that of the drift region.
14. The transistor structure of Claim 8, wherein the step of forming a body region comprises: forming a channel portion in contact with a side of the trench near the principal surface; and forming a deep body portion spaced apart from a side of the trench and near the bottom of the trench.
15. The transistor structure of Claim 14, wherein the trench bottom region is spaced apart from the deep body portion.
16. The transistor structure of Claim 8, wherein the trench bottom region extends at least 0.5μm into the drift region from the bottom of the trench.
17. The transistor structure of Claim 8, wherein the trench bottom region is spaced apart from the substrate by at least lμ .
PCT/US1997/012046 1996-07-19 1997-07-18 High density trench dmos transistor with trench bottom implant WO1998004004A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU37241/97A AU3724197A (en) 1996-07-19 1997-07-18 High density trench dmos transistor with trench bottom implant
DE69739206T DE69739206D1 (en) 1996-07-19 1997-07-18 HIGH DENSITY TRIANGLE DIGITAL TRANSISTOR WITH TRIANGLE IMPLANT PLANTING
JP10506999A JP2000515684A (en) 1996-07-19 1997-07-18 High density trench DMOS transistor with trench bottom implant region
EP97934104A EP0948818B1 (en) 1996-07-19 1997-07-18 High density trench dmos transistor with trench bottom implant

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US68436396A 1996-07-19 1996-07-19
US684,363 1996-07-19

Publications (1)

Publication Number Publication Date
WO1998004004A1 true WO1998004004A1 (en) 1998-01-29

Family

ID=24747740

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/012046 WO1998004004A1 (en) 1996-07-19 1997-07-18 High density trench dmos transistor with trench bottom implant

Country Status (6)

Country Link
US (1) US5929481A (en)
EP (2) EP0948818B1 (en)
JP (1) JP2000515684A (en)
AU (1) AU3724197A (en)
DE (1) DE69739206D1 (en)
WO (1) WO1998004004A1 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1009022A1 (en) * 1998-12-09 2000-06-14 STMicroelectronics S.r.l. Manufacturing process of a high integration density power MOS device
EP1014450A2 (en) * 1998-11-25 2000-06-28 Siliconix Incorporated Trench MOSFET having improved breakdown and on-resistance characteristics and process for manufacturing the same
EP1041640A2 (en) * 1999-04-01 2000-10-04 Intersil Corporation Power trench MOS-gated device and method of manufacturing it
WO2002058161A2 (en) * 2001-01-22 2002-07-25 Fairchild Semiconductor Corporation Mos device having a trench gate electrode
WO2003032797A1 (en) 2001-10-12 2003-04-24 Kimberly-Clark Worldwide, Inc. Interfolded towel dispenser
US6764906B2 (en) 2001-07-03 2004-07-20 Siliconix Incorporated Method for making trench mosfet having implanted drain-drift region
US6849898B2 (en) 2001-08-10 2005-02-01 Siliconix Incorporated Trench MIS device with active trench corners and thick bottom oxide
US6882000B2 (en) 2001-08-10 2005-04-19 Siliconix Incorporated Trench MIS device with reduced gate-to-drain capacitance
WO2005088722A2 (en) * 2004-03-03 2005-09-22 Koninklijke Philips Electronics N.V. Trench field effect transistor and method of making it
WO2005088695A1 (en) * 2004-03-03 2005-09-22 Koninklijke Philips Electronics N.V. Trench field effect transistor and method of making it
US7009247B2 (en) 2001-07-03 2006-03-07 Siliconix Incorporated Trench MIS device with thick oxide layer in bottom of gate contact trench
US7033876B2 (en) 2001-07-03 2006-04-25 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same
US7291884B2 (en) 2001-07-03 2007-11-06 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide
DE19913375B4 (en) * 1999-03-24 2009-03-26 Infineon Technologies Ag Method for producing a MOS transistor structure

Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6163051A (en) * 1995-08-24 2000-12-19 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device
KR100225409B1 (en) * 1997-03-27 1999-10-15 김덕중 Trench dmos and method of manufacturing the same
DE19801095B4 (en) * 1998-01-14 2007-12-13 Infineon Technologies Ag Power MOSFET
US6351009B1 (en) * 1999-03-01 2002-02-26 Fairchild Semiconductor Corporation MOS-gated device having a buried gate and process for forming same
US6198127B1 (en) * 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
US7084456B2 (en) * 1999-05-25 2006-08-01 Advanced Analogic Technologies, Inc. Trench MOSFET with recessed clamping diode using graded doping
JP4169879B2 (en) * 1999-08-20 2008-10-22 新電元工業株式会社 High voltage transistor
US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US6710403B2 (en) 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6818513B2 (en) 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US6893923B2 (en) * 2001-03-21 2005-05-17 International Rectifier Corporation Reduced mask count process for manufacture of mosgated device
DE10131707B4 (en) * 2001-06-29 2009-12-03 Atmel Automotive Gmbh Method for producing a DMOS transistor and its use for producing an integrated circuit
DE10131705B4 (en) 2001-06-29 2010-03-18 Atmel Automotive Gmbh Method for producing a DMOS transistor
DE10131706B4 (en) * 2001-06-29 2005-10-06 Atmel Germany Gmbh Method for producing a DMOS transistor
US20060038223A1 (en) * 2001-07-03 2006-02-23 Siliconix Incorporated Trench MOSFET having drain-drift region comprising stack of implanted regions
US6709930B2 (en) * 2002-06-21 2004-03-23 Siliconix Incorporated Thicker oxide formation at the trench bottom by selective oxide deposition
US6635544B2 (en) 2001-09-07 2003-10-21 Power Intergrations, Inc. Method of fabricating a high-voltage transistor with a multi-layered extended drain structure
US6573558B2 (en) * 2001-09-07 2003-06-03 Power Integrations, Inc. High-voltage vertical transistor with a multi-layered extended drain structure
US7221011B2 (en) * 2001-09-07 2007-05-22 Power Integrations, Inc. High-voltage vertical transistor with a multi-gradient drain doping profile
US6555873B2 (en) * 2001-09-07 2003-04-29 Power Integrations, Inc. High-voltage lateral transistor with a multi-layered extended drain structure
US7786533B2 (en) 2001-09-07 2010-08-31 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
US6657254B2 (en) 2001-11-21 2003-12-02 General Semiconductor, Inc. Trench MOSFET device with improved on-resistance
US6784505B2 (en) * 2002-05-03 2004-08-31 Fairchild Semiconductor Corporation Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique
US7012005B2 (en) * 2002-06-25 2006-03-14 Siliconix Incorporated Self-aligned differential oxidation in trenches by ion implantation
US6919599B2 (en) * 2002-06-28 2005-07-19 International Rectifier Corporation Short channel trench MOSFET with reduced gate charge
US6777722B1 (en) * 2002-07-02 2004-08-17 Lovoltech, Inc. Method and structure for double dose gate in a JFET
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
JP3742400B2 (en) * 2003-04-23 2006-02-01 株式会社東芝 Semiconductor device and manufacturing method thereof
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP3954541B2 (en) * 2003-08-05 2007-08-08 株式会社東芝 Semiconductor device and manufacturing method thereof
DE10345347A1 (en) * 2003-09-19 2005-04-14 Atmel Germany Gmbh Method of making a lateral drift region dopant profile DMOS transistor
KR100994719B1 (en) 2003-11-28 2010-11-16 페어차일드코리아반도체 주식회사 Superjunction semiconductor device
US7279743B2 (en) * 2003-12-02 2007-10-09 Vishay-Siliconix Closed cell trench metal-oxide-semiconductor field effect transistor
DE10361135B4 (en) * 2003-12-23 2006-07-27 Infineon Technologies Ag Trench transistor and method of making a high energy implanted drain trench transistor
US7368777B2 (en) 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
WO2005084221A2 (en) 2004-03-01 2005-09-15 International Rectifier Corporation Self aligned contact structure for trench device
US7045857B2 (en) * 2004-03-26 2006-05-16 Siliconix Incorporated Termination for trench MIS device having implanted drain-drift region
US8183629B2 (en) * 2004-05-13 2012-05-22 Vishay-Siliconix Stacked trench metal-oxide-semiconductor field effect transistor device
CN100517719C (en) * 2004-06-30 2009-07-22 先进模拟科技公司 Trench mosfet with recessed clamping diode
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
DE102004042758B4 (en) * 2004-09-03 2006-08-24 Infineon Technologies Ag Semiconductor device
JP4899405B2 (en) * 2004-11-08 2012-03-21 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
WO2006108011A2 (en) 2005-04-06 2006-10-12 Fairchild Semiconductor Corporation Trenched-gate field effect transistors and methods of forming the same
AT504289A2 (en) * 2005-05-26 2008-04-15 Fairchild Semiconductor TRENCH-GATE FIELD EFFECT TRANSISTORS AND METHOD FOR MAKING THE SAME
JP4939012B2 (en) * 2005-08-26 2012-05-23 ルネサスエレクトロニクス株式会社 Semiconductor device
US8883595B2 (en) * 2006-02-23 2014-11-11 Vishay-Siliconix Process for forming a short channel trench MOSFET and device formed thereby
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US8471390B2 (en) * 2006-05-12 2013-06-25 Vishay-Siliconix Power MOSFET contact metallization
US7560755B2 (en) * 2006-06-09 2009-07-14 Dsm Solutions, Inc. Self aligned gate JFET structure and method
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
KR100868542B1 (en) 2006-12-29 2008-11-13 어드밴스드 아날로직 테크놀로지스 인코퍼레이티드 Trench MOSFET with recessed clamping diode
US7468536B2 (en) 2007-02-16 2008-12-23 Power Integrations, Inc. Gate metal routing for transistor with checkerboarded layout
US7557406B2 (en) * 2007-02-16 2009-07-07 Power Integrations, Inc. Segmented pillar layout for a high-voltage vertical transistor
US7859037B2 (en) 2007-02-16 2010-12-28 Power Integrations, Inc. Checkerboarded high-voltage vertical transistor layout
US8653583B2 (en) 2007-02-16 2014-02-18 Power Integrations, Inc. Sensing FET integrated with a high-voltage transistor
US7595523B2 (en) * 2007-02-16 2009-09-29 Power Integrations, Inc. Gate pullback at ends of high-voltage vertical transistor structure
US8368126B2 (en) * 2007-04-19 2013-02-05 Vishay-Siliconix Trench metal oxide semiconductor with recessed trench material and remote contacts
CN103762243B (en) 2007-09-21 2017-07-28 飞兆半导体公司 Power device
US7772668B2 (en) 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
US20100090274A1 (en) * 2008-10-10 2010-04-15 Force Mos Technology Co. Ltd. Trench mosfet with shallow trench contact
US8174067B2 (en) 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8022471B2 (en) * 2008-12-31 2011-09-20 Force-Mos Technology Corp. Trench metal oxide semiconductor field effect transistor (MOSFET) with low gate to drain coupled charges (Qgd) structures
JP5013436B2 (en) 2009-06-04 2012-08-29 三菱電機株式会社 Power semiconductor device
JP2011018694A (en) * 2009-07-07 2011-01-27 Toyota Motor Corp Semiconductor device
US9306056B2 (en) * 2009-10-30 2016-04-05 Vishay-Siliconix Semiconductor device with trench-like feed-throughs
US8604525B2 (en) 2009-11-02 2013-12-10 Vishay-Siliconix Transistor structure with feed-through source-to-substrate contact
US8378392B2 (en) * 2010-04-07 2013-02-19 Force Mos Technology Co., Ltd. Trench MOSFET with body region having concave-arc shape
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US8525254B2 (en) * 2010-08-12 2013-09-03 Infineon Technologies Austria Ag Silicone carbide trench semiconductor device
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8742490B2 (en) * 2011-05-02 2014-06-03 Monolithic Power Systems, Inc. Vertical power transistor die packages and associated methods of manufacturing
CN103426924A (en) * 2012-05-14 2013-12-04 无锡华润上华半导体有限公司 Groove-type power MOSFET and manufacturing method thereof
JP2013243179A (en) * 2012-05-18 2013-12-05 Sumitomo Electric Ind Ltd Silicon carbide semiconductor device
JP2013258333A (en) * 2012-06-13 2013-12-26 Toshiba Corp Power semiconductor device
US9543396B2 (en) 2013-12-13 2017-01-10 Power Integrations, Inc. Vertical transistor device structure with cylindrically-shaped regions
US10325988B2 (en) 2013-12-13 2019-06-18 Power Integrations, Inc. Vertical transistor device structure with cylindrically-shaped field plates
CN104952731A (en) * 2014-03-31 2015-09-30 桂林斯壮微电子有限责任公司 Field effect transistor with accumulation effect and production method thereof
DE102014109926A1 (en) * 2014-07-15 2016-01-21 Infineon Technologies Austria Ag A semiconductor device having a plurality of transistor cells and manufacturing methods
US9425304B2 (en) 2014-08-21 2016-08-23 Vishay-Siliconix Transistor structure with improved unclamped inductive switching immunity
DE102014112338A1 (en) 2014-08-28 2016-03-03 Infineon Technologies Austria Ag Semiconductor device and method for manufacturing a semiconductor device
US9443973B2 (en) * 2014-11-26 2016-09-13 Infineon Technologies Austria Ag Semiconductor device with charge compensation region underneath gate trench
DE102015202764B4 (en) * 2015-02-16 2018-05-30 Infineon Technologies Austria Ag A method of manufacturing a trench semiconductor device having an insulating block in a semiconductor trench and semiconductor device
US11264457B1 (en) 2020-11-20 2022-03-01 Globalfoundries U.S. Inc. Isolation trenches augmented with a trap-rich layer
US20230261104A1 (en) * 2022-02-11 2023-08-17 Infineon Technologies Austria Ag Semiconductor device having a current spreading region
CN116646391A (en) * 2023-07-26 2023-08-25 深圳市锐骏半导体股份有限公司 Trench power device and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4893160A (en) * 1987-11-13 1990-01-09 Siliconix Incorporated Method for increasing the performance of trenched devices and the resulting structure
US4964080A (en) * 1990-03-09 1990-10-16 Intel Corporation Three-dimensional memory cell with integral select transistor
JPH05343691A (en) * 1992-06-08 1993-12-24 Nippondenso Co Ltd Vertical insulated-gate field-effect transistor
US5442214A (en) * 1994-08-09 1995-08-15 United Microelectronics Corp. VDMOS transistor and manufacturing method therefor
US5558313A (en) * 1992-07-24 1996-09-24 Siliconix Inorporated Trench field effect transistor with reduced punch-through susceptibility and low RDSon

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553462A (en) * 1978-10-13 1980-04-18 Int Rectifier Corp Mosfet element
US4705759B1 (en) 1978-10-13 1995-02-14 Int Rectifier Corp High power mosfet with low on-resistance and high breakdown voltage
JPS5658267A (en) * 1979-10-17 1981-05-21 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type field-effect transistor
US4983160A (en) 1985-09-27 1991-01-08 Nestle S.A. Rigid transparent fluid conduit for ophthalmic surgical irrigation
US5072266A (en) * 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US5168331A (en) * 1991-01-31 1992-12-01 Siliconix Incorporated Power metal-oxide-semiconductor field effect transistor
JPH0621468A (en) * 1992-06-29 1994-01-28 Toshiba Corp Insulated gate semiconductor device
US5341011A (en) * 1993-03-15 1994-08-23 Siliconix Incorporated Short channel trenched DMOS transistor
US5410170A (en) * 1993-04-14 1995-04-25 Siliconix Incorporated DMOS power transistors with reduced number of contacts using integrated body-source connections
US5688725A (en) * 1994-12-30 1997-11-18 Siliconix Incorporated Method of making a trench mosfet with heavily doped delta layer to provide low on-resistance
JPH08306914A (en) * 1995-04-27 1996-11-22 Nippondenso Co Ltd Semiconductor device and its manufacture
US5821583A (en) * 1996-03-06 1998-10-13 Siliconix Incorporated Trenched DMOS transistor with lightly doped tub

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4893160A (en) * 1987-11-13 1990-01-09 Siliconix Incorporated Method for increasing the performance of trenched devices and the resulting structure
US4964080A (en) * 1990-03-09 1990-10-16 Intel Corporation Three-dimensional memory cell with integral select transistor
JPH05343691A (en) * 1992-06-08 1993-12-24 Nippondenso Co Ltd Vertical insulated-gate field-effect transistor
US5558313A (en) * 1992-07-24 1996-09-24 Siliconix Inorporated Trench field effect transistor with reduced punch-through susceptibility and low RDSon
US5442214A (en) * 1994-08-09 1995-08-15 United Microelectronics Corp. VDMOS transistor and manufacturing method therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0948818A4 *

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1014450A2 (en) * 1998-11-25 2000-06-28 Siliconix Incorporated Trench MOSFET having improved breakdown and on-resistance characteristics and process for manufacturing the same
EP1014450A3 (en) * 1998-11-25 2001-02-07 Siliconix Incorporated Trench MOSFET having improved breakdown and on-resistance characteristics and process for manufacturing the same
EP1009022A1 (en) * 1998-12-09 2000-06-14 STMicroelectronics S.r.l. Manufacturing process of a high integration density power MOS device
US6541318B2 (en) 1998-12-09 2003-04-01 Stmicroelectronics, S.R.L. Manufacturing process of a high integration density power MOS device
DE19913375B4 (en) * 1999-03-24 2009-03-26 Infineon Technologies Ag Method for producing a MOS transistor structure
EP1041640A2 (en) * 1999-04-01 2000-10-04 Intersil Corporation Power trench MOS-gated device and method of manufacturing it
EP1041640A3 (en) * 1999-04-01 2000-10-11 Intersil Corporation Power trench MOS-gated device and method of manufacturing it
WO2002058161A2 (en) * 2001-01-22 2002-07-25 Fairchild Semiconductor Corporation Mos device having a trench gate electrode
US6552391B2 (en) 2001-01-22 2003-04-22 Fairchild Semiconductor Corporation Low voltage dual-well trench MOS device
WO2002058161A3 (en) * 2001-01-22 2003-05-15 Fairchild Semiconductor Mos device having a trench gate electrode
US7009247B2 (en) 2001-07-03 2006-03-07 Siliconix Incorporated Trench MIS device with thick oxide layer in bottom of gate contact trench
US6764906B2 (en) 2001-07-03 2004-07-20 Siliconix Incorporated Method for making trench mosfet having implanted drain-drift region
US7435650B2 (en) 2001-07-03 2008-10-14 Siliconix Incorporated Process for manufacturing trench MIS device having implanted drain-drift region and thick bottom oxide
US7416947B2 (en) 2001-07-03 2008-08-26 Siliconix Incorporated Method of fabricating trench MIS device with thick oxide layer in bottom of trench
US7326995B2 (en) 2001-07-03 2008-02-05 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide
US7291884B2 (en) 2001-07-03 2007-11-06 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide
US7033876B2 (en) 2001-07-03 2006-04-25 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same
US6921697B2 (en) 2001-08-10 2005-07-26 Siliconix Incorporated Method for making trench MIS device with reduced gate-to-drain capacitance
US6849898B2 (en) 2001-08-10 2005-02-01 Siliconix Incorporated Trench MIS device with active trench corners and thick bottom oxide
US6903412B2 (en) 2001-08-10 2005-06-07 Siliconix Incorporated Trench MIS device with graduated gate oxide layer
US6882000B2 (en) 2001-08-10 2005-04-19 Siliconix Incorporated Trench MIS device with reduced gate-to-drain capacitance
US6875657B2 (en) * 2001-08-10 2005-04-05 Siliconix Incorporated Method of fabricating trench MIS device with graduated gate oxide layer
WO2003032797A1 (en) 2001-10-12 2003-04-24 Kimberly-Clark Worldwide, Inc. Interfolded towel dispenser
WO2005088695A1 (en) * 2004-03-03 2005-09-22 Koninklijke Philips Electronics N.V. Trench field effect transistor and method of making it
WO2005088722A3 (en) * 2004-03-03 2006-03-30 Koninkl Philips Electronics Nv Trench field effect transistor and method of making it
WO2005088722A2 (en) * 2004-03-03 2005-09-22 Koninklijke Philips Electronics N.V. Trench field effect transistor and method of making it
US7682889B2 (en) 2004-03-03 2010-03-23 Nxp B.V. Trench field effect transistor and method of making it

Also Published As

Publication number Publication date
EP0948818A4 (en) 2000-01-19
JP2000515684A (en) 2000-11-21
AU3724197A (en) 1998-02-10
EP2043158A2 (en) 2009-04-01
DE69739206D1 (en) 2009-02-26
EP2043158B1 (en) 2013-05-15
EP0948818B1 (en) 2009-01-07
EP2043158A3 (en) 2010-04-28
EP0948818A1 (en) 1999-10-13
US5929481A (en) 1999-07-27

Similar Documents

Publication Publication Date Title
EP0948818B1 (en) High density trench dmos transistor with trench bottom implant
US5689128A (en) High density trenched DMOS transistor
EP0580452B1 (en) Field effect trench transistor having lightly doped epitaxial region on the surface portion thereof
KR100759937B1 (en) A trench mosfet device, and a method of forming such a trench mosfet device
EP0763259B1 (en) Punch-through field effect transistor
US5821583A (en) Trenched DMOS transistor with lightly doped tub
US5629543A (en) Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
EP0616372B1 (en) Short channel trenched DMOS transistor
US6566201B1 (en) Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
US6992350B2 (en) High voltage power MOSFET having low on-resistance
EP2178125A2 (en) Trenched field effect transistor and method of its manufacture
EP1454361A1 (en) Trench mosfet device with polycrystalline silicon source contact structure
EP1468453A2 (en) High voltage power mosfet having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source
EP1454352A1 (en) Method for forming trench mosfet device with low parasitic resistance
WO1997007548A1 (en) Low voltage short channel trench dmos transistor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG UZ VN YU AM AZ BY KG KZ MD RU TJ TM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH KE LS MW SD SZ UG ZW AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1997934104

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWP Wipo information: published in national office

Ref document number: 1997934104

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: CA