WO1998033267A2 - High efficiency power converter - Google Patents

High efficiency power converter Download PDF

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Publication number
WO1998033267A2
WO1998033267A2 PCT/US1998/001498 US9801498W WO9833267A2 WO 1998033267 A2 WO1998033267 A2 WO 1998033267A2 US 9801498 W US9801498 W US 9801498W WO 9833267 A2 WO9833267 A2 WO 9833267A2
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WO
WIPO (PCT)
Prior art keywords
power converter
voltage
controlled
primary
output
Prior art date
Application number
PCT/US1998/001498
Other languages
French (fr)
Other versions
WO1998033267A3 (en
Inventor
Martin F. Schlecht
Original Assignee
Fische, Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=21887510&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO1998033267(A2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Fische, Llc filed Critical Fische, Llc
Priority to AU59314/98A priority Critical patent/AU722043B2/en
Priority to JP53221198A priority patent/JP2002514378A/en
Priority to EP98902723A priority patent/EP0954899A2/en
Priority to CA002278250A priority patent/CA2278250A1/en
Publication of WO1998033267A2 publication Critical patent/WO1998033267A2/en
Publication of WO1998033267A3 publication Critical patent/WO1998033267A3/en

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10Parallel operation of dc sources
    • H02J1/102Parallel operation of dc sources being switching converters
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/337Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
    • H02M3/3372Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration of the parallel type
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/337Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
    • H02M3/3372Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration of the parallel type
    • H02M3/3374Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration of the parallel type with preregulator, e.g. current injected push-pull
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0067Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007Plural converter units in cascade
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This invention pertains to switching power converters.
  • a specific example of a power converter is a DC-DC power supply that draws 100 watts of power from a 48 volt DC source and converts it to a 5 volt DC output to drive logic circuitry.
  • the nominal values and ranges of the input and output voltages, as well as the maximum power handling capability of the converter, depend on the application. It is common today for switching power supplies to have a switching frequency of 100 kHz or higher. Such a high switching frequency permits the capacitors, inductors, and transformers in the converter co be physically small. The reduction in the overall volume of the converter that results is desirable to the users of such supplies.
  • Another important attribute of a power supply is its efficiency. The higher the efficiency, the less heat that is dissipated within the supply, and the less design effort, volume, weight, and cost that must be devoted to remove this heat. A higher efficiency is therefore also desirable to the users of these supplies.
  • a significant fraction of the energy dissipated in a power supply is due to the on-state (or conduction) loss of the diodes used, particularly if the load and/or source voltages are low (e.g. 3.3, 5, or 12 volts) .
  • the diodes are sometimes replaced with transistors whose on-state voltages are much smaller. These transistors, called synchronous rectifiers, are typically power MOSFETs for converters switching in the 100 kHz and higher range.
  • transistors as synchronous rectifiers in high switching frequency converters presents several technical challenges.
  • Another challenge is the need to minimize losses during the switch transitions of the synchronous rectifiers. An important portion of these switching losses is due to the need to charge and discharge the parasitic capacitances of the transistors, the parasitic inductances of interconnections, and the leakage inductance of transformer windings .
  • a power converter comprises a power source and a primary transformer winding circuit having at least one primary winding connected to the source.
  • a secondary transformer winding circuit has at least one secondary winding coupled to the at least one primary winding.
  • Plural controlled rectifiers such as voltage controlled field effect transistors, each having a parallel uncontrolled rectifier, are connected to a secondary winding. Each controlled rectifier is turned on and off in synchronization with the voltage waveform across a primary winding to provide an output .
  • Each primary winding has a voltage waveform with a fixed duty cycle and transition times which are short relative to the on-state and off-state times of the controlled rectifiers.
  • a regulator regulates the output while the fixed duty cycle is maintained.
  • first and second primary transformer windings are connected to the source and first and second primary switches are connected in series with the first and second primary windings, respectively.
  • First and second secondary transformer windings are coupled to the first and second primary windings, respectively.
  • First and second controlled rectifiers each having a parallel uncontrolled rectifier, are in series with the first and second secondary windings, respectively.
  • a controller turns on the first and second primary switches in opposition, each for approximately one half of the switching cycle with transition times which are short relative to the on-state and off-state times of the first and second controlled rectifiers.
  • the first and second controlled rectifiers are controlled to be on at substantially the same times that the first and second primary switches, respectively, are on.
  • each controlled rectifier is turned on and off by a signal applied to a control terminal relative to a reference terminal of the controlled rectifier, and the reference terminals of the controlled rectifiers are connected to a common node.
  • the signal that controls each controlled rectifier is derived from the voltage at the connection between the other controlled rectifier and its associated secondary winding.
  • Regulation may be through a separate regulation stage which in one form is on the primary side of the converter as part of the power source. Power conversion may then be regulated in response to a variable sensed on the primary side of the converter.
  • the regulator may be a regulation stage on the secondary side of the converter, and power conversion may be regulated by control of the controlled rectifiers.
  • the on-state voltage of a controlled rectifier may be made larger than its minimum value to provide regulation, or the on-state duration of a controlled rectifier may be shorter than its maximum value to provide regulation.
  • the preferred systems include reset circuits associated with transformers for flow of magnetizing current. The energy stored in the magnetizing inductance may be recovered.
  • the reset circuit comprises a tertiary transformer winding, and in another form it comprises a clamp.
  • the power source has a current fed output, the current fed output characteristic of the power source being provided by an inductor.
  • the power source may have a voltage-fed output where the voltage- fed output characteristic of the power source is provided by a capacitor. In either case, the characteristics may alternatively be provided by active circuitry.
  • the primary switches With the preferred current -fed output, the primary switches are both turned on during overlapping periods, and the overlapping periods may be selected to achieve maximum efficiency. With the voltage- fed output, the primary switches are both turned off during overlapping periods. Additional leakage or parasitic inductance may be added to the circuit to accommodate an overlap period.
  • a signal controlling a controlled rectifier is derived with a capacitive divider circuit.
  • a circuit may determine the DC component of the signal controlling the controlled rectifier, and the DC component of the signal may be adjusted to provide regulation.
  • an ORing controlled rectifier connects the converter's output to an output bus to which multiple converter outputs are coupled, and the ORing controlled rectifier is turned off if the power converter fails.
  • the signal controlling the ORing controlled rectifier is derived from one or more secondary windings.
  • the ORing controlled rectifier is turned on when the converter's output voltage approximately matches the bus voltage.
  • Figure 1 is a block diagram illustrating a preferred embodiment of the invention.
  • Figure 2 is a schematic of an embodiment of the invention with synchronous rectifiers replaced by diodes.
  • Figure 3 is an illustration of a preferred embodiment of the invention with the controlled rectifiers and parallel uncontrolled rectifiers illustrated.
  • Figure 4 illustrates an alternative location of the synchronous rectifiers in the circuit of Figure 3.
  • Figure 5 illustrates the circuit of Figure 3 with important parasitic capacitances and inductances illustrated.
  • Figure 6A illustrates another embodiment of the invention with the tertiary winding connected to the primary side.
  • Figure 6B illustrates another embodiment of the invention with a voltage fed isolation stage.
  • Figure 7 illustrates a secondary circuit having capacitive dividers to divide the voltages applied to the control terminals of the controlled rectifiers.
  • Figure 8 shows an alternative embodiment in which the output is regulated by controlling the voltage applied to the control terminals of the controlled rectifiers.
  • FIG. 9 illustrates an embodiment of the invention in which the primary windings are tightly coupled.
  • Figure 10 illustrates the use of an ORing controlled rectifier to couple the power converter to an output bus.
  • One embodiment of the invention described herein pertains to an electrically isolated DC-DC converter that might be used to deliver power at a low DC voltage (e.g. 5 volts) from a DC source such as a battery or a rectified utility.
  • a transformer is used to provide the electrical isolation and to provide a step-down (or step-up) in voltage level according to its turns-ratio.
  • Switches in the form of power semiconductor transistors and diodes are used in conjunction with capacitors and inductors to create the conversion.
  • a control circuit is typically included to provide the drive signals to the transistors' control terminals.
  • the switching frequency is high (e.g. 100 kHz and above) it is typical today to use power MOSFETs and Schottky diodes for the converter's switches since these majority carrier devices can undergo faster switch transitions than minority carrier devices such as power bipolar transistors and bipolar diodes.
  • DC-DC converters are designed to provide regulation of their output voltage in the face of input voltage and output current variations. For example, a converter might need to maintain a 5 volt output (plus or minus a few percent) as its input varies over the range of 36 to 75 volts and its output current ranges from 1 to 25 amps. This ability to provide regulation is usually the result of the power circuit's topology and the manner in which its switching devices are controlled. Sometimes the regulation function is supplied by (or augmented with) a linear regulator.
  • Figure 1 shows a block diagram of a DC-DC converter that represents one embodiment of the invention. It shows a two stage converter structure where the power first flows through one stage and then through the next .
  • One stage provides the regulation function and the other provides the electrical isolation and/or step-down (or step-up) function.
  • the regulation stage is situated before the isolation stage, but this ordering is not necessary for the invention.
  • the block diagram shows a control function.
  • the purpose of this control function is to determine when the transistors in the power circuit will be turned on and off (or to determine the drive of a linear regulator) .
  • the control circuit typically senses voltages and currents at the input, at the output, and/or within the power circuit.
  • FIG. 2 shows one way to implement the two power stages represented in the block diagram of Figure 1.
  • diodes rather than synchronous rectifiers, are used to simplify the initial description of the circuit's operation.
  • the topology of the regulation stage is that of a "down converter" .
  • This canonical switching cell has a capacitor, C IN , a transistor, Q R , a diode, D R , and an inductor, L.
  • Regulation is by control of the duty cycle of the transistor Q R in response to one or more parameters sensed in the circuit.
  • the regulation stage can be modified by providing higher order filters at its input and output, by replacing the diode with a synchronous rectifier, by adding resonant elements to create a "multi-resonant" converter and the like.
  • the topology of the isolation stage shown in Figure 2 has two transformers that are not, in this case, coupled.
  • Each of these transformers Tl and T2 has three windings: a primary winding Tl PR ⁇ , T2 PRI ; a secondary winding T1 SEC , T2 ⁇ EC ; and a tertiary winding T1 TER ,T2 TER .
  • the transformer windings are connected through MOSFETs Ql and Q2 on the primary windings and through diodes Dl, D2 , D3 , and D4 on the secondary and tertiary windings.
  • the stage is "current- fed" , in this case by the inductor L from the output of the regulation stage.
  • the output filter is simply a capacitor C ou ⁇ whose voltage is relatively constant over the time frame of the switching cycle. Additional filtering stages could be added to this output filter in a known manner .
  • the operation of the isolation stage proceeds in the following manner. First, for approximately one half of the switching cycle, transistor Ql is on and Q2 is off. The current flowing through inductor L therefore flows through the primary winding of transformer Tl , and a corresponding current (transformed by the turns ratio) flows through the secondary winding of Tl and through diode Dl to the output filter capacitor C ou ⁇ and the load. During this time the magnetizing current in Tl is increasing due to the positive voltage placed across its windings. This positive voltage is determined by the output capacitor voltage, V ou ⁇ , plus the forward voltage drop of Dl .
  • transistor Q2 and diode D2 are on and Ql and Dl are off. While the current of inductor L flows through transformer T2 in the same manner as described above for Tl, the magnetizing current of transformer Tl flows through its tertiary winding and diode D3 to the output filter capacitor, C ou ⁇ .
  • This arrangement of the tertiary winding provides a means to reset the Tl transformer core with a negative voltage and to recover most of the magnetizing inductance energy.
  • the tertiary winding may alternatively be connected to other suitable points in the power circuit, including those on the primary side of the transformer. Other techniques for resetting the core and/or for recovering the magnetizing energy are known in the art and may be used here.
  • the tertiary winding could be eliminated and replaced with a conventional clamp circuit attached to either the primary or secondary winding and designed to impose a negative voltage across the transformer during its operative half cycle.
  • Techniques to recover the energy delivered to this clamp circuit such as the one in which a transistor is placed in anti-parallel with a clamping diode so that energy can flow from the clamping circuitry back into the magnetizing inductance, could also be used.
  • the old primary side transistor (say Ql) is turned off.
  • the voltage across this transistor rises as its parasitic capacitance is charged by the current that had been flowing through the channel.
  • this voltage rises high enough to forward bias diode D3 connected to the tertiary winding, the transistor voltage becomes clamped, although an over-ring and/or a commutation interval will occur due to parasitic leakage inductance.
  • all of the current in inductor L will flow through switch Q2 , switch Ql will be off, and the magnetizing current of Tl will flow through diode D3.
  • the body diode of the MOSFET synchronous rectifier is explicitly shown since it plays a role in the circuit's operation. More generally, the schematical drawings of Q3 and Q4 depict the need for a controlled rectifier (e.g. a transistor) and an uncontrolled rectifier (e.g. a diode) connected in parallel. These two devices may be monolithically integrated, as they are for power MOSFETs, or they may be separate components.
  • the positions of these synchronous rectifiers m the circuit are slightly different than the positions of the diodes m Figure 2. They are still in series with their respective secondary windings, but are connected to the minus output terminal rather than the positive output terminal.
  • the current of inductor L flows into the primary of Tl and out its secondary.
  • This secondary side current will flow through transistor Q3 (note that even if Q3 ' s channel is not turned on, the secondary side current will flow through the transistor's internal anti-parallel body diode).
  • the voltage across transformer Tl ' s secondary winding is therefore positive, and equal to the output voltage V ou ⁇ plus the voltage drop across Q3.
  • the voltage across T2 ' s secondary winding is negative during this time, with a magnitude approximately equal to the output voltage if the magnetizing inductance reset circuitry takes approximately the whole half cycle to finish its reset function. (The negative secondary winding voltage may be made greater than the positive voltage so that the core, will finish its reset before the next half cycle begins. This could be accomplished, for example, by using less turns on the tertiary winding.)
  • the voltage at node A during this state of operation is nearly zero with respect to the indicated secondary-side ground node (actually the voltage is slightly negative due to the drop across Q3) .
  • the voltage at node B is, following our example, approximately twice the output voltage (say 10 volts for a 5 volt output) . Given the way these nodes are connected to the synchronous rectifier transistors, Q3 is turned on and Q4 is turned off. These respective conduction states are consistent with transformer Tl delivering the power and transformer T2 being reset.
  • the sequence of operation is as follows. Start with Ql and Q3 on, Q2 and Q4 off. (The clamp circuit's diode D4 may still be on, or it may have stopped conducting at this point if the magnetizing inductance has finished resetting to zero.) First, Q2 is turned on. If we ignore the effects of parasitic capacitances and inductances, the voltage across T2 steps from a negative value to a positive value. The current flowing through inductor L splits between the two primary windings, causing current to flow out of both secondary windings. These secondary currents flow through Q3 and Q4.
  • FIG. 5 shows the same topology as Figure 3, but with several important parasitic capacitances and inductances indicated schematically.
  • Each indicated capacitor (C3 and C4) represents the combined effect of one synchronous rectifier's input capacitance and the other rectifier's output capacitance, as well as other parasitic capacitances.
  • Each indicated inductor (L P1 and L P2 ) represents the combined effect of a transformer leakage inductance and the parasitic inductance associated with the loops formed by the primary side components and the secondary side components.
  • the nearly lossless delivery and recovery of energy is achieved because the circuit topology permits the synchronous rectifier switch transitions to proceed as oscillations between inductors and capacitors. These transitions are short compared to the overall on-state and off-state portions of the switching cycle (e.g. less than 20% of the time is taken up by the transition) .
  • This characteristic of nearly lossless and relatively short transitions which we will call soft switching, is distinct from that used in full resonant, quasi -resonant , or multi- resonant converters where the oscillations last for a large portion, if not all, of the on-state and/or off-state time.
  • the way in which the soft-switching characteristic is achieved can be understood in the following manner.
  • I LP2 reaches (I L - I MPK ) first (and assuming the voltage across C3 has fallen below the threshold voltage of Q3 so that I LP1 is flowing through the body diode of Q3 ) , the oscillation stops because the body diode will not let I LP1 go negative.
  • I LP2 and I LP1 will hold constant at (I L - I MPK ) and zero, respectively. Whatever voltage remains across C3 will then discharge linearly due to the current I LP2 until the body diode of Q4 turns on. The body diode will then carry I LP2 until the overlap interval is over and Ql is turned off.
  • the body diode of Q4 will turn on and prevent this voltage from ringing further negative.
  • the currents I LP1 and I LP2 (which are flowing through the body diodes of Q3 and Q4) will hold constant until the overlap interval is over and Ql is turned off. Once Ql is turned off, an oscillation ensues between L pl and Cl . This oscillation is driven by the current remaining in L P1 when Ql was turned off. Given typical parameter values, this oscillation will continue until I LP1 reaches zero, at which point the body diode of Q3 will turn off. Finally, the magnetizing current I MPK charges up the parallel combination of C4 and Cl until the clamping diode D3 turns on to start the reset half-cycle.
  • the energy lost in this second scenario is a very small fraction (typically less than one ninth) of the total energy originally stored in (or delivered to) L P1 , L P2 , C3 and C4. In other words, most of the parasitic energy is recovered.
  • the required size of the output filter is also affected by the AC ripple currents flowing in the magnetizing inductances of the transformers. Making these inductances as large as possible to reduce their ripple currents is therefore desirable. It is also beneficial to connect the tertiary reset windings back to a suitable point on the primary side as shown in Figure 6A where they are connected to capacitor C B , rather than to connect them to the output filter, as shown in Figure 3. This alternative connection reduces by a factor of two the ripple current seen by the output filter due to the magnetizing inductance currents, compared to the connection shown in Figure 3, since these magnetizing currents no longer flow to the output capacitor during their respective reset half cycles.
  • the power converter circuits described so far have all had an isolation stage that is current fed. It is also possible to incorporate the invention with an isolation stage that is voltage fed. By “voltage fed” it is meant that the voltage across the primary side of the isolation stage is held relatively constant over the time frame of the switching cycle. Such a converter circuit is shown in Figure 6B where two uncoupled transformers are used.
  • the operation of the voltage-fed isolation stage is slightly different than for a current -fed isolation stage.
  • Each primary transistor is still turned on for approximately one half the cycle, but instead of providing a brief overlap period during which both primary transistors, Ql and Q2 , are turned on together, here the primary transistors are both turned off for a brief overlap period.
  • the current flowing into one primary winding and out its respective secondary winding can be determined as follows. Say transistors Ql and Q3 have just been turned on to begin a new half cycle. At the completion of their switch transition they will be carrying some initial current (to be discussed in more detail below) . There is also a difference between the voltage across capacitor C B and the voltage across capacitor C ou ⁇ , both reflected to the secondary side. This voltage differential will be called ⁇ V. It appears across the series circuit composed of the leakage/parasitic inductances and resistances of the primary and secondary windings, T 1PRI and T 1SEC , the transistors Ql and Q3 , and the capacitors C B and C ou ⁇ . The current flowing through this series L-R circuit responds to the voltage across it, ⁇ V, in accordance with the component values, all referenced to the secondary side.
  • Inductor L p2 now has a negative voltage across it and its current I LP2 , will therefore linearly ramp down to zero as its energy is recovered back to CB through the clamping circuit. Once this current reaches zero, the body diode of Q4 will turn off and the current will become negative, but only to the point where it equals the second transform's magnetizing current, I m (reflected to the secondary side). This current will linearly charge capacitor C3 nearly losslessly as energy is delivered to the capacitor from the magnetizing inductance of the second transformer (reflected to the secondary side) . This current will linearly charge capacitor C3 nearly losslessly as energy is delivered to the capacitor from the mangetizing inductance of the second transformer.
  • transistor Q3 will turn on and the current that had been flowing through the body diode of Q3 will commutate to the channel of Q3.
  • I s being the initial value of current mentioned in that discussion.
  • the transition between the two half cycles has a period of time when the two body diodes are conducting. This condition is highly dissipative and should be kept short by keeping the overlap period that both primary side transistors, Ql and Q2 , are off short.
  • the synchronous rectifier MOSFETs Q3 and Q4 in the circuit of Figure 3 are driven with a gate-source voltage equal to approximately twice the output voltage. For a 5 volt output, the 10 volt drive that results is appropriate for common MOSFETs. If the output voltage is such that the gate drive voltage is too large for the ratings of the MOSFET, however, steps must be taken to reduce the drive voltage. For example, if the output voltage is 15 volts, a 30 volt gate drive will result, and it is typically desired that the gate be driven to only 10 volts. Also, some MOSFETs are designed to be driven with only 5 volts, or less, at their gates.
  • Figure 7 shows one way to reduce the drive voltage while maintaining the energy recovery feature.
  • the voltage waveform at node B (or at node A) is capacitively divided down by the series combination of capacitors C5 and C3 (or by C6 and C4 ) .
  • the values of these capacitors are chosen to provide the division of the AC voltage provided at node B (or node A) as desired. For example, if node B has a 30 volt step change and a 10 volt step change is desired at the gate of Q3 , then C5 should have one half the capacitance of C3. Since C3 may be comprised of the parasitic capacitance of Q3 , it is likely to be nonlinear. In this case, an effective value of capacitance that relates the large scale change in charge to the large scale change in voltage should be used in the calculation to determine C5.
  • FIG. 7 shows one way to do this in which two resistors, Rl and R2 (or R3 and R4) , provide the correct division of the DC component of the voltage at node B (or node A) .
  • These resistors should have values large enough to keep their dissipation reasonably small.
  • the resistors should be small enough such that the time constant of the combined capacitor/resistor divider is short enough to respond to transients such as start-up.
  • One variation of the invention described herein would be to create a power supply with multiple outputs by having more than one secondary winding on each transformer in the isolation stage. For example, by using two secondary windings with the same number of turns it would be possible to create a positive 12 volt output and a negative 12 volt output. If the two secondary windings have a different number of turns it would be possible to create two output voltages of different magnitudes (e.g., 5 volts and 3.3 volts) . Another approach for creating multiple outputs would be to have multiple isolation stages, each with a turns -ratio appropriate for their respective output voltages .
  • One advantageous approach to providing linear regulation with the power circuits described here is to control how much the synchronous rectifier MOSFETs are turned on during their conduction state. This can be done by adding circuitry to limit the peak voltage to which their gates will be driven so that their on-state resistances can be made larger than their minimum values.
  • the amount to which the output voltage can be regulated is the difference between the voltage drop of the synchronous rectifiers when their channels are fully on (i.e., when they are at their minimum resistance) and when only their body diodes are carrying the current .
  • One way to accomplish the first technique, that of controlling the peak gate voltage, is to use the basic capacitor divider circuit that was shown in Figure 7.
  • Figure 8 shows an alternative method to control the DC component of the gate voltage waveform.
  • the output voltage (or a scaled version of it) is subtracted from a reference voltage and the error is multipled by the gain of an op-amp circuit.
  • the output of the op-amp (node C) is then connected to the synchronous rectifier gates through resistors that are large enough to not significantly alter the AC waveforms at the gates. With this connection, the DC components of the gate voltages will equal the output voltage of the op-amp at node C. If the gain of the op-amp circuit is large enough, such as when an integrator is used, the error in the output voltage will be driven toward zero.
  • Z F and Z x are impedances that should be chosen, with well established techniques, to ensure stability of this feedback loop while providing the gain desired.
  • the range of voltage required at the output of the op- amp depends on the particular application, and it may include negative values. This range influences the supply voltage requirements for the op-amp. Also, if the op-amp's output voltage gets too high, the synchronous rectifiers may not turn off when they are supposed to. Some means of limiting this voltage, such as a clamp circuit, may therefore be desirable.
  • One way to accomplish the second technique, that of controlling the portion of the half cycle in which the MOSFET is gated on, is to place a low power switch network between the gate of Q3 (or Q4) , node B (or node A) , and ground.
  • This network (composed, say, of analog switches operated with digital control signals) might be used to keep the gate voltage grounded for some period of time after the node voltage increases, and to then connect the gate to node B (or A) for the remainder of the half cycle with a switch capable of bidirectional current flow.
  • the length of the delay would be based on a signal derived from the error in the output voltage.
  • the switch network could be controlled to start out the half cycle with the gate connected to node B (or A) , and then after some delay to connect the gate to ground.
  • Using a synchronous rectifier to provide regulation as well as rectification, as described above, is not limited to multiple-output situations. It can also be used in single-output situations either as the total regulation stage or as an additional regulation stage to augment the first one. It is also possible to use DC-DC switching regulators on the secondary side to achieve the additional regulation desired, or to create more than one output voltage from any of the outputs of the isolation stage.
  • each controlled rectifier With multiple outputs it is not necessary for the gate of each controlled rectifier to be connected to secondary winding of the other transformer which corresponds to the same output. For instance, if the two outputs are 5 volts and 3.3 volts, the gates of the 3.3 volts output controlled rectifiers could be connected to the 5 volt output secondary windings. Doing so would give these controlled rectifiers a 10 volt gate drive, resulting in a lower on- state resistance than if they had a 6.6 volt gate drive.
  • the isolation stage first in the power flow, and to have the regulation stage follow.
  • the circuit might be configured as one isolation/step-down (or step-up) stage followed by several DC-DC switching or linear regulators.
  • the isolation stage is situated, if it is to be current fed this requirement could be met with active circuitry as well as by a passive component such as an inductor.
  • a passive component such as an inductor.
  • the current fed isolation stage follows a regulation stage that is achieved with a linear regulator, then this linear regulator could be designed to have a large AC output impedance to achieve the input requirement of the current fed isolation stage.
  • the regulation stage precedes the isolation stage, it is not necessary to sense the isolated output voltage to control the regulation.
  • An alternative approach is to sense the voltage on the primary side of the isolation stage, which may eliminate the need for secondary side circuitry and the need to bridge the feedback control signal across the isolation barrier.
  • the voltage across C B the capacitor of the third-order output filter of the down converter, could be used.
  • This voltage nearly represents the isolated output voltage (corrected for the turns- ratio) . It differs only due to the resistive (and parasitic inductance commutation) drops between C B and the output. Since these drops are small and proportional to the current flowing through the isolation stage, the error in output voltage they create can either be tolerated or corrected.
  • the current on the primary side could be sensed, multiplied by an appropriate gain, and the result used to modify the reference voltage to which the voltage across C B is compared. Since these resistive drops vary with temperature, it might also be desirable to include temperature compensation in the control circuitry. Note that this approach could also be used to correct for resistive drops along the leads connecting the supply's output to its load.
  • the embodiments of the invention described above have used two uncoupled transformers for the isolation stage. It is also possible, as shown in Figure 9, to use a single transformer T in which, for example, there are two primary windings T PRI1 ,T PRI2 and two secondary windings, T SEC1 , T SEC2 . While the two primary windings may be tightly coupled, either the two secondaries should be loosely coupled to each other or the connections to the output capacitors and synchronous rectifier transistors should provide adequate parasitic inductance. The resulting leakage and parasitic inductance on the secondary side can then be modeled as is shown in Figure 9.
  • diodes When two or more power supplies are connected in parallel, diodes are sometimes placed in series with each supply's output to avoid a situation where one supply's failure, seen as a short at its output, takes down the entire output bus.
  • These "ORing" diodes typically dissipate a significant amount of energy.
  • One way to reduce this dissipation is to replace the diode with a MOSFET having a lower on-state voltage.
  • This "ORing" synchronous rectifier MOSFET can be placed in either output lead, with its body diode pointing in the direction of the output current flow.
  • the voltage for driving the gate of this MOSFET, Q5 can be derived by connecting diodes to node A and/or node B (or to nodes of capacitor dividers connected to these nodes) , as shown in Figure 10. These diodes rectify the switching waveforms at node A and/or node B to give a constant voltage suitable for turning on the ORing MOSFET at node D.
  • a filter capacitor, C F might be added to the circuit as shown in the figure, or the parasitic input capacitance of the ORing MOSFET might be used alone.
  • a resistor R F ensures the gate voltage discharges when the drive is removed.
  • the power supply fails in a way that creates a short at its output, such as when a synchronous rectifier shorts, the voltages at nodes A and B will also be shorted ' after the transient is complete. With its gate drive no longer supplied, the ORing MOSFET will turn off, and the failed supply will be disconnected from the output bus.
  • ORing MOSFET 's gate voltage rises high enough to turn it on before the newly rising output voltage approximately matches the existing bus voltage, then there will be at least a momentary large current flow as the two voltages equalize.
  • additional circuitry can be added to make sure an ORing MOSFET is not turned on until its supply's output voltage has approximately reached the bus voltage. This might be done by sensing the two voltages and taking appropriate action, or it might be done by providing a delay between when the ORing MOSFET 's gate drive is made available and when it is actually applied to the gate. Such a delay should only affect the turn-on, however; the turn-off of the ORing MOSFET should have minimal delay so that the protective function of the transistor can be provided.
  • the regulation stage could be composed of an up-converter .
  • the ideas that have been presented in terms of the N-channel implementation of the synchronous rectifier MOSFET can be modified to apply to the P-channel implementation, as well.
  • the components shown in the schematics of the figures (such as Q3 in Figure 3) could be implemented with several discrete parts connected in parallel.
  • certain aspects of the invention could be applied to a power converter having only one primary transformer winding and/or one secondary transformer winding.

Abstract

A power converter nearly losslessly delivers energy and recovers energy from capacitors (C3, C4) associated with controlled rectifiers (Q3, Q4) in a secondary winding circuit, each controlled rectifier having a parallel uncontrolled rectifier. First and second primary switches (Q1, Q2) in series with first and second primary windings, respectively, are turned on for a fixed duty cycle, each for approximately one half of the switching cycle. Switched transition times are short relative to the on-state and off-state times of the controlled rectifiers. The control inputs to the controlled rectifiers (Q3, Q4) are cross-coupled from opposite secondary transformer windings.

Description

HIGH EFFICIENCY POWER CONVERTER
BACKGROUND OF THE INVENTION
This invention pertains to switching power converters. A specific example of a power converter is a DC-DC power supply that draws 100 watts of power from a 48 volt DC source and converts it to a 5 volt DC output to drive logic circuitry. The nominal values and ranges of the input and output voltages, as well as the maximum power handling capability of the converter, depend on the application. It is common today for switching power supplies to have a switching frequency of 100 kHz or higher. Such a high switching frequency permits the capacitors, inductors, and transformers in the converter co be physically small. The reduction in the overall volume of the converter that results is desirable to the users of such supplies.
Another important attribute of a power supply is its efficiency. The higher the efficiency, the less heat that is dissipated within the supply, and the less design effort, volume, weight, and cost that must be devoted to remove this heat. A higher efficiency is therefore also desirable to the users of these supplies.
A significant fraction of the energy dissipated in a power supply is due to the on-state (or conduction) loss of the diodes used, particularly if the load and/or source voltages are low (e.g. 3.3, 5, or 12 volts) . In order to reduce this conduction loss, the diodes are sometimes replaced with transistors whose on-state voltages are much smaller. These transistors, called synchronous rectifiers, are typically power MOSFETs for converters switching in the 100 kHz and higher range.
The use of transistors as synchronous rectifiers in high switching frequency converters presents several technical challenges. One is the need to provide properly timed drives to the control terminals of these transistors. This task is made more complicated when the converter provides electrical isolation between its input and output because the synchronous rectifier drives are then isolated from the drives of the main, primary side transistors. Another challenge is the need to minimize losses during the switch transitions of the synchronous rectifiers. An important portion of these switching losses is due to the need to charge and discharge the parasitic capacitances of the transistors, the parasitic inductances of interconnections, and the leakage inductance of transformer windings .
SUMMARY OF THE INVENTION Various approaches to addressing these technical challenges have been presented in the prior art, but further improvements are needed. In response to this need, a new power circuit topology designed to work with synchronous rectifiers in a manner that better addresses the challenges is presented here.
In preferred embodiments of the invention, a power converter comprises a power source and a primary transformer winding circuit having at least one primary winding connected to the source. A secondary transformer winding circuit has at least one secondary winding coupled to the at least one primary winding. Plural controlled rectifiers, such as voltage controlled field effect transistors, each having a parallel uncontrolled rectifier, are connected to a secondary winding. Each controlled rectifier is turned on and off in synchronization with the voltage waveform across a primary winding to provide an output . Each primary winding has a voltage waveform with a fixed duty cycle and transition times which are short relative to the on-state and off-state times of the controlled rectifiers. A regulator regulates the output while the fixed duty cycle is maintained.
In the preferred embodiments, first and second primary transformer windings are connected to the source and first and second primary switches are connected in series with the first and second primary windings, respectively. First and second secondary transformer windings are coupled to the first and second primary windings, respectively. First and second controlled rectifiers, each having a parallel uncontrolled rectifier, are in series with the first and second secondary windings, respectively. A controller turns on the first and second primary switches in opposition, each for approximately one half of the switching cycle with transition times which are short relative to the on-state and off-state times of the first and second controlled rectifiers. The first and second controlled rectifiers are controlled to be on at substantially the same times that the first and second primary switches, respectively, are on. - A -
In a system embodying the invention, energy may be nearly losslessly delivered to and recovered from capacitors associated with the controlled rectifiers during their transition times. In the preferred embodiments, the first primary and secondary transformer windings and the second primary and secondary transformer windings are on separate uncoupled transformers, but the two primary windings and two secondary windings may be coupled on a single transformer. Preferably, each controlled rectifier is turned on and off by a signal applied to a control terminal relative to a reference terminal of the controlled rectifier, and the reference terminals of the controlled rectifiers are connected to a common node. Further, the signal that controls each controlled rectifier is derived from the voltage at the connection between the other controlled rectifier and its associated secondary winding.
Regulation may be through a separate regulation stage which in one form is on the primary side of the converter as part of the power source. Power conversion may then be regulated in response to a variable sensed on the primary side of the converter. Alternatively, the regulator may be a regulation stage on the secondary side of the converter, and power conversion may be regulated by control of the controlled rectifiers. Specifically, the on-state voltage of a controlled rectifier may be made larger than its minimum value to provide regulation, or the on-state duration of a controlled rectifier may be shorter than its maximum value to provide regulation. The preferred systems include reset circuits associated with transformers for flow of magnetizing current. The energy stored in the magnetizing inductance may be recovered. In one form, the reset circuit comprises a tertiary transformer winding, and in another form it comprises a clamp.
In preferred embodiments, the power source has a current fed output, the current fed output characteristic of the power source being provided by an inductor. Alternatively, the power source may have a voltage-fed output where the voltage- fed output characteristic of the power source is provided by a capacitor. In either case, the characteristics may alternatively be provided by active circuitry. With the preferred current -fed output, the primary switches are both turned on during overlapping periods, and the overlapping periods may be selected to achieve maximum efficiency. With the voltage- fed output, the primary switches are both turned off during overlapping periods. Additional leakage or parasitic inductance may be added to the circuit to accommodate an overlap period.
In one embodiment, a signal controlling a controlled rectifier is derived with a capacitive divider circuit. A circuit may determine the DC component of the signal controlling the controlled rectifier, and the DC component of the signal may be adjusted to provide regulation.
In accordance with another aspect of the invention, an ORing controlled rectifier connects the converter's output to an output bus to which multiple converter outputs are coupled, and the ORing controlled rectifier is turned off if the power converter fails. Preferably, the signal controlling the ORing controlled rectifier is derived from one or more secondary windings. The ORing controlled rectifier is turned on when the converter's output voltage approximately matches the bus voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views.
The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
Figure 1 is a block diagram illustrating a preferred embodiment of the invention.
Figure 2 is a schematic of an embodiment of the invention with synchronous rectifiers replaced by diodes. Figure 3 is an illustration of a preferred embodiment of the invention with the controlled rectifiers and parallel uncontrolled rectifiers illustrated.
Figure 4 illustrates an alternative location of the synchronous rectifiers in the circuit of Figure 3. Figure 5 illustrates the circuit of Figure 3 with important parasitic capacitances and inductances illustrated. Figure 6A illustrates another embodiment of the invention with the tertiary winding connected to the primary side.
Figure 6B illustrates another embodiment of the invention with a voltage fed isolation stage.
Figure 7 illustrates a secondary circuit having capacitive dividers to divide the voltages applied to the control terminals of the controlled rectifiers.
Figure 8 shows an alternative embodiment in which the output is regulated by controlling the voltage applied to the control terminals of the controlled rectifiers.
Figure 9 illustrates an embodiment of the invention in which the primary windings are tightly coupled.
Figure 10 illustrates the use of an ORing controlled rectifier to couple the power converter to an output bus.
DETAILED DESCRIPTION OF THE INVENTION
One embodiment of the invention described herein pertains to an electrically isolated DC-DC converter that might be used to deliver power at a low DC voltage (e.g. 5 volts) from a DC source such as a battery or a rectified utility. In such a converter a transformer is used to provide the electrical isolation and to provide a step-down (or step-up) in voltage level according to its turns-ratio. Switches in the form of power semiconductor transistors and diodes are used in conjunction with capacitors and inductors to create the conversion. A control circuit is typically included to provide the drive signals to the transistors' control terminals. When the switching frequency is high (e.g. 100 kHz and above) it is typical today to use power MOSFETs and Schottky diodes for the converter's switches since these majority carrier devices can undergo faster switch transitions than minority carrier devices such as power bipolar transistors and bipolar diodes.
Most DC-DC converters are designed to provide regulation of their output voltage in the face of input voltage and output current variations. For example, a converter might need to maintain a 5 volt output (plus or minus a few percent) as its input varies over the range of 36 to 75 volts and its output current ranges from 1 to 25 amps. This ability to provide regulation is usually the result of the power circuit's topology and the manner in which its switching devices are controlled. Sometimes the regulation function is supplied by (or augmented with) a linear regulator.
Figure 1 shows a block diagram of a DC-DC converter that represents one embodiment of the invention. It shows a two stage converter structure where the power first flows through one stage and then through the next . One stage provides the regulation function and the other provides the electrical isolation and/or step-down (or step-up) function. In this embodiment the regulation stage is situated before the isolation stage, but this ordering is not necessary for the invention. Notice also that the block diagram shows a control function. As mentioned, the purpose of this control function is to determine when the transistors in the power circuit will be turned on and off (or to determine the drive of a linear regulator) . To aid in this function the control circuit typically senses voltages and currents at the input, at the output, and/or within the power circuit.
Figure 2 shows one way to implement the two power stages represented in the block diagram of Figure 1. In this figure diodes, rather than synchronous rectifiers, are used to simplify the initial description of the circuit's operation. The topology of the regulation stage is that of a "down converter" . This canonical switching cell has a capacitor, CIN, a transistor, QR, a diode, DR, and an inductor, L. Regulation is by control of the duty cycle of the transistor QR in response to one or more parameters sensed in the circuit. In a well known manner the regulation stage can be modified by providing higher order filters at its input and output, by replacing the diode with a synchronous rectifier, by adding resonant elements to create a "multi-resonant" converter and the like.
The topology of the isolation stage shown in Figure 2 has two transformers that are not, in this case, coupled. Each of these transformers Tl and T2 has three windings: a primary winding TlPRι , T2PRI ; a secondary winding T1SEC, T2ΞEC; and a tertiary winding T1TER,T2TER. The transformer windings are connected through MOSFETs Ql and Q2 on the primary windings and through diodes Dl, D2 , D3 , and D4 on the secondary and tertiary windings. The stage is "current- fed" , in this case by the inductor L from the output of the regulation stage. By this it is meant that the current flowing into the primary side of the isolation stage is held relatively constant over the time frame of the switching cycle. It also means that the voltage across the primary side of the isolation stage is free to have large, high frequency components. The output filter is simply a capacitor Couτ whose voltage is relatively constant over the time frame of the switching cycle. Additional filtering stages could be added to this output filter in a known manner .
The operation of the isolation stage proceeds in the following manner. First, for approximately one half of the switching cycle, transistor Ql is on and Q2 is off. The current flowing through inductor L therefore flows through the primary winding of transformer Tl , and a corresponding current (transformed by the turns ratio) flows through the secondary winding of Tl and through diode Dl to the output filter capacitor Couτ and the load. During this time the magnetizing current in Tl is increasing due to the positive voltage placed across its windings. This positive voltage is determined by the output capacitor voltage, Vouτ, plus the forward voltage drop of Dl .
During the second half of the switching cycle, transistor Q2 and diode D2 are on and Ql and Dl are off. While the current of inductor L flows through transformer T2 in the same manner as described above for Tl, the magnetizing current of transformer Tl flows through its tertiary winding and diode D3 to the output filter capacitor, Couτ. This arrangement of the tertiary winding provides a means to reset the Tl transformer core with a negative voltage and to recover most of the magnetizing inductance energy. The tertiary winding may alternatively be connected to other suitable points in the power circuit, including those on the primary side of the transformer. Other techniques for resetting the core and/or for recovering the magnetizing energy are known in the art and may be used here. In particular, the tertiary winding could be eliminated and replaced with a conventional clamp circuit attached to either the primary or secondary winding and designed to impose a negative voltage across the transformer during its operative half cycle. Techniques to recover the energy delivered to this clamp circuit, such as the one in which a transistor is placed in anti-parallel with a clamping diode so that energy can flow from the clamping circuitry back into the magnetizing inductance, could also be used.
Notice that because the isolation stage of Figure 2 is fed by an inductor (L) , it is important to make sure there is at least one path through which the current in this inductor can flow. At the transitions between each half cycle, it is therefore typical to turn on the new primary side transistor (say Q2) before turning off the old primary side transistor (say Ql) . The time when both transistors are on will be referred to as an overlap interval.
In a conventional current-fed push-pull topology where all the transformer windings are coupled on a single core, turning on both primary-side transistors will cause the voltage across the transformer windings to drop to zero, the output diodes to turn off, and the power to stop flowing through the isolation stage.
Here, however, since two separate, uncoupled transformers are used, the voltage across the transformer windings does not have to collapse to zero when both Ql and Q2 are on. Instead, both of the output diodes Dl and D2 turn on, both transformers have a voltage across them determined by the output voltage, and the current of inductor L splits (not necessarily equally) between the two halves of the isolation stage. The power flow through the isolation stage is therefore not interrupted (except to charge/discharge parasitic capacitances and inductances) . This means the output filter (Couτ) can be made much smaller and simpler than would otherwise be necessary. It also means that the isolation stage does not impose a large fundamental frequency voltage ripple across the inductor (L) which provides its current-fed input characteristic.
After an appropriate amount of overlap time has elapsed, the old primary side transistor (say Ql) is turned off. The voltage across this transistor rises as its parasitic capacitance is charged by the current that had been flowing through the channel. Once this voltage rises high enough to forward bias diode D3 connected to the tertiary winding, the transistor voltage becomes clamped, although an over-ring and/or a commutation interval will occur due to parasitic leakage inductance. Eventually, all of the current in inductor L will flow through switch Q2 , switch Ql will be off, and the magnetizing current of Tl will flow through diode D3.
Now replace output diodes Dl and D2 with MOSFET synchronous rectifiers Q3 and Q4 , as shown in Figure 3.
Note that in this and later figures, the body diode of the MOSFET synchronous rectifier is explicitly shown since it plays a role in the circuit's operation. More generally, the schematical drawings of Q3 and Q4 depict the need for a controlled rectifier (e.g. a transistor) and an uncontrolled rectifier (e.g. a diode) connected in parallel. These two devices may be monolithically integrated, as they are for power MOSFETs, or they may be separate components. The positions of these synchronous rectifiers m the circuit are slightly different than the positions of the diodes m Figure 2. They are still in series with their respective secondary windings, but are connected to the minus output terminal rather than the positive output terminal. This is done to have the sources of both N-channel MOSFETs connected to a single, DC node. If P-channel MOSFETs are to be used, their position m the circuit would be as shown m the partial schematic of Figure 4. This position permits the P-channel devices to also have their sources connected to a single, DC node. As shown in Figure 3, the gates of the synchronous rectifier MOSFETs are cross-coupled to the opposite transformers. With this connection, the voltage across one transformer determines the gate voltage, and therefore the conduction state (on or off) of the MOSFET connected to the other transformer, and vice versa. These connections therefore provide properly timed drives to the gates of the MOSFETs without the need for special secondary side control circuitry.
For instance, during the half cycle m which transistor Ql is turned on and transistor Q2 is off, the current of inductor L flows into the primary of Tl and out its secondary. This secondary side current will flow through transistor Q3 (note that even if Q3 ' s channel is not turned on, the secondary side current will flow through the transistor's internal anti-parallel body diode). The voltage across transformer Tl ' s secondary winding is therefore positive, and equal to the output voltage Vouτ plus the voltage drop across Q3. The voltage across T2 ' s secondary winding is negative during this time, with a magnitude approximately equal to the output voltage if the magnetizing inductance reset circuitry takes approximately the whole half cycle to finish its reset function. (The negative secondary winding voltage may be made greater than the positive voltage so that the core, will finish its reset before the next half cycle begins. This could be accomplished, for example, by using less turns on the tertiary winding.)
Referring to Figure 3, the voltage at node A during this state of operation is nearly zero with respect to the indicated secondary-side ground node (actually the voltage is slightly negative due to the drop across Q3) . The voltage at node B, on the other hand, is, following our example, approximately twice the output voltage (say 10 volts for a 5 volt output) . Given the way these nodes are connected to the synchronous rectifier transistors, Q3 is turned on and Q4 is turned off. These respective conduction states are consistent with transformer Tl delivering the power and transformer T2 being reset.
In the second half-cycle when Q2 is on and Ql is off, the voltage at node B will be nearly zero (causing Q3 to be off) and the voltage at node A will be approximately twice the output voltage (causing Q4 to be on) .
During the transition from one half-cycle to the next, the sequence of operation is as follows. Start with Ql and Q3 on, Q2 and Q4 off. (The clamp circuit's diode D4 may still be on, or it may have stopped conducting at this point if the magnetizing inductance has finished resetting to zero.) First, Q2 is turned on. If we ignore the effects of parasitic capacitances and inductances, the voltage across T2 steps from a negative value to a positive value. The current flowing through inductor L splits between the two primary windings, causing current to flow out of both secondary windings. These secondary currents flow through Q3 and Q4. Since the voltages at both node A and node B are now nearly zero, Q3 , which was on, will now be off, and Q4 will remain off (or more precisely, the channels of these two devices are off) . The secondary side currents therefore flow through the body diodes of Q3 and Q4. At the end of the overlap interval, Ql is turned off. The current stops flowing through transformer Tl , the body diode of Q3 turns off, and the voltage at node A rises from nearly zero to approximately twice the output voltage as Tl begins its reset half-cycle. With node A voltage high, the channel of transistor Q4 turns on, and the secondary side current of transformer T2 commutates from the body diode of Q4 to its channel.
Notice that during the overlap interval, the secondary side currents flow through the body diodes of transistors Q3 and Q4 , not their channels. Since these diodes have a high on-state voltage (about 0.9V) compared to the on-state voltage of the channel when the gate-source voltage is high, a much higher power dissipation occurs during this interval . It is therefore desirable to keep the overlap interval short compared to the period of the cycle. Notice also the benefit of using two, uncoupled transformers. The voltage across a first transformer can be changed, causing the channel of the MOSFET synchronous rectifier transistor connected to a second transformer to be turned off, before the voltage across the second transformer is made to change. This could not be done if both primary and both secondary windings were tightly coupled in the same transformer, since the voltages across all the windings would have to change together. Figure 5 shows the same topology as Figure 3, but with several important parasitic capacitances and inductances indicated schematically. Each indicated capacitor (C3 and C4) represents the combined effect of one synchronous rectifier's input capacitance and the other rectifier's output capacitance, as well as other parasitic capacitances. Each indicated inductor (LP1 and LP2) represents the combined effect of a transformer leakage inductance and the parasitic inductance associated with the loops formed by the primary side components and the secondary side components. These elements store significant energy that is dissipated each switching cycle in many prior art power circuits where diodes are replaced with synchronous rectifiers. Here, however, the energy stored in these parasitic components is nearly losslessly delivered to and recovered from them. By nearly lossless it is meant that no more than approximately 30% of the energy is dissipated. With one implementation of the present invention, less than 10% dissipation is obtained.
The nearly lossless delivery and recovery of energy is achieved because the circuit topology permits the synchronous rectifier switch transitions to proceed as oscillations between inductors and capacitors. These transitions are short compared to the overall on-state and off-state portions of the switching cycle (e.g. less than 20% of the time is taken up by the transition) . This characteristic of nearly lossless and relatively short transitions, which we will call soft switching, is distinct from that used in full resonant, quasi -resonant , or multi- resonant converters where the oscillations last for a large portion, if not all, of the on-state and/or off-state time. The way in which the soft-switching characteristic is achieved can be understood in the following manner. Start with transistors Ql and Q3 on, Q2 and Q4 off. The voltage at node A, and therefore the voltage across C4 , is nearly zero and the voltage at node B (and across C3 ) is approximately twice the output voltage. The current flowing through inductor L, IL, is flowing into the primary winding of Tl . The current flowing out of the secondary winding of Tl is I_ minus the current flowing in Tl ' s magnetizing inductance, IM, both referenced to the secondary side. The magnetizing current is increasing towards its maximum value, IMPK, which it reaches at the end of the half cycle.
When Q2 is turned on at the end of the half cycle, the voltage across both windings of both transformers steps to zero volts in the circuit model depicted in Figure 5. An L-C oscillatory ring ensues between capacitor C3 and the series combination of the two parasitic inductances, Lpl and LP2. If we assume the parasitic capacitances and inductances are linear, the voltage across C3 decreases - l i
cosinusoidally toward zero while the current flowing out of the dotted end of T2 ' s secondary winding, ILP2, builds up sinusoidally toward a peak determined by the initial voltage across C3 divided by the characteristic impedance
Figure imgf000020_0001
Note that the current flowing out of the dotted end of Tl ' s secondary winding, ILP1, decreases by the same amount that ILP2 increases such that the sum of the two currents is (IL - IMPK) , referenced to the secondary side. Also note that during this part of the transition, the voltages across both transformers' secondary windings will be approximately the output voltage minus half the voltage across C3. As the oscillation ensues, therefore, the transformer winding voltages, which started at zero, build up toward the output voltage.
The oscillation described above will continue until either the current ILP2 reaches (IL - IMPK) or the voltages across C3 reaches zero. The first scenario occurs for lower values of (IL - IMPK) and the second occurs for higher values of this current.
If ILP2 reaches (IL - IMPK) first (and assuming the voltage across C3 has fallen below the threshold voltage of Q3 so that ILP1 is flowing through the body diode of Q3 ) , the oscillation stops because the body diode will not let ILP1 go negative. ILP2 and ILP1 will hold constant at (IL - IMPK) and zero, respectively. Whatever voltage remains across C3 will then discharge linearly due to the current ILP2 until the body diode of Q4 turns on. The body diode will then carry ILP2 until the overlap interval is over and Ql is turned off.
When Ql is turned off, the magnetizing current IMPK will charge the parallel capacitance of C4 and Cl , the parasitic output capacitance of Ql, until the voltage across them is high enough to forward bias the clamping diode D3. At this point the reset portion of Tl ' s cycle commences .
Notice that for this first scenario, the complete transition is accomplished with portions of oscillatory rings that, to first order, are lossless. (Some loss does occur due to parasitic series resistance, but this is generally less than 20% of the total energy and typically around 5%.) It could be said that the energy that had been stored in LP1 has been transferred to Lp2, and that the energy that had been stored in C3 has been transferred to C4.
If, on the other hand, the voltage across C3 reaches zero (or, more precisely, a diode drop negative) first, then the body diode of Q4 will turn on and prevent this voltage from ringing further negative. The currents ILP1 and ILP2 (which are flowing through the body diodes of Q3 and Q4) will hold constant until the overlap interval is over and Ql is turned off. Once Ql is turned off, an oscillation ensues between Lpl and Cl . This oscillation is driven by the current remaining in LP1 when Ql was turned off. Given typical parameter values, this oscillation will continue until ILP1 reaches zero, at which point the body diode of Q3 will turn off. Finally, the magnetizing current IMPK charges up the parallel combination of C4 and Cl until the clamping diode D3 turns on to start the reset half-cycle.
Notice that for this second scenario, the transition is almost accomplished in a (to first order) lossless manner. Some loss does occur because in the final portion of the transition the voltages across C4 and Cl do not start out equal. Cl has already been partially charged whereas C4 is still at zero volts. As these capacitor voltages equalize, an energy will be lost. This lost energy is a small fraction (typically less than one third) of the energy stored in Cl before the equalization occurs. The energy stored in Cl equals the energy stored in ILP1 when Ql was turned off, which itself is a small fraction (typically less than one third) of the energy that was stored in this parasitic inductance when it was carrying the full load current, (IL - IM) . As such, the energy lost in this second scenario is a very small fraction (typically less than one ninth) of the total energy originally stored in (or delivered to) LP1, LP2, C3 and C4. In other words, most of the parasitic energy is recovered.
Note that since the second scenario has a small amount of loss, it may be desirable to avoid this scenario by adjusting component values. One approach would be to make C3 and C4 bigger by augmenting the parasitic capacitors with explicit capacitors placed in parallel. With large enough values it is possible to ensure that the first scenario described above holds true for the full range of load currents expected.
The descriptions given above for both scenarios must be modified to account for the nonlinear nature of capacitors C3 , C4 , and Cl , and also to account for the reverse recovery charge of the body diodes of Q3 and Q4. The details of the nonlinear waveforms are too complex to be described here, but the goal of recovering most of the parasitic energy is still achieved.
As mentioned previously, it is desirable to keep the overlap period as short as possible to minimize the time that the secondary currents are flowing through the body diodes of Q3 and Q4. It is also desirable to allow the energy recovering transitions just described to reach completion. These two competing desires can be traded off to determine an optimum overlap duration. In general, it is desirable to make sure the new primary switch is turned on before the old one is turned off, and that the portion of the half-cycle during which the uncontrolled rectifiers are conducting should, for efficiency sake, be less than 20%. Note that due to delays in the gate drive circuitry it is possible for the overlap interval to appear negative at some point in the control circuit. The size of the output filter required to achieve a given output voltage ripple is affected by the AC ripple in the current of inductor L. This ripple current is largely caused by the switching action of the preregulation stage. A larger inductance, or a higher order filter for the output of the regulation stage, as shown in Figure 6 where inductor LB and capacitor CB have been added, will reduce this ripple current.
The required size of the output filter is also affected by the AC ripple currents flowing in the magnetizing inductances of the transformers. Making these inductances as large as possible to reduce their ripple currents is therefore desirable. It is also beneficial to connect the tertiary reset windings back to a suitable point on the primary side as shown in Figure 6A where they are connected to capacitor CB, rather than to connect them to the output filter, as shown in Figure 3. This alternative connection reduces by a factor of two the ripple current seen by the output filter due to the magnetizing inductance currents, compared to the connection shown in Figure 3, since these magnetizing currents no longer flow to the output capacitor during their respective reset half cycles.
The power converter circuits described so far have all had an isolation stage that is current fed. It is also possible to incorporate the invention with an isolation stage that is voltage fed. By "voltage fed" it is meant that the voltage across the primary side of the isolation stage is held relatively constant over the time frame of the switching cycle. Such a converter circuit is shown in Figure 6B where two uncoupled transformers are used.
The operation of the voltage-fed isolation stage is slightly different than for a current -fed isolation stage. Each primary transistor is still turned on for approximately one half the cycle, but instead of providing a brief overlap period during which both primary transistors, Ql and Q2 , are turned on together, here the primary transistors are both turned off for a brief overlap period.
During each half cycle, the current flowing into one primary winding and out its respective secondary winding can be determined as follows. Say transistors Ql and Q3 have just been turned on to begin a new half cycle. At the completion of their switch transition they will be carrying some initial current (to be discussed in more detail below) . There is also a difference between the voltage across capacitor CB and the voltage across capacitor Couτ, both reflected to the secondary side. This voltage differential will be called ΔV. It appears across the series circuit composed of the leakage/parasitic inductances and resistances of the primary and secondary windings, T1PRI and T1SEC, the transistors Ql and Q3 , and the capacitors CB and Couτ. The current flowing through this series L-R circuit responds to the voltage across it, ΔV, in accordance with the component values, all referenced to the secondary side.
Since CB and Couτ are charged and discharged throughout the half cycle, ΔV will vary. But if we assume ΔV is relatively constant, then the current flowing through the series L-R circuit will change exponentially with an L/R time constant. If this time constant is long compared to the duration of the half cycle, then the current will have a linearly ramping shape. If the time constant is short, that the current will quickly reach a steady value determined by the resistance. To understand the switch transitions that occur between each half cycle, consider the leakage/parasitic inductances, Lpl and Lp2, and the capacitances associated with the controlled rectifiers, C3 and C4 , to be modeled in the same way as was shown in Figure 5. Assume Q2 and Q4 have been on and are carrying a final current level, IF, at the end of the half cycle. Transistor Ql is then turned on, causing the voltage VCB to be applied across primary winding T1PRI# and its reflected value across secondary winding T1SEC. An oscillation between C4 and Lpl will ensue, with the voltage across C4 starting at approximately twice the output voltage. After approximately one quarter of a cycle of this oscillation, the voltage across C4 will attempt to go negative and be clamped by the body diode of Q3. At this point the current flowing through Lpl will have reached a peak value, Is, determined by approximately twice the output voltage divided by the characteristic impedance, A_~ CΛ . This transition discharges capacitor C4 and builds up the current in Lpl to the value Is in a nearly lossless manner. During the quarter cycle of oscillation the voltage across the gate of transistor Q4 will drop below the threshold value for the device, and the channel of Q4 will turn off. The current that had been flowing through the channel will commutate to the body diode of Q4. At this point current if flowing through both transformers ' secondary windings and through the body diodes of Q3 and Q4. Q3 is carrying the current Is and Q4 is carrying the current 1- . Now transistor Q2 is turned off and its voltage rises as parasitic capacitors are losslessly charged until the voltage is clamped by the diode in series with the tertiary windings, T2TER. Inductor Lp2 now has a negative voltage across it and its current ILP2, will therefore linearly ramp down to zero as its energy is recovered back to CB through the clamping circuit. Once this current reaches zero, the body diode of Q4 will turn off and the current will become negative, but only to the point where it equals the second transform's magnetizing current, Im (reflected to the secondary side). This current will linearly charge capacitor C3 nearly losslessly as energy is delivered to the capacitor from the magnetizing inductance of the second transformer (reflected to the secondary side) . This current will linearly charge capacitor C3 nearly losslessly as energy is delivered to the capacitor from the mangetizing inductance of the second transformer.
As the voltage across C3 rises above the threshold value, transistor Q3 will turn on and the current that had been flowing through the body diode of Q3 will commutate to the channel of Q3. The new half cycle will then proceed as discussed above, with Is being the initial value of current mentioned in that discussion.
As with the current-fed isolation stage, the transition between the two half cycles has a period of time when the two body diodes are conducting. This condition is highly dissipative and should be kept short by keeping the overlap period that both primary side transistors, Ql and Q2 , are off short.
In all of the power converter circuits described above, it might be desirable to slow down the switch transitions in the isolation stage for many reasons. For instance, slower transitions might reduce the high frequency differential -mode and common-mode ripple components in the output voltage waveform. There are several ways the switch transitions might be slowed down. For instance, in a well known manner a resistor could be placed in series with the gate of the primary side transistor Ql (or Q2 ) in Figure 5 so that its gate voltage would change more slowly. Similarly, a resistor could be placed in series with the gate of a synchronous rectifier Q3 or (Q4) . In either case an RC circuit is created by the added resistor, R, and the capacitance, C, associated with the transistor. If this RC product is long compared to the normal length of the oscillatory transitions described above, the switch transitions will be slowed down. If the length of the switch transitions are on the order of \] { LC) or longer, where L is the leakage/parasitic inductance (LP1 and/or Lp2) that oscillates with the capacitor C4 (or C3 ) , then the nearly lossless transitions described above will not be achieved. The more the switch transitions are slowed down, the more the energy delivered to and/or recovered from the capacitors associated with the controlled rectifiers will be dissipated. As such, there is a tradeoff between the power converter's efficiency and its other attributes, such as output ripple content. This tradeoff might result in slower switch transitions in situations where high efficiency is not required or if better synchronous rectifiers in the future have much smaller capacitances.
As discussed above, the synchronous rectifier MOSFETs Q3 and Q4 in the circuit of Figure 3 are driven with a gate-source voltage equal to approximately twice the output voltage. For a 5 volt output, the 10 volt drive that results is appropriate for common MOSFETs. If the output voltage is such that the gate drive voltage is too large for the ratings of the MOSFET, however, steps must be taken to reduce the drive voltage. For example, if the output voltage is 15 volts, a 30 volt gate drive will result, and it is typically desired that the gate be driven to only 10 volts. Also, some MOSFETs are designed to be driven with only 5 volts, or less, at their gates.
Figure 7 shows one way to reduce the drive voltage while maintaining the energy recovery feature. The voltage waveform at node B (or at node A) is capacitively divided down by the series combination of capacitors C5 and C3 (or by C6 and C4 ) . The values of these capacitors are chosen to provide the division of the AC voltage provided at node B (or node A) as desired. For example, if node B has a 30 volt step change and a 10 volt step change is desired at the gate of Q3 , then C5 should have one half the capacitance of C3. Since C3 may be comprised of the parasitic capacitance of Q3 , it is likely to be nonlinear. In this case, an effective value of capacitance that relates the large scale change in charge to the large scale change in voltage should be used in the calculation to determine C5.
Since a capacitor divider only divides the AC components of a waveform, additional components need to be added to determine the DC component of the voltage applied to the gates of Q3 and Q4. Figure 7 shows one way to do this in which two resistors, Rl and R2 (or R3 and R4) , provide the correct division of the DC component of the voltage at node B (or node A) . These resistors should have values large enough to keep their dissipation reasonably small. On the other hand, the resistors should be small enough such that the time constant of the combined capacitor/resistor divider is short enough to respond to transients such as start-up.
Other techniques employing diodes or zener diodes that are known in the art could be used instead of the resistor technique shown in Figure 7.
One variation of the invention described herein would be to create a power supply with multiple outputs by having more than one secondary winding on each transformer in the isolation stage. For example, by using two secondary windings with the same number of turns it would be possible to create a positive 12 volt output and a negative 12 volt output. If the two secondary windings have a different number of turns it would be possible to create two output voltages of different magnitudes (e.g., 5 volts and 3.3 volts) . Another approach for creating multiple outputs would be to have multiple isolation stages, each with a turns -ratio appropriate for their respective output voltages .
When multiple outputs are provided in this manner, a phenomenon commonly called cross-regulation occurs. A single regulation stage cannot control the various output voltages independently, and these output voltages depend not just on the relative turns ratios, but also on the voltage drops that result as the various output currents flow through the impedances of their various output paths. A change in any one or more output currents therefore causes a change in the voltages of those outputs that are not used for feedback to the regulation stage. If this variation due to changes in output currents is a problem, then various approaches for providing regulation of the uncontrolled outputs can be provided. For example, a linear regulator might be added to each output that is not otherwise regulated.
One advantageous approach to providing linear regulation with the power circuits described here is to control how much the synchronous rectifier MOSFETs are turned on during their conduction state. This can be done by adding circuitry to limit the peak voltage to which their gates will be driven so that their on-state resistances can be made larger than their minimum values.
It can also be done by controlling the portion of operative half cycle during which a MOSFET 's gate voltage is allowed to be high so that the MOSFET 's body diode conducts for the rest of the time. With both techniques, the amount to which the output voltage can be regulated is the difference between the voltage drop of the synchronous rectifiers when their channels are fully on (i.e., when they are at their minimum resistance) and when only their body diodes are carrying the current . One way to accomplish the first technique, that of controlling the peak gate voltage, is to use the basic capacitor divider circuit that was shown in Figure 7. All that is needed is to make the resistor divider ratio, (or, alternatively, the diode clamping voltage if such an approach is chosen) dependent on a control signal derived from the error in the output voltage compared to its desired value. The goal is to shift the DC component of the gate voltage in response to the error signal such that the peak voltage applied to the gate, and therefore the on- state resistance and voltage of the synchronous rectifier, helps to minimize this error. Various control circuitry schemes that might be used to achieve this goal will be obvious to one skilled in the art. Note that this approach preserves the energy recovery feature of the gate drive. Note also that if the voltages at nodes A and B are such that no AC division is desired, then C5 and C6 should be made large compared to C3 and C4.
Figure 8 shows an alternative method to control the DC component of the gate voltage waveform. The output voltage (or a scaled version of it) is subtracted from a reference voltage and the error is multipled by the gain of an op-amp circuit. The output of the op-amp (node C) is then connected to the synchronous rectifier gates through resistors that are large enough to not significantly alter the AC waveforms at the gates. With this connection, the DC components of the gate voltages will equal the output voltage of the op-amp at node C. If the gain of the op-amp circuit is large enough, such as when an integrator is used, the error in the output voltage will be driven toward zero. ZF and Zx are impedances that should be chosen, with well established techniques, to ensure stability of this feedback loop while providing the gain desired.
The range of voltage required at the output of the op- amp depends on the particular application, and it may include negative values. This range influences the supply voltage requirements for the op-amp. Also, if the op-amp's output voltage gets too high, the synchronous rectifiers may not turn off when they are supposed to. Some means of limiting this voltage, such as a clamp circuit, may therefore be desirable. One way to accomplish the second technique, that of controlling the portion of the half cycle in which the MOSFET is gated on, is to place a low power switch network between the gate of Q3 (or Q4) , node B (or node A) , and ground. This network (composed, say, of analog switches operated with digital control signals) might be used to keep the gate voltage grounded for some period of time after the node voltage increases, and to then connect the gate to node B (or A) for the remainder of the half cycle with a switch capable of bidirectional current flow. The length of the delay would be based on a signal derived from the error in the output voltage. With this approach, the energy recovery feature associated with discharging each synchronous rectifier's gate capacitance is preserved, but the charging transition will become lossy. Alternatively, the switch network could be controlled to start out the half cycle with the gate connected to node B (or A) , and then after some delay to connect the gate to ground.
Using a synchronous rectifier to provide regulation as well as rectification, as described above, is not limited to multiple-output situations. It can also be used in single-output situations either as the total regulation stage or as an additional regulation stage to augment the first one. It is also possible to use DC-DC switching regulators on the secondary side to achieve the additional regulation desired, or to create more than one output voltage from any of the outputs of the isolation stage.
With multiple outputs it is not necessary for the gate of each controlled rectifier to be connected to secondary winding of the other transformer which corresponds to the same output. For instance, if the two outputs are 5 volts and 3.3 volts, the gates of the 3.3 volts output controlled rectifiers could be connected to the 5 volt output secondary windings. Doing so would give these controlled rectifiers a 10 volt gate drive, resulting in a lower on- state resistance than if they had a 6.6 volt gate drive.
In some situations, it may be desirable to place the isolation stage first in the power flow, and to have the regulation stage follow. For example, when there are many outputs sharing the total power, the circuit might be configured as one isolation/step-down (or step-up) stage followed by several DC-DC switching or linear regulators.
No matter where the isolation stage is situated, if it is to be current fed this requirement could be met with active circuitry as well as by a passive component such as an inductor. For instance, if the current fed isolation stage follows a regulation stage that is achieved with a linear regulator, then this linear regulator could be designed to have a large AC output impedance to achieve the input requirement of the current fed isolation stage. When the regulation stage precedes the isolation stage, it is not necessary to sense the isolated output voltage to control the regulation. An alternative approach is to sense the voltage on the primary side of the isolation stage, which may eliminate the need for secondary side circuitry and the need to bridge the feedback control signal across the isolation barrier.
For example, in Figure 6 the voltage across CB, the capacitor of the third-order output filter of the down converter, could be used. This voltage nearly represents the isolated output voltage (corrected for the turns- ratio) . It differs only due to the resistive (and parasitic inductance commutation) drops between CB and the output. Since these drops are small and proportional to the current flowing through the isolation stage, the error in output voltage they create can either be tolerated or corrected.
To correct the error, the current on the primary side could be sensed, multiplied by an appropriate gain, and the result used to modify the reference voltage to which the voltage across CB is compared. Since these resistive drops vary with temperature, it might also be desirable to include temperature compensation in the control circuitry. Note that this approach could also be used to correct for resistive drops along the leads connecting the supply's output to its load.
The embodiments of the invention described above have used two uncoupled transformers for the isolation stage. It is also possible, as shown in Figure 9, to use a single transformer T in which, for example, there are two primary windings TPRI1,TPRI2 and two secondary windings, TSEC1, TSEC2. While the two primary windings may be tightly coupled, either the two secondaries should be loosely coupled to each other or the connections to the output capacitors and synchronous rectifier transistors should provide adequate parasitic inductance. The resulting leakage and parasitic inductance on the secondary side can then be modeled as is shown in Figure 9. With this inductance present in the secondary side loops, the operation of the coupled isolation stage during the overlap period is similar to what was described above for the uncoupled case. With Ql and Q3 on, turn Q2 on. The voltage across the transformer windings, as modeled in Figure 9, drops to zero, which is consistent with what must happen if the primary windings are tightly coupled. A nearly-lossless energy saving transition involving inductor/capacitor oscillations and linear discharges then ensues.
What is different here is that the overlap period during which both Ql and Q2 are on cannot last too long. If the overlap lasts too long, the transient waveforms will settle into a state where the voltages at nodes A and B rise to the output voltage. If this voltage is higher than the gates' threshold levels, transistors Q3 and Q4 will partially turn on. A large amount of energy will then be dissipated while this state persists, and it is possible for the output capacitor to be significantly discharged. These problems can be avoided by making sure the overlap period when both Ql and Q2 are on does not last too long. For a given converter, an overlap period can be found which will give the highest converter efficiency. The more leakage/parasitic inductance there is, the longer an overlap period that can be tolerated. Based on the overlap time provided by a given control circuit, it may become necessary to add additional inductance by increasing the leakage or parasitic inductance.
With a coupled transformer it is not necessary to provide a separate reset circuit (whether it uses a tertiary winding or not) since the magnetizing current always has a path through which it can flow. With a coupled transformer it is necessary to keep the lengths of the two halves of the cycle well balanced to avoid imposing an average voltage across the core and driving it into saturation. Several techniques for balancing the two half cycles are well known in the art.
When two or more power supplies are connected in parallel, diodes are sometimes placed in series with each supply's output to avoid a situation where one supply's failure, seen as a short at its output, takes down the entire output bus. These "ORing" diodes typically dissipate a significant amount of energy. One way to reduce this dissipation is to replace the diode with a MOSFET having a lower on-state voltage. This "ORing" synchronous rectifier MOSFET can be placed in either output lead, with its body diode pointing in the direction of the output current flow.
With the invention described here, the voltage for driving the gate of this MOSFET, Q5 , can be derived by connecting diodes to node A and/or node B (or to nodes of capacitor dividers connected to these nodes) , as shown in Figure 10. These diodes rectify the switching waveforms at node A and/or node B to give a constant voltage suitable for turning on the ORing MOSFET at node D. A filter capacitor, CF, might be added to the circuit as shown in the figure, or the parasitic input capacitance of the ORing MOSFET might be used alone. A resistor RF ensures the gate voltage discharges when the drive is removed. If the power supply fails in a way that creates a short at its output, such as when a synchronous rectifier shorts, the voltages at nodes A and B will also be shorted' after the transient is complete. With its gate drive no longer supplied, the ORing MOSFET will turn off, and the failed supply will be disconnected from the output bus.
When two (or more) power supplies of the type described here are placed in parallel, a problem can arise. If one power supply is turned on while another is left off (i.e. not switching), the output bus voltage generated by the first supply will appear at the gates of the second supply's synchronous rectifiers. Once this voltage rises above the threshold value, these synchronous rectifiers will turn on and draw current. At the least this will result in extra dissipation, but it could result in a shorted output bus. This problem can occur even if both supplies are turned on and off together if one supply's transition "gets ahead" of the other.
There are several approaches to solving this problem. One is to make sure both supplies have matched transitions. Another is to connect the supplies together with ORing diodes so that no supply can draw current from the combined output bus. If an ORing MOSFET is used instead of an ORing diode, however, this second approach can still fail to solve the problem. For instance, consider the case where a supply drives its ORing MOSFET with the technique shown in Figure 10. Assume the bus voltage is already high due to another supply, and the first supply is then turned on in a way that causes its output voltage to rise slowly toward its desired value. If the ORing MOSFET 's gate voltage rises high enough to turn it on before the newly rising output voltage approximately matches the existing bus voltage, then there will be at least a momentary large current flow as the two voltages equalize. To avoid this problem additional circuitry can be added to make sure an ORing MOSFET is not turned on until its supply's output voltage has approximately reached the bus voltage. This might be done by sensing the two voltages and taking appropriate action, or it might be done by providing a delay between when the ORing MOSFET 's gate drive is made available and when it is actually applied to the gate. Such a delay should only affect the turn-on, however; the turn-off of the ORing MOSFET should have minimal delay so that the protective function of the transistor can be provided.
While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Those skilled in the art will recognize or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention described specifically herein. Such equivalents are intended to be encompassed in the scope of the claims. For instance, the regulation stage could be composed of an up-converter . The ideas that have been presented in terms of the N-channel implementation of the synchronous rectifier MOSFET can be modified to apply to the P-channel implementation, as well. The components shown in the schematics of the figures (such as Q3 in Figure 3) could be implemented with several discrete parts connected in parallel. In addition, certain aspects of the invention could be applied to a power converter having only one primary transformer winding and/or one secondary transformer winding.

Claims

CLAIMSWhat is claimed is:
1. A power converter comprising: a power source; a primary transformer winding circuit having at least one primary winding connected to the source; a secondary transformer winding circuit having at least one secondary winding coupled to the at least one primary winding; plural controlled rectifiers, each having a parallel uncontrolled rectifier and each connected to a secondary winding, each controlled rectifier being turned on and off in synchronization with the voltage waveform across a primary winding to provide an output, each primary winding having a voltage waveform with a fixed duty cycle and transition times which are short relative to the on-state and off-state times of the controlled rectifiers; and a regulator which regulates the output while the fixed duty cycle is maintained.
2. A power converter as claimed in claim 1 wherein the regulator is a regulation stage on the primary side of the converter.
3. A power converter as claimed in claim 2 wherein the regulation stage is part of the power source.
4. A power converter as claimed in claim 2 wherein power conversion is regulated in response to a variable sensed on the primary side of the converter.
5. A power converter as claimed in claim 1 wherein the regulator is a regulation stage on the secondary side of the converter.
6. A power converter as claimed in claim 5 wherein power conversion is regulated by control of the controlled rectifiers .
7. A power converter as claimed in claim 6 wherein the on-state voltage of a controlled rectifier is made larger than its minimum value to provide regulation.
8. A power converter as claimed in claim 6 wherein the on-state duration of a controlled rectifier is made shorter than its maximum value.
9. A power converter as claimed in claim 1 wherein the first and second controlled rectifiers are voltage controlled field effect transistors.
10. A power converter as claimed in claim 1 further comprising a reset circuit associated with a transformer for flow of magnetizing current.
11. A power converter as claimed in claim 10 wherein the energy stored in the magnetizing inductance is recovered.
12. A power converter as claimed in claim 10 wherein the reset circuit comprises a tertiary transformer winding.
13. A power converter as claimed in claim 10 wherein the reset circuit comprises a clamp.
14. A power converter as claimed in claim 1 wherein the power source has a current-fed output.
15. A power converter as claimed in claim 14 wherein the current-fed output characteristic of the power source is provided by an inductor.
16. A power converter as claimed in claim 1 wherein the power source has a voltage- fed output.
17. A power converter as claimed in claim 16 wherein the voltage fed output characteristic of the power source is provided by a capacitor.
18. A power converter as claimed in claim 1 wherein the signal controlling a controlled rectifier is provided by a transformer winding.
19. A power converter as claimed in claim 1 wherein a signal controlling a controlled rectifier is derived with a capacitive divider circuit.
20. A power converter as claimed in claim 19 further comprising a circuit to determine the dc component of the signal controlling a controlled rectifier.
21. A power converter as claimed in claim 20 wherein the dc component of the signal is adjusted to provide regulation.
22. A power converter as claimed in claim 1 further comprising a signal for controlling an ORing controlled rectifier that connects the converter's output to an output bus.
23. A power converter as claimed in claim 22 wherein the ORing controlled rectifier is turned off if the power converter fails.
24. A power converter as claimed in claim 22 wherein the signal controlling the ORing controlled rectifier is derived from one or more secondary windings .
25. A power converter as claimed in claim 22 wherein the ORing controlled rectifier is turned on when the converter's output voltage approximately matches the bus voltage.
26. A power converter as claimed in claim 1 wherein energy is nearly losslessly delivered to and recovered from capacitors associated with the controlled rectifiers.
27. A power converter as claimed in claim 1 wherein each controlled rectifier is turned on and off by a signal applied to a control terminal relative to a reference terminal of the controlled rectifier and the reference terminals of the controlled rectifiers are connected to a common node .
28. A power converter comprising: a power source; first and second primary transformer windings connected to the source; first and second primary switches in series with the first and second primary windings, respectively; first and second secondary transformer windings coupled to the first and second primary windings, respectively; first and second controlled rectifiers, each having a parallel uncontrolled rectifier, in series with the first and second secondary windings, respectively; and a controller which turns on the first and second primary switches in opposition, each for approximately one half of the switching cycle with transition times which are short relative to the on-state and off-state times of the first and second controlled rectifiers, the first and second controlled rectifiers being controlled to be on at substantially the same times that the first and second primary switches, respectively, are on.
29. A power converter as claimed in claim 28 further comprising a regulation stage.
30. A power converter as claimed in claim 28 wherein energy is nearly losslessly delivered to and recovered from capacitors associated with the first and second controlled rectifiers.
31. A power converter as claimed in claim 28 wherein the first primary and secondary transformer windings and the second primary and secondary transformer windings are on separate uncoupled transformers.
32. A power converter as claimed in claim 28 wherein the signal that controls a controlled rectifier is derived from the voltage at the connection between the other controlled rectifier and its associated secondary winding .
33. A power converter as claimed in claim 28 wherein the power source has a current fed output and the primary switches are both turned on during overlapping periods .
3,4. A power converter as claimed in claim 33 wherein the overlapping periods are selected to achieve maximum efficiency.
35. A power converter as claimed in claim 33 wherein additional leakage or parasitic inductance is added to the circuit to accommodate an overlap period.
36. A power converter as claimed in claim 28 wherein the power source has a voltage-fed output and the primary switches are both turned off during overlapping periods.
37. A power converter as claimed in claim 36 wherein the overlapping periods are selected to achieve maximum efficiency.
38. A power converter as claimed in claim 36 wherein additional leakage or parasitic inductance is added to the circuit to accommodate an overlap period.
39. A power converter as claimed in claim 28 wherein the two primary windings and two secondary windings are coupled on a single transformer.
40. A power converter as claimed in claim 28 wherein the first and second controlled rectifiers are controlled by signals derived from transformer windings coupled to the first and second primary transformer windings.
41. A power converter as claimed in claim 28 wherein the first controlled rectifier is controlled by a signal derived from the voltage of the second secondary winding and the second controlled rectifier is controlled by a signal derived from the voltage of the first secondary winding.
42. A power converter as claimed in claim 28 wherein each of the first and second controlled rectifiers is turned on and off by a signal applied to a control terminal relative to a reference terminal of the controlled rectifier and the reference terminals of the controlled rectifiers are connected to a common node .
43. A power converter comprising: means for converting power; means for providing a source of power to first and second primary transformer windings; means for controlling a voltage waveform across the first and second primary transformer windings with a fixed duty cycle; means for controlling first and second controlled rectifiers, each having a parallel uncontrolled rectifier, each controlled rectifier being turned on and off in synchronization with the voltage waveform across a primary winding over transitions times which are short relative to the on-state and off-state times of the controlled rectifiers; and means for regulating the output while the fixed duty cycle is maintained.
44. A method of converting power comprising: providing a source of power to first and second primary transformer windings; controlling a voltage waveform across the first and second primary transformer windings with a fixed duty cycle; controlling first and second controlled rectifiers, each having a parallel uncontrolled rectifier, each controlled rectifier being turned on and off in synchronization with the voltage waveform across a primary winding over transitions times which are short relative to the on-state and off-state times of the controlled rectifiers; and regulating the output while the fixed duty cycle is maintained.
45. A method as claimed in claim 44 wherein the source of power has a current fed output and the voltage waveforms on the first and second primary transformer windings are turned on during overlapping periods, each for approximately one half of a switching cycle.
46. A method as claimed in claim 45 wherein energy is nearly losslessly delivered to and recovered from capacitors associated with the controlled rectifiers.
47. A method as claimed in claim 46 wherein the first controlled rectifier is controlled by a signal derived from the voltage of the second secondary winding and the second controlled rectifier is controlled by a signal derived from the voltage of the first secondary winding .
48. A method as claimed in claim 47 wherein energy is nearly losslessly delivered to and recovered from capacitors associated with the controlled rectifiers.
49. A method as claimed in claim 48 wherein the first controlled rectifier is controlled by a signal derived from the voltage of the second secondary winding and the second controlled rectifier is controlled by a signal derived from the voltage of the first secondary winding.
50. A power converter comprising: a controlled rectifier; and a capacitive divider circuit, a signal controlling the controlled rectifier being derived from the capacitive divider circuit.
51. A power converter as claimed in claim 50 further comprising a circuit to determine the dc component of the signal controlling a controlled rectifier.
52. A power converter as claimed in claim 51 wherein the dc component of the signal is adjusted to provide regulation.
53. A power circuit comprising: a power converter; and an ORing controlled rectifier that connects the converter output to an output bus, the ORing controlled rectifier being controlled by a signal from the power converter.
54. A power converter as claimed in claim 53 wherein the ORing controlled rectifier is turned off if the power converter fails.
55. A power converter as claimed in claim 53 wherein the signal controlling the ORing controlled rectifier is derived from one or more secondary windings.
56. A power converter as claimed in claim 53 wherein the ORing controlled rectifier is turned on when the converter's output voltage approximately matches the bus voltage.
PCT/US1998/001498 1997-01-24 1998-01-23 High efficiency power converter WO1998033267A2 (en)

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EP98902723A EP0954899A2 (en) 1997-01-24 1998-01-23 High efficiency power converter
CA002278250A CA2278250A1 (en) 1997-01-24 1998-01-23 High efficiency power converter

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7119524B2 (en) 1999-07-07 2006-10-10 Bank America, N.A. Control of DC/DC converters having synchronous rectifiers
CN107851661A (en) * 2015-06-23 2018-03-27 Tm4股份有限公司 The physical topological structure of power converter
US11705820B2 (en) 2013-07-02 2023-07-18 Vicor Corporation Power distribution architecture with series-connected bus converter

Families Citing this family (150)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0954899A2 (en) * 1997-01-24 1999-11-10 Fische, LLC High efficiency power converter
US7269034B2 (en) 1997-01-24 2007-09-11 Synqor, Inc. High efficiency power converter
US7272021B2 (en) * 1997-01-24 2007-09-18 Synqor, Inc. Power converter with isolated and regulated stages
US7050309B2 (en) * 2002-12-06 2006-05-23 Synqor, Inc. Power converter with output inductance
US6441590B1 (en) * 1999-03-26 2002-08-27 Sarnoff Corporation Two stage architecture for a monitor power supply
US6594156B1 (en) * 2000-04-24 2003-07-15 Minimed Inc. Device and method for circuit protection during radiation sterilization
US6246592B1 (en) 1999-08-10 2001-06-12 Texas Instruments Incorporated Unique power supply architecture with cascaded converters for large input-to-output step-down ratio
US6169683B1 (en) * 1999-10-07 2001-01-02 Ericsson Inc. Resonant gate drive for synchronous rectifiers
US6442047B1 (en) 1999-10-08 2002-08-27 Lambda Electronics, Inc. Power conversion apparatus and methods with reduced current and voltage switching
US6961253B1 (en) 1999-10-08 2005-11-01 Lambda Electronics Drive circuits for synchronous rectifiers
US6370039B1 (en) 1999-11-19 2002-04-09 Iwatt Isolated power converter having primary feedback control
US6381150B2 (en) 1999-11-19 2002-04-30 Iwatt Isolated dual converter having primary side internal feedback for output regulation
US6304460B1 (en) * 2000-05-05 2001-10-16 Slobodan Cuk Switching DC-to-DC converter utilizing a soft switching technique
US6195270B1 (en) 2000-06-19 2001-02-27 Technical Witts, Inc. Self clamping zero voltage switching DC transformers
US6341073B1 (en) * 2000-11-16 2002-01-22 Philips Electronics North America Corporation Multiple valley controller for switching circuit
US6831847B2 (en) * 2000-11-20 2004-12-14 Artesyn Technologies, Inc. Synchronous rectifier drive circuit and power supply including same
US6570268B1 (en) 2000-11-20 2003-05-27 Artesyn Technologies, Inc. Synchronous rectifier drive circuit and power supply including same
US6400582B1 (en) 2000-11-21 2002-06-04 International Business Machines Corporation Dual forward power converter utilizing coupling capacitors for improved efficiency
US6437999B1 (en) * 2001-05-12 2002-08-20 Technical Witts, Inc. Power electronic circuits with ripple current cancellation
US6504735B2 (en) 2001-03-12 2003-01-07 02 Micro International Ltd. Regulated voltage reducing high-voltage isolated DC/DC converter system
EP1257048B1 (en) * 2001-05-09 2017-10-04 Philips Lighting Holding B.V. Regulation device for a resonant converter
GB2377823B (en) * 2001-06-15 2005-11-23 Marconi Applied Technologies Transformer/rectifier arrangement
US6445597B1 (en) 2001-06-28 2002-09-03 Tyco Electronics Logistics Ag Local loop control system for a multiple output power converter
US6442052B1 (en) 2001-08-30 2002-08-27 International Business Machines Corporation High efficiency power converter with fast transient response
US6927987B2 (en) * 2001-11-13 2005-08-09 Synqor, Inc. Half-bridge isolation stage topologies
WO2003061105A1 (en) * 2002-01-04 2003-07-24 Fujitsu Siemens Computers Gmbh Switched-mode power supply unit
US6937483B2 (en) * 2002-01-16 2005-08-30 Ballard Power Systems Corporation Device and method of commutation control for an isolated boost converter
US6975098B2 (en) * 2002-01-31 2005-12-13 Vlt, Inc. Factorized power architecture with point of load sine amplitude converters
US6930893B2 (en) * 2002-01-31 2005-08-16 Vlt, Inc. Factorized power architecture with point of load sine amplitude converters
US6781853B2 (en) * 2002-03-13 2004-08-24 Virginia Tech Intellectual Properties, Inc. Method and apparatus for reduction of energy loss due to body diode conduction in synchronous rectifiers
GB2393336B (en) * 2002-09-20 2005-07-20 Coutant Lambda Ltd Multi-resonant power conversion apparatus and methods
US7477529B2 (en) * 2002-11-01 2009-01-13 Honeywell International Inc. High-voltage power supply
NL1022226C2 (en) * 2002-12-20 2004-07-19 Leader Electronics Europ B V Device and method for converting an alternating voltage.
JP2004215376A (en) * 2002-12-27 2004-07-29 Sony Corp Switching power supply circuit
US7057906B2 (en) * 2003-03-11 2006-06-06 Denso Corporation Insulating switching DC/DC converter
CN100392963C (en) * 2003-04-17 2008-06-04 中兴通讯股份有限公司 Low voltage largecurrent modle power source
KR100510143B1 (en) * 2003-07-01 2005-08-25 삼성전자주식회사 Method for compensating power factor, appratus therefor and power supplyer thereof
JP2005110486A (en) * 2003-08-06 2005-04-21 Sony Corp Switching power circuit
US7872454B2 (en) * 2003-08-21 2011-01-18 Marvell World Trade Ltd. Digital low dropout regulator
EP1816734A3 (en) 2003-08-21 2007-11-21 Marvell World Trade Ltd. Voltage regulator
US7760525B2 (en) * 2003-08-21 2010-07-20 Marvell World Trade Ltd. Voltage regulator
US7102251B2 (en) 2003-08-22 2006-09-05 Distributed Power, Inc. Bi-directional multi-port inverter with high frequency link transformer
JP4439979B2 (en) * 2003-09-17 2010-03-24 太陽誘電株式会社 Power supply
US9153960B2 (en) 2004-01-15 2015-10-06 Comarco Wireless Technologies, Inc. Power supply equipment utilizing interchangeable tips to provide power and a data signal to electronic devices
US7149096B2 (en) * 2004-02-18 2006-12-12 Astec International Limited Power converter with interleaved topology
US7548441B2 (en) 2004-02-24 2009-06-16 Vlt, Inc. Universal AC adapter
US7170764B2 (en) * 2004-02-24 2007-01-30 Vlt, Inc. Adaptively configured voltage transformation module array
US7408795B2 (en) * 2004-02-24 2008-08-05 Vlt, Inc. Energy storage and hold-up method and apparatus for high density power conversion
US7782639B2 (en) * 2004-02-24 2010-08-24 Vlt, Inc. Adaptively configured and autoranging power converter arrays
US7212419B2 (en) * 2004-02-24 2007-05-01 Vlt, Inc. Adaptively configured and autoranging voltage transformation module arrays
US7561446B1 (en) 2005-09-15 2009-07-14 Vlt, Inc. Double-clamped ZVS buck-boost power converter
US8324872B2 (en) 2004-03-26 2012-12-04 Marvell World Trade, Ltd. Voltage regulator with coupled inductors having high coefficient of coupling
US7190152B2 (en) 2004-07-13 2007-03-13 Marvell World Trade Ltd. Closed-loop digital control system for a DC/DC converter
US7202646B2 (en) * 2004-08-02 2007-04-10 Vlt, Inc. Control interface with droop compensation
JP4403926B2 (en) * 2004-08-30 2010-01-27 サンケン電気株式会社 DC power supply
US20060043490A1 (en) * 2004-09-02 2006-03-02 Texas Instruments Incorporated Electrostatic discharge (ESD) detection and protection
US7531918B2 (en) * 2005-03-30 2009-05-12 Hewlett-Packard Development Company, L.P. Hot insertion and extraction of power supply module
US7272024B2 (en) * 2005-06-08 2007-09-18 Tamura Corporation Synchronized rectification circuit and switching power supply device
JP2006345641A (en) * 2005-06-09 2006-12-21 Toyota Industries Corp Dc/ac converter circuit and method for converting dc into ac
DE102006002698A1 (en) * 2006-01-19 2007-08-02 Conergy Ag Inverter circuit for mains supply and for mains-independent operation
US7554796B2 (en) 2006-01-20 2009-06-30 Adc Telecommunications, Inc. Modular power distribution system and methods
US20070211500A1 (en) * 2006-03-02 2007-09-13 Hipro Electronic Co., Ltd DC-DC converter with direct driven synchronous rectifier
WO2007105188A1 (en) * 2006-03-10 2007-09-20 Commergy Technologies Limited A power converter
US7787261B2 (en) * 2006-11-01 2010-08-31 Synqor, Inc. Intermediate bus architecture with a quasi-regulated bus converter
US8054652B2 (en) 2007-07-16 2011-11-08 Texas Instruments Incorporated Systems and methods for off-time control in a voltage converter
US7796406B2 (en) 2007-07-31 2010-09-14 Lumenis Ltd. Apparatus and method for high efficiency isolated power converter
EP2051360B1 (en) * 2007-10-17 2016-09-21 Power Systems Technologies GmbH Control circuit for a primary controlled switching power supply with increased accuracy of voltage regulation and primary controlled switched mode power supply
US8039989B2 (en) * 2007-11-27 2011-10-18 International Business Machines Corporation Apparatus, system, and method for a low cost multiple output redundant power supply
WO2009140404A2 (en) * 2008-05-13 2009-11-19 Igo , Inc. Circuit and method for ultra-low idle power
US8693213B2 (en) 2008-05-21 2014-04-08 Flextronics Ap, Llc Resonant power factor correction converter
US7779278B2 (en) * 2008-05-29 2010-08-17 Igo, Inc. Primary side control circuit and method for ultra-low idle power operation
US7770039B2 (en) * 2008-05-29 2010-08-03 iGo, Inc Primary side control circuit and method for ultra-low idle power operation
JP2010004633A (en) * 2008-06-19 2010-01-07 Sanken Electric Co Ltd Dc power supply apparatus
US7795759B2 (en) * 2008-06-27 2010-09-14 iGo, Inc Load condition controlled power strip
US7795760B2 (en) * 2008-07-25 2010-09-14 Igo, Inc. Load condition controlled power module
US7800252B2 (en) * 2008-06-27 2010-09-21 Igo, Inc. Load condition controlled wall plate outlet system
US8199529B2 (en) * 2008-09-04 2012-06-12 Astec International Limited Inductorless isolated power converters with zero voltage and zero current switching
CN101728389B (en) * 2008-10-29 2014-01-29 飞思卡尔半导体公司 Method for passively eliminating substrate noise in buck converter
WO2010078694A1 (en) * 2009-01-07 2010-07-15 Texas Instruments Incorporated Sweeping frequency llc resonant power regulator
JP5157987B2 (en) * 2009-03-25 2013-03-06 株式会社豊田自動織機 Isolated DC-DC converter
US8405456B2 (en) 2009-03-31 2013-03-26 Quantance, Inc. High speed power supply system
US9755630B2 (en) * 2009-04-30 2017-09-05 The United States of America as represented by the Secretary of the Government Solid-state circuit breakers and related circuits
US8787044B2 (en) * 2009-05-07 2014-07-22 Flextronics Ap, Llc Energy recovery snubber circuit for power converters
US8891803B2 (en) * 2009-06-23 2014-11-18 Flextronics Ap, Llc Notebook power supply with integrated subwoofer
US20110149613A1 (en) * 2009-12-23 2011-06-23 Comarco Wireless Technologies, Inc. Flyback converter utilizing boost inductor between ac source and bridge rectifier
DE102010000934A1 (en) * 2010-01-15 2011-07-21 Osram Gesellschaft mit beschränkter Haftung, 81543 rectifier
CN101741258B (en) * 2010-01-19 2012-05-09 魏其萃 Isolative current regulation type direct current-direct current converter
US20110216560A1 (en) * 2010-03-04 2011-09-08 Sheng Ye Two stage isolated switch-mode ac/dc converter
US8000118B1 (en) 2010-03-15 2011-08-16 Varentec Llc Method and system for delivering a controlled voltage
US8964413B2 (en) * 2010-04-22 2015-02-24 Flextronics Ap, Llc Two stage resonant converter enabling soft-switching in an isolated stage
US8456868B2 (en) * 2010-04-30 2013-06-04 Infineon Technologies Ag Controller for a resonant switched-mode power converter
US8665611B2 (en) 2010-04-30 2014-03-04 Infineon Technologies Ag Controller for a resonant switched-mode power converter
US8472221B1 (en) * 2010-05-07 2013-06-25 Alfred E. Mann Foundation For Scientific Research High voltage rectifier using low voltage CMOS process transistors
US8617154B2 (en) 2010-06-25 2013-12-31 Covidien Lp Current-fed push-pull converter with passive voltage clamp
CN103125068B (en) * 2010-07-30 2015-11-25 Abb技术有限公司 Based on the capacitor discharge in the voltage source converter of unit
JP5504129B2 (en) * 2010-10-18 2014-05-28 東芝テック株式会社 Power converter
TWI427887B (en) 2010-11-03 2014-02-21 Delta Electronics Inc High voltage power supply module and power supply system using the same
US9520772B2 (en) 2010-11-09 2016-12-13 Tdk-Lambda Corporation Multi-level voltage regulator system
US8520410B2 (en) 2010-11-09 2013-08-27 Flextronics Ap, Llc Virtual parametric high side MOSFET driver
US8934267B2 (en) 2010-11-09 2015-01-13 Tdk-Lambda Corporation Loosely regulated feedback control for high efficiency isolated DC-DC converters
US9118213B2 (en) 2010-11-24 2015-08-25 Kohler Co. Portal for harvesting energy from distributed electrical power sources
CN102624245A (en) * 2011-01-28 2012-08-01 联正电子(深圳)有限公司 Quasi resonance push-pull converter and control method thereof
US10153701B2 (en) 2011-03-03 2018-12-11 Telefonaktiebolaget Lm Ericsson (Publ) Controlling a switched mode power supply with maximised power efficiency
US9083247B2 (en) * 2011-04-25 2015-07-14 Fairchild Semiconductor Corporation Synchronous rectifier control techniques for a resonant converter
KR101228797B1 (en) * 2011-05-30 2013-01-31 한국과학기술원 Power supply apparatus
US8737094B2 (en) * 2011-11-17 2014-05-27 Ixys Corporation Transformer drive for low conduction loss rectifier in flyback converter
US8970067B2 (en) 2011-11-30 2015-03-03 Futurewei Technologies, Inc. Hybrid DC/DC converters and methods
WO2013113354A1 (en) 2012-01-30 2013-08-08 Telefonaktiebolaget Lm Ericsson (Publ) Controlling a switched mode power supply with maximised power efficiency
WO2013117226A1 (en) 2012-02-09 2013-08-15 Telefonaktiebolaget L M Ericsson (Publ) Control of transformer flux density in an isolated switched mode power supply
CN104106203B (en) 2012-02-17 2017-09-29 瑞典爱立信有限公司 The electric voltage feed forward compensation and Voltage Feedback compensation of switched-mode power supply
US8952753B2 (en) 2012-02-17 2015-02-10 Quantance, Inc. Dynamic power supply employing a linear driver and a switching regulator
US8890502B2 (en) 2012-02-17 2014-11-18 Quantance, Inc. Low-noise, high bandwidth quasi-resonant mode switching power supply
WO2013156079A1 (en) 2012-04-20 2013-10-24 Telefonaktiebolaget Lm Ericsson (Publ) Controlling a switched mode power supply with maximised power efficiency
US9276460B2 (en) 2012-05-25 2016-03-01 Flextronics Ap, Llc Power converter with noise immunity
WO2013182249A1 (en) 2012-06-08 2013-12-12 Telefonaktiebolaget L M Ericsson (Publ) Controlling a switched mode power supply with maximised power efficiency
US9203292B2 (en) 2012-06-11 2015-12-01 Power Systems Technologies Ltd. Electromagnetic interference emission suppressor
US9203293B2 (en) 2012-06-11 2015-12-01 Power Systems Technologies Ltd. Method of suppressing electromagnetic interference emission
US9019726B2 (en) 2012-07-13 2015-04-28 Flextronics Ap, Llc Power converters with quasi-zero power consumption
US9019727B2 (en) * 2012-07-18 2015-04-28 Linear Technology Corporation Temperature compensation of output diode in an isolated flyback converter
US9019724B2 (en) 2012-07-27 2015-04-28 Flextronics Ap, Llc High power converter architecture
US8937468B2 (en) 2012-08-13 2015-01-20 Northrop Grumman Systems Corporation Power supply systems and methods
US9287792B2 (en) 2012-08-13 2016-03-15 Flextronics Ap, Llc Control method to reduce switching loss on MOSFET
US9281749B2 (en) 2012-08-13 2016-03-08 Northrop Grumman Systems Corporation Multiple power supply systems and methods
US9312775B2 (en) 2012-08-15 2016-04-12 Flextronics Ap, Llc Reconstruction pulse shape integrity in feedback control environment
US9136769B2 (en) 2012-10-10 2015-09-15 Flextronics Ap, Llc Load change detection for switched mode power supply with low no load power
US9605860B2 (en) 2012-11-02 2017-03-28 Flextronics Ap, Llc Energy saving-exhaust control and auto shut off system
US9660540B2 (en) 2012-11-05 2017-05-23 Flextronics Ap, Llc Digital error signal comparator
US9494658B2 (en) 2013-03-14 2016-11-15 Flextronics Ap, Llc Approach for generation of power failure warning signal to maximize useable hold-up time with AC/DC rectifiers
US9323267B2 (en) 2013-03-14 2016-04-26 Flextronics Ap, Llc Method and implementation for eliminating random pulse during power up of digital signal controller
US9184668B2 (en) 2013-03-15 2015-11-10 Flextronics Ap, Llc Power management integrated circuit partitioning with dedicated primary side control winding
US8654553B1 (en) 2013-03-15 2014-02-18 Flextronics Ap, Llc Adaptive digital control of power factor correction front end
US9627915B2 (en) 2013-03-15 2017-04-18 Flextronics Ap, Llc Sweep frequency mode for multiple magnetic resonant power transmission
US9712063B2 (en) 2013-04-15 2017-07-18 Futurewei Technologies, Inc. Apparatus and method for loosely regulated power converters
US9407154B2 (en) * 2013-06-14 2016-08-02 Advanced Charging Technologies, LLC Electrical circuit for delivering power to consumer electronic devices
US9866133B2 (en) 2014-01-10 2018-01-09 Astec International Limited Control circuits and methods for regulating output voltages using multiple and/or adjustable reference voltages
US9698694B2 (en) 2014-01-10 2017-07-04 Astec International Limited Control circuits and methods for regulating output voltages based on adjustable references voltages
DE102014201581A1 (en) 2014-01-29 2015-07-30 Robert Bosch Gmbh On-board network isolation circuit for DC-DC converter and method for separating a vehicle electrical system from a DC-DC converter
US9362832B2 (en) 2014-02-25 2016-06-07 Telefonaktiebolaget L M Ericsson (Publ) Intermediate bus architecture power supply
CN105099230B (en) 2014-04-16 2018-07-31 华为技术有限公司 Controlled resonant converter and its synchronous rectification translation circuit
FR3023083B1 (en) * 2014-06-30 2018-03-16 Valeo Siemens Eautomotive France Sas VOLTAGE CONVERTER COMPRISING AN ISOLATED DC / DC CONVERTER CIRCUIT
US9621053B1 (en) 2014-08-05 2017-04-11 Flextronics Ap, Llc Peak power control technique for primary side controller operation in continuous conduction mode
KR101832296B1 (en) 2016-04-26 2018-02-26 엠투파워 주식회사 Foward-flyback bus converter
CA2972307A1 (en) 2016-07-07 2018-01-07 Tianshu Liu Multi-stage multilevel dc-dc step-down converter
FR3056038B1 (en) * 2016-09-12 2018-10-12 Valeo Systemes De Controle Moteur VOLTAGE CONVERTER WITH TWO CIRCUITS VOLTAGE CONVERTER CHAINS
US10381822B2 (en) 2016-12-12 2019-08-13 Google Llc Oring control using low voltage device for high voltage DC rack
US10700611B2 (en) * 2016-12-28 2020-06-30 Halliburton Energy Services, Inc. Current-to-voltage power converter
CN108988400B (en) * 2018-07-03 2021-04-27 中国科学院广州能源研究所 Power distribution method for multi-machine parallel power electronic transformer and electronic equipment
US11407322B2 (en) 2019-09-05 2022-08-09 Hong Kong Applied Science and Technology Research Institute Company, Limited Smart power hub
KR20210060067A (en) * 2019-11-18 2021-05-26 삼성전자주식회사 Electronic device for performing power management and method for operating thereof
US11223289B2 (en) 2020-01-17 2022-01-11 Astec International Limited Regulated switched mode power supplies having adjustable output voltages

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988009084A1 (en) * 1987-05-13 1988-11-17 Otis Elevator Company Switching regulator
US5179512A (en) * 1991-09-18 1993-01-12 General Electric Company Gate drive for synchronous rectifiers in resonant converters
EP0549920A1 (en) * 1991-12-31 1993-07-07 Alcatel Standard Electrica, S.A. Rectification system for non-resonant voltage switched converters
US5274543A (en) * 1992-04-20 1993-12-28 At&T Bell Laboratories Zero-voltage switching power converter with lossless synchronous rectifier gate drive
US5625541A (en) * 1993-04-29 1997-04-29 Lucent Technologies Inc. Low loss synchronous rectifier for application to clamped-mode power converters

Family Cites Families (171)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1181803A (en) 1914-07-31 1916-05-02 Gen Electric Attachment-plug.
US2042274A (en) 1933-12-30 1936-05-26 Standard Oil Dev Co Method and apparatus for protecting oil storage tanks
US2241261A (en) * 1940-05-29 1941-05-06 Wheeler Insulated Wire Company Transformer
US2497534A (en) 1947-09-13 1950-02-14 Gen Electric Circuits for high-frequency operation of fluorescent lamps
BE538611A (en) 1954-06-02 1900-01-01
US2902862A (en) 1955-05-16 1959-09-08 Harry G Twiford Static wheel balancer
US2852730A (en) 1955-09-23 1958-09-16 Motorola Inc Power supply
GB909969A (en) 1958-07-26
US3141140A (en) 1959-05-20 1964-07-14 Acoustica Associates Inc A. c. operated transistor oscillator or amplifier circuits
DE1278601B (en) 1959-07-04 1968-09-26 Philips Nv Self-excited transistor voltage converter
US3029398A (en) 1959-08-05 1962-04-10 Thompson Ramo Wooldridge Inc Converter
US3083328A (en) 1959-12-10 1963-03-26 Bell Telephone Labor Inc Control circuit
US3161837A (en) 1961-07-27 1964-12-15 Daven Company Self-oscillatory direct-current to alternating-current inverters with magnetic amplifer controls
US3229111A (en) 1961-10-27 1966-01-11 Electro Seal Corp A.c. power system having alternate sources of supply
US3241035A (en) 1962-01-26 1966-03-15 Warren Mfg Company Inc A.c.-d.c. regulated power supply
US3174042A (en) 1962-03-01 1965-03-16 White Ralph Effner Distortion-free high voltage power supply
US3295042A (en) 1963-10-14 1966-12-27 Robertshaw Controls Co Capacitance to d. c. voltage converter
US3307073A (en) 1964-04-02 1967-02-28 Motorola Inc Ignition system with series connected transistor and common core inductors to speed switching
US3313996A (en) 1964-05-04 1967-04-11 Honeywell Inc Rectifier control apparatus
US3343073A (en) 1964-07-13 1967-09-19 Lorain Prod Corp Regulated direct current power supply employing auxiliary cell
US3435375A (en) 1965-09-20 1969-03-25 Motorola Inc Controller having fet bridge circuit
US3400325A (en) 1966-01-28 1968-09-03 Rca Corp Voltage regulator including transient reducing means
US3458798A (en) 1966-09-15 1969-07-29 Ibm Solid state rectifying circuit arrangements
US3471747A (en) 1967-02-02 1969-10-07 Gen Motors Corp Starting circuit and solid state running circuit for high pressure arc lamp
US3454853A (en) 1967-04-06 1969-07-08 Honeywell Inc Tracer servo control apparatus for a machine tool with slow down means for the feed axis
US3495157A (en) 1967-06-22 1970-02-10 Forbro Design Corp Preventing turn-off overshoot in regulated power supplies employing feedback regulation
US3514692A (en) 1967-06-22 1970-05-26 Honeywell Inc High efficiency voltage regulating circuit
US3459957A (en) 1967-07-19 1969-08-05 Ite Imperial Corp Voltage regulator circuit
US3448370A (en) 1967-08-11 1969-06-03 Bell Telephone Labor Inc High frequency power inverter
FR96147E (en) 1967-09-14 1972-05-19 Ibm Converter improves direct current to direct current with constant power to the load.
US3517301A (en) 1967-10-23 1970-06-23 Bunker Ramo Regulated power supply
US3573494A (en) 1968-01-12 1971-04-06 Automatic Timing & Controls Differential transformer demodulating circuit
GB1246860A (en) 1968-02-10 1971-09-22 Wandel & Goltermann Direct current converter
US3506908A (en) 1968-05-20 1970-04-14 Trw Inc Elimination of short circuit current of power transistors in push-pull inverter circuits
US3553428A (en) 1968-08-30 1971-01-05 Du Pont Apparatus and method for controlling the power supplied to a load
US3573508A (en) 1968-09-27 1971-04-06 Bell Telephone Labor Inc Thyristor switch circuit
US3604920A (en) 1968-09-30 1971-09-14 Donald M Niles Portable fluorescent lantern
US3599073A (en) 1968-12-18 1971-08-10 Texas Instruments Inc Voltage-regulated power supply with standby power capability
US3579026A (en) 1969-01-02 1971-05-18 Sylvania Electric Prod Lamp ballast
GB1278272A (en) * 1969-02-19 1972-06-21 Pfizer Ltd Substituted hexahydro-imidazoquinolines
US3564393A (en) 1969-03-12 1971-02-16 North American Rockwell Circuit using capacitor and switch on primary winding of transformer for regulating voltage on secondary winding of transformer
JPS4810976B1 (en) 1969-03-12 1973-04-09
US3581186A (en) 1969-03-19 1971-05-25 Motorola Inc Reduced forward voltage drop rectifying circuit
US3619713A (en) 1969-04-01 1971-11-09 Sola Basic Ind Inc High-frequency lamp circuit for copying apparatus
US3584289A (en) 1969-04-17 1971-06-08 Bell Telephone Labor Inc Regulated inverter using synchronized leading edge pulse width modulation
US3573483A (en) 1969-05-02 1971-04-06 Essex International Inc Power supply control apparatus
US3573544A (en) 1969-05-21 1971-04-06 Energy Electronics A gas discharge lamp circuit employing a transistorized oscillator
US3569818A (en) 1969-07-22 1971-03-09 Hughes Aircraft Co Multiple output dc voltage regulator
US3629648A (en) 1969-07-31 1971-12-21 Brent W Brown Transistorized fluorescent tube operating circuit
US3582758A (en) 1969-09-30 1971-06-01 Ibm Rectifier using low saturation voltage transistors
US3588595A (en) 1969-11-26 1971-06-28 Kidde & Co Walter Fluorescent lamp ballast and thermal protective means therefor
NL6919147A (en) 1969-12-19 1971-06-22
US3629725A (en) 1969-12-24 1971-12-21 Bell Telephone Labor Inc Driven inverter with low-impedance path to drain stored charge from switching transistors during the application of reverse bias
US3573597A (en) 1969-12-29 1971-04-06 Gen Electric High current switching regulator with overlapped output current pulses
US3646395A (en) 1970-05-15 1972-02-29 American Optical Corp High repetition rate laser optical pumping system
CA963083A (en) 1970-06-26 1975-02-18 Hisayuki Matsumoto Current control circuit for a plurality of loads
US3696286A (en) 1970-08-06 1972-10-03 North American Rockwell System for detecting and utilizing the maximum available power from solar cells
US3639099A (en) * 1970-08-13 1972-02-01 Grace W R & Co Preparation of high-silica faujasite
US3668508A (en) 1970-09-15 1972-06-06 Acme Electric Corp Regulator circuit
US3684891A (en) 1970-09-28 1972-08-15 Dual Lite Co Fail-safe solid-state emergency lighting power supply and transfer circuit
US3663941A (en) * 1970-12-16 1972-05-16 Nasa Dc to ac to dc converter having transistor synchronous rectifiers
US3660672A (en) 1971-02-25 1972-05-02 Pioneer Magnetics Inc Power supply dual output
US3665203A (en) 1971-03-15 1972-05-23 Jerry D Hogg Parallel direct current generators arrangement
US3710231A (en) 1971-03-15 1973-01-09 Westinghouse Electric Corp D.c. static switch including means to suppress transient spikes between a drive source and the switch element
US3638099A (en) 1971-03-29 1972-01-25 Collins Radio Co Self-excited inverter employing commutation time transformers
FR2134287B1 (en) 1971-04-30 1974-03-08 Schlumberger Compteurs
JPS5129702Y2 (en) 1971-06-09 1976-07-27
US3704381A (en) 1971-09-02 1972-11-28 Forbro Design Corp High stability current regulator controlling high current source with lesser stability
BE788914A (en) 1971-09-17 1973-03-15 Philips Nv DIRECT CURRENT-ALTERNATIVE CURRENT CONVERTER
BE790134A (en) 1971-10-19 1973-02-15 Western Electric Co CONTINUOUS-DIRECT CURRENT CONVERTER
US3743861A (en) 1971-11-26 1973-07-03 Honeywell Inc Thyristor hard-firing circuit
IT944469B (en) 1971-12-29 1973-04-20 Honeywell Inf Systems SWITCH TRANSFORMER DRIVING CIRCUIT
US3787730A (en) 1971-12-29 1974-01-22 United Aircraft Corp Bilateral high voltage dc system
IT946985B (en) 1972-01-28 1973-05-21 Honeywell Inf Systems TRANSFORMER DRIVING CIRCUIT FOR SWITCH TRANSISTOR
US3737755A (en) 1972-03-22 1973-06-05 Bell Telephone Labor Inc Regulated dc to dc converter with regulated current source driving a nonregulated inverter
US3733538A (en) 1972-03-28 1973-05-15 Westinghouse Electric Corp Apparatus for limiting instantaneous inverter current
US3771040A (en) 1972-04-18 1973-11-06 Nasa Regulated dc-to-dc converter for voltage step-up or step-down with input-output isolation
US3753076A (en) 1972-04-27 1973-08-14 Lighting Systems Inc Inverter circuit and switching means
US3769545A (en) 1972-05-25 1973-10-30 Kodan Inc Circuit arrangement for operating electric arc discharge devices
US3851278A (en) 1972-06-12 1974-11-26 Bell & Howell Japan Inverter circuit
US3753071A (en) 1972-06-15 1973-08-14 Westinghouse Electric Corp Low cost transistorized inverter
US3845404A (en) 1972-06-16 1974-10-29 T Trilling Differential amplifier having active feedback circuitry
US3781505A (en) 1972-06-28 1973-12-25 Gen Electric Constant duty cycle control of induction cooking inverter
US3781638A (en) 1972-06-28 1973-12-25 Gen Electric Power supply including inverter having multiple-winding transformer and control transistor for controlling main switching transistors and providing overcurrent protection
US3757195A (en) 1972-08-11 1973-09-04 Honeywell Inc Isolated two wire signal transmitter
US3818237A (en) 1972-08-14 1974-06-18 Hughes Aircraft Co Means for providing redundancy of key system components
US3754177A (en) 1972-09-05 1973-08-21 Lectron Corp Solid state controller
US3873846A (en) 1972-09-07 1975-03-25 Sony Corp Power supply system
US3816810A (en) 1973-01-02 1974-06-11 Honeywell Inf Systems High current, regulated power supply with fault protection
US3824450A (en) 1973-05-14 1974-07-16 Rca Corp Power supply keep alive system
US3859638A (en) 1973-05-31 1975-01-07 Intersil Inc Non-volatile memory unit with automatic standby power supply
US3879652A (en) 1973-08-13 1975-04-22 Westinghouse Electric Corp AC solid state power controller with minimized internal power supply requirements
US3940682A (en) * 1973-10-15 1976-02-24 General Electric Company Rectifier circuits using transistors as rectifying elements
US3909695A (en) 1973-10-17 1975-09-30 Hewlett Packard Co Regulation and stabilization in a switching power supply
US3848175A (en) 1973-10-24 1974-11-12 Gen Electric Starting inhibit scheme for an hvdc converter
US3851240A (en) 1973-11-15 1974-11-26 Gen Electric Rectifier circuits using at least one multi-winding transformer in combination with transistors connected in an inverter mode and arranged in a bridge configuration
US3913002A (en) 1974-01-02 1975-10-14 Gen Electric Power circuits for obtaining a high power factor electronically
US3909700A (en) 1974-01-18 1975-09-30 Gen Electric Monolithic semiconductor rectifier circuit structure
US3879647A (en) 1974-06-07 1975-04-22 Bell Telephone Labor Inc DC to DC converter with regulation having accelerated soft start into active control region of regulation and fast response overcurrent limiting features
US3913036A (en) 1974-08-16 1975-10-14 Victor Comptometer Corp High-power, high frequency saturable core multivibrator power supply
US3912940A (en) 1974-09-18 1975-10-14 Honeywell Inc Dc power supply
US3938024A (en) * 1975-01-06 1976-02-10 Bell Telephone Laboratories, Incorporated Converter regulation by controlled conduction overlap
US3949238A (en) * 1975-01-13 1976-04-06 Northern Electric Company, Limited Distributed power switch for modular systems
US3916289A (en) 1975-01-16 1975-10-28 Us Air Force DC to DC converter
US3904950A (en) 1975-01-27 1975-09-09 Bell Telephone Labor Inc Rectifier circuit
US4078247A (en) * 1975-02-05 1978-03-07 Rca Corporation Inverter circuit control circuit for precluding simultaneous conduction of thyristors
US4027228A (en) * 1975-04-15 1977-05-31 General Electric Company Photocoupled isolated switching amplifier circuit
US4010381A (en) * 1975-04-24 1977-03-01 Bell Telephone Laboratories, Incorporated No-break ac power supply
US4205368A (en) * 1975-04-28 1980-05-27 Siemens Aktiengesellschaft Method for the transmission of DC current between at least one rectifier station and several inverter stations
US4005335A (en) * 1975-07-15 1977-01-25 Iota Engineering Inc. High frequency power source for fluorescent lamps and the like
US4017746A (en) * 1975-07-18 1977-04-12 Nartron Corporation Timing circuit means
US4011518A (en) * 1975-10-28 1977-03-08 The United States Of America As Represented By The Secretary Of The Navy Microwave GaAs FET amplifier circuit
US4187147A (en) * 1976-02-20 1980-02-05 Westinghouse Electric Corp. Recirculation system for nuclear reactors
US4066945A (en) * 1976-03-31 1978-01-03 The Bendix Corporation Linear driving circuit for a d.c. motor with current feedback
US4017784A (en) * 1976-05-17 1977-04-12 Litton Systems, Inc. DC to DC converter
US4140959A (en) * 1976-07-19 1979-02-20 Powell William S Electrical power generating system
US4074182A (en) * 1976-12-01 1978-02-14 General Electric Company Power supply system with parallel regulators and keep-alive circuitry
JPS5378042A (en) * 1976-12-20 1978-07-11 Sanyo Electric Co Ltd Switching control type power source circuit
US4150423A (en) * 1977-09-19 1979-04-17 Boschert Associates Transformer coupled pass element
US4184197A (en) * 1977-09-28 1980-01-15 California Institute Of Technology DC-to-DC switching converter
US4251857A (en) * 1979-02-21 1981-02-17 Sperry Corporation Loss compensation regulation for an inverter power supply
US4257087A (en) * 1979-04-02 1981-03-17 California Institute Of Technology DC-to-DC switching converter with zero input and output current ripple and integrated magnetics circuits
US4270165A (en) * 1979-04-24 1981-05-26 Qualidyne Systems, Inc. Controller for d.c. current supplied by a plurality of parallel power supplies
US4245286A (en) * 1979-05-21 1981-01-13 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Buck/boost regulator
US4262214A (en) * 1979-10-09 1981-04-14 The Foxboro Company System for switching a load between two sources
US4438411A (en) * 1981-07-20 1984-03-20 Ford Aerospace & Communications Corporation Temperature compensating method and apparatus for thermally stabilizing amplifier devices
US4586119A (en) * 1984-04-16 1986-04-29 Itt Corporation Off-line switching mode power supply
US4788634A (en) * 1987-06-22 1988-11-29 Massachusetts Institute Of Technology Resonant forward converter
US4788450A (en) 1987-09-11 1988-11-29 General Electric Company Backup power switch
US4812672A (en) 1987-10-01 1989-03-14 Northern Telecom Limited Selective connection of power supplies
US5019954A (en) * 1989-06-23 1991-05-28 Allied-Signal Inc. AC/DC conversion with reduced supply waveform distortion
JP2819932B2 (en) 1992-03-05 1998-11-05 日本電気株式会社 MOSFET rectifier circuit of forward converter
US5396412A (en) 1992-08-27 1995-03-07 Alliedsignal Inc. Synchronous rectification and adjustment of regulator output voltage
SE501046C2 (en) * 1993-01-25 1994-10-24 Lindmark Electric Ab Power unit with self-rotating series resonant converter
US5442534A (en) 1993-02-23 1995-08-15 California Institute Of Technology Isolated multiple output Cuk converter with primary input voltage regulation feedback loop decoupled from secondary load regulation loops
JPH0832167B2 (en) 1993-04-27 1996-03-27 日本電気株式会社 Switching power supply circuit
US5303138A (en) * 1993-04-29 1994-04-12 At&T Bell Laboratories Low loss synchronous rectifier for application to clamped-mode power converters
DE4324150C1 (en) * 1993-07-19 1994-10-27 Bruker Analytische Messtechnik Finely controlled, low-loss high-power power supply unit
US5528480A (en) 1994-04-28 1996-06-18 Elonex Technologies, Inc. Highly efficient rectifying and converting circuit for computer power supplies
US6016288A (en) * 1994-12-05 2000-01-18 Thomas Tools, Inc. Servo-driven mud pulser
US5774350A (en) * 1995-04-07 1998-06-30 Sgs-Thomson Microelectronics S.A. Integrated low dissipation power controller
JPH09103073A (en) * 1995-10-05 1997-04-15 Fujitsu Denso Ltd Dc-dc converter
KR0153863B1 (en) * 1995-12-28 1998-12-15 김광호 The switching regulator with multi-outputs
US5663887A (en) * 1996-01-11 1997-09-02 Progressive International Electronics Dispenser control console interfaced to a register
FR2753850B1 (en) * 1996-09-24 1998-11-13 SOFT SWITCHING POWER CONVERTER COMPRISING MEANS OF CORRECTING THE MEDIUM VOLTAGE OF A CAPACITIVE VOLTAGE DIVIDER
FR2758019B1 (en) * 1996-12-30 1999-01-22 Alsthom Cge Alcatel POWER CONVERTER WITH IMPROVED CONTROL OF MAIN SWITCHES
US7272021B2 (en) 1997-01-24 2007-09-18 Synqor, Inc. Power converter with isolated and regulated stages
EP0954899A2 (en) * 1997-01-24 1999-11-10 Fische, LLC High efficiency power converter
US7269034B2 (en) * 1997-01-24 2007-09-11 Synqor, Inc. High efficiency power converter
US7050309B2 (en) 2002-12-06 2006-05-23 Synqor, Inc. Power converter with output inductance
US5870299A (en) * 1997-05-28 1999-02-09 Lucent Technologies Inc. Method and apparatus for damping ringing in self-driven synchronous rectifiers
US5789871A (en) * 1997-07-09 1998-08-04 Massachusetts Institute Of Technology Series-capacitor electronic ballast
US6088329A (en) * 1997-12-11 2000-07-11 Telefonaktiebolaget Lm Ericsson Fault tolerant subrate switching
US6081432A (en) * 1998-05-26 2000-06-27 Artesyn Technologies, Inc. Active reset forward converter employing synchronous rectifiers
US5959370A (en) * 1998-07-15 1999-09-28 Pardo; Herbert Differential voltage battery DC power supply
CA2249755C (en) * 1998-10-02 2006-12-12 Praveen K. Jain Full bridge dc-dc converters
US6066943A (en) * 1998-10-08 2000-05-23 Texas Instruments Incorporated Capacitive-summing switch-mode power conversion control
US6487093B1 (en) * 2000-06-26 2002-11-26 Intel Corporation Voltage regulator
ATE381141T1 (en) * 2001-02-01 2007-12-15 Power One Inc ISOLATED DRIVER CIRCUIT ARRANGEMENT FOR USE IN POWER SWITCHING REGULATORS
US6674658B2 (en) * 2001-02-09 2004-01-06 Netpower Technologies, Inc. Power converter including circuits for improved operational control of synchronous rectifiers therein
JP3529740B2 (en) * 2001-03-29 2004-05-24 シャープ株式会社 Switching power supply
US6552917B1 (en) * 2001-11-05 2003-04-22 Koninklijke Philips Electronics N.V. System and method for regulating multiple outputs in a DC-DC converter
US6700365B2 (en) * 2001-12-10 2004-03-02 Intersil Americas Inc. Programmable current-sensing circuit providing discrete step temperature compensation for DC-DC converter
US6504267B1 (en) * 2001-12-14 2003-01-07 Koninklijke Philips Electronics N.V. Flyback power converter with secondary-side control and primary-side soft switching
US6781853B2 (en) * 2002-03-13 2004-08-24 Virginia Tech Intellectual Properties, Inc. Method and apparatus for reduction of energy loss due to body diode conduction in synchronous rectifiers
JP2004015886A (en) * 2002-06-05 2004-01-15 Shindengen Electric Mfg Co Ltd Synchronous rectification driving circuit
US6735094B2 (en) * 2002-08-15 2004-05-11 General Electric Company Low-noise multi-output power supply circuit featuring efficient linear regulators and method of design
US6728118B1 (en) * 2002-11-13 2004-04-27 Innoveta Technologies, Inc. Highly efficient, tightly regulated DC-to-DC converter
US6853568B2 (en) * 2003-05-20 2005-02-08 Delta Electronics, Inc. Isolated voltage regulator with one core structure
US6987679B2 (en) * 2003-06-18 2006-01-17 Delta Electronics, Inc. Multiple output converter with improved cross regulation
US7501715B2 (en) * 2005-06-01 2009-03-10 Delta Electronics, Inc. Multi-output DC-DC converter

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988009084A1 (en) * 1987-05-13 1988-11-17 Otis Elevator Company Switching regulator
US5179512A (en) * 1991-09-18 1993-01-12 General Electric Company Gate drive for synchronous rectifiers in resonant converters
EP0549920A1 (en) * 1991-12-31 1993-07-07 Alcatel Standard Electrica, S.A. Rectification system for non-resonant voltage switched converters
US5274543A (en) * 1992-04-20 1993-12-28 At&T Bell Laboratories Zero-voltage switching power converter with lossless synchronous rectifier gate drive
US5625541A (en) * 1993-04-29 1997-04-29 Lucent Technologies Inc. Low loss synchronous rectifier for application to clamped-mode power converters

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BLANCHARD R ; SEVERNS R: " MOSFETs Move In On Low Voltage Rectification" OFFICIAL PROCEEDINGS OF THE NINTH INTERNATIONAL PCI '84 CONFERENCE, 29 - 31 October 1984, PARIS, pages 213- 222, XP002064681 *
GARCIA O ET AL: "ZERO VOLTAGE SWITCHING IN THE PWM HALF BRIDGE TOPOLOGY WITH COMPLEMENTARY CONTROL AND SYNCHRONOUS RECTIFICATION" RECORD OF THE ANNUAL POWER ELECTRONICS SPECIALISTS CONFERENCE (PESC, ATLANTA, JUNE 12 - 15, 1995, vol. VOL. 1, no. CONF. 26, 12 June 1995, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 286-291, XP000548419 *
See also references of EP0954899A2 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7119524B2 (en) 1999-07-07 2006-10-10 Bank America, N.A. Control of DC/DC converters having synchronous rectifiers
US11705820B2 (en) 2013-07-02 2023-07-18 Vicor Corporation Power distribution architecture with series-connected bus converter
CN107851661A (en) * 2015-06-23 2018-03-27 Tm4股份有限公司 The physical topological structure of power converter

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US6731520B2 (en) 2004-05-04
AU722043B2 (en) 2000-07-20
US20030112645A1 (en) 2003-06-19
EP0954899A2 (en) 1999-11-10
US20050024906A1 (en) 2005-02-03
US7564702B2 (en) 2009-07-21
US7272023B2 (en) 2007-09-18
US20060209572A1 (en) 2006-09-21
US5999417A (en) 1999-12-07
WO1998033267A3 (en) 1998-09-11
JP2002514378A (en) 2002-05-14
CA2278250A1 (en) 1998-07-30
US20080151580A1 (en) 2008-06-26
US6594159B2 (en) 2003-07-15
US20010010637A1 (en) 2001-08-02
US7072190B2 (en) 2006-07-04
AU5931498A (en) 1998-08-18
US6222742B1 (en) 2001-04-24

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