WO1998045947A1 - Configurable logic element for fpga - Google Patents

Configurable logic element for fpga Download PDF

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Publication number
WO1998045947A1
WO1998045947A1 PCT/US1997/015366 US9715366W WO9845947A1 WO 1998045947 A1 WO1998045947 A1 WO 1998045947A1 US 9715366 W US9715366 W US 9715366W WO 9845947 A1 WO9845947 A1 WO 9845947A1
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WO
WIPO (PCT)
Prior art keywords
function
input
multiplexer
cle
inputs
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Application number
PCT/US1997/015366
Other languages
French (fr)
Inventor
Steven P. Young
Shekhar Bapat
Kamal Chaudhary
Trevor J. Bauer
Roman Iwanczuk
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Xilinx, Inc.
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Publication of WO1998045947A1 publication Critical patent/WO1998045947A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

Definitions

  • the invention relates to programmable integrated circuit devices, more particularly to a Configurable Logic Element (CLE) in a field programmable logic device.
  • CLE Configurable Logic Element
  • FPGAs Field Programmable Gate Arrays
  • FPGAs typically include an array of tiles.
  • Each tile includes a Configurable Logic Element (CLE) connectable to CLEs in other tiles through programmable interconnect lines .
  • the interconnect lines typically provide for connecting each CLE to each other CLE.
  • CLEs typically include combinatorial function generators, which are often implemented as 4-input lookup tables .
  • Some CLEs can also implement any 5-input function by selecting between the outputs of two 4-input function generators with another CLE input.
  • One such CLE, implemented in the Xilinx XC4000-Series FPGAs, is described in pages 4-11 through 4-23 of the Xilinx 1996 Data Book entitled “The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
  • a portion of an XC4000-Series CLE implementing a 5-input function generator is shown in Figure 1.
  • the outputs F' and G' of the two function generators F and G can be optionally combined with a third signal Hi in a third function generator 3H to form output 3H' .
  • the 3H function generator can implement any function of the three inputs (256 functions) , including a 2-to-l multiplexer that can be used when a 5-input function is desired.
  • function generators F and G share the same four inputs (Fl/Gl, F2/G2, F3/G3, F4/G4) and function generator 3H is programmed to function as a 2-to-l multiplexer
  • output 3H' can represent any function of up to five inputs (Fl/Gl, F2/G2, F3/G3, F4/G4, Hi) .
  • output 3H' can represent some functions of up to nine inputs (Fl, F2 , F3 , F4, Gl, G2 , G3 , G4, Hi).
  • Function generator 3H can be replaced by a 2-to-l multiplexer, with signal HI selecting between outputs F' and G', as disclosed in U.S. Patent No. 5,349,250 entitled "Logic Structure and Circuit for Fast Carry" by Bernard J. New. Replacing the function generator of Figure 1 with a 2- to-1 multiplexer reduces the number of supported functions with up to nine inputs, but still provides any function of up to five inputs and reduces the silicon area required to implement a five-input-func ion generator.
  • An FPGA using two 4-input function generators and a 2-to-l multiplexer to implement a five input function generator is the XC5200 family of products from Xilinx, Inc.
  • the XC5200 CLE is described in pages 4-188 through 4-190 of the Xilinx 1996 Data Book entitled “The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
  • a CLE capable of generating 6-input functions is described as implemented in the ORCATM 0R2C FPGAs from Lucent Technologies Inc. ("ORCA” is a trademark of Lucent Technologies Inc.) This CLE is described in pages 2-9 through 2-20 of the Lucent Technologies October 1996 Data Book entitled “Field-Programmable Gate Arrays", available from Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103.
  • a portion of an ORCA OR2C CLE implementing a 6-input function generator is shown here in Figure 2.
  • the CLE of Figure 2 comprises four 4-input function generators QLUT0 , QLUTl, QLUT2, QLUT3.
  • Function generator QLUT0 has four inputs B0, Bl, B2, B3
  • function generator QLUTl has four inputs Bl, B2, B3 , B4.
  • QLUT0 and QLUTl can be selected between in 2- to-1 multiplexer MUX0 with CLE input signal B4 acting as a select line to form output M0.
  • Multiplexer MUX0 therefore can provide functions of five input signals BO, Bl, B2 , B3 , B4.
  • function generator QLUT2 has four inputs AO , Al, A2 , A3
  • function generator QLUT3 has four inputs Al, A2 , A3, A4.
  • Outputs QL2 and QL3 of function generators QLUT2 and QLUT3 can be optionally combined in 2-to-l multiplexer MUX3 with CLE input signal A4 acting as a select line to form output M3.
  • Multiplexer MUX3 therefore can provide functions of five input signals AO, Al , A2 , A3, A4.
  • Multiplexer outputs MO and M3 can optionally be combined in 2-to-l multiplexer MUX6 with CLE input signal CO acting as a select line to form output Ml .
  • multiplexer output Ml can represent functions of up to six inputs (A0/B0, Al/Bl, A2/B2, A3/B3, A4/B4, CO).
  • One advantage of including four function generators in a single CLE is the ability to implement circuits requiring three or four function generators, such as 6-input functions, in a single CLE, thereby improving the performance of the circuit. (Connections between CLE outputs and inputs are typically slower than internal connections within a single CLE.)
  • one disadvantage is that the resulting software model for the CLE is more complicated than the software model for a smaller, simpler CLE.
  • FPGA mapping, placing, routing, and delay estimation software tools require a CLE software model in order to implement a user's design. The more complicated the CLE software model, the more complicated it becomes to write the mapping, placing, routing, and delay estimation software, and the longer the software takes to run.
  • the amount of logic that can be placed in an FPGA is often limited by the amount of interconnect available, particularly in high-density designs (i.e., designs using a high percentage of the available logic blocks) .
  • Adding enough interconnect lines to support high- density designs allows a larger percentage of the available logic blocks to be used, but is costly in terms of silicon area because of the silicon required to programmably interconnect the lines .
  • the silicon area for the extra interconnect lines is wasted for designs that do not require the extra interconnect lines. It is therefore desirable to minimize the number of required interconnect lines, rather than adding additional lines for high-density designs.
  • a CLE preferably included in each of an array of identical tiles.
  • a CLE according to the invention has four 4-input function generators .
  • the outputs of first and second function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs.
  • the multiplexer or function generator can provide some functions of up to nine inputs, since none of the inputs are shared.
  • One 6-input function that is particularly useful is a 4-to-l multiplexer, which is a function frequently used in FPGA customer designs.
  • the outputs of the third and fourth function generators are similarly combined.
  • the outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a first six-input-function multiplexer or function generator, and with a different sixth independent input in a second six-input-function multiplexer or function generator.
  • the two six-input-function multiplexers or function generators therefore produce two outputs.
  • One of the outputs can be any function of six inputs; the other output can be a related function of six inputs, where five inputs and two five-input-function multiplexers or function generators are shared between the two 6-input functions.
  • One 11-input function that is particularly useful is an 8-to-l multiplexer, which is a function frequently used in FPGA customer designs .
  • the CLE of the invention is believed to be the first CLE able to generate an 8-to-l multiplexer using only four 4-input function generators .
  • the sixth input is also shared, the two 6-input functions are the same, and the same output signal appears at two exit points on the CLE.
  • One method of minimizing the number of required interconnect lines in an FPGA is to provide additional exit points for CLE outputs.
  • an output signal can use either exit point, and therefore has a wider choice of interconnect paths than when restricted to one exit point. It is also easier for the software to route the signal, and fewer of the available interconnect lines need be used.
  • multiple exit points for a six-input-function output are provided.
  • the CLE is organized into two similar portions called “slices", each slice comprising two function generators, one five-input-function multiplexer, and one six-input-function multiplexer.
  • the two slices are symmetric , and in one embodiment are laid out as mirror images of each other. Therefore, a software model for a single slice can be used by the FPGA mapping, placing, routing, and delay estimation software, resulting in a much simpler model than would be required to model the entire CLE. A simpler model decreases software runtime and simplifies the software development process. Additionally, using a similar layout for the two slices results in approximately equal delays between corresponding nodes in the two slices of the CLE and also provides a considerable saving to the FPGA vendor of time and money during the design cycle.
  • the second six-input-function multiplexer provides several benefits while using little or no additional silicon area.
  • either the five-input-function multiplexers, the six-input-function multiplexers, or both have additional inputs, thereby further increasing the number of functions that can be implemented in the CLE.
  • the number of functions supported by the CLE is increased by using 3-input function generators instead of the five-input-function multiplexers, the six- input-function multiplexers, or both.
  • each slice has a separate carry chain.
  • each carry chain incorporates the outputs of two function generators .
  • Figure 1 shows a portion of a prior art CLE that can evaluate 5-input functions.
  • Figure 2 shows a portion of a prior art CLE that can evaluate 6-input functions.
  • Figure 3 shows the function generators and multiplexers for a single CLE according to a first embodiment of the invention.
  • Figures 4A and 4B show the internal logic for one CLE according to a second embodiment of the invention. To view the entire CLE, Figures 4A and 4B must be viewed together as shown in the key at the top of Figure 4A.
  • Figure 3 shows a simplified block diagram of a portion of a first CLE according to the invention. Included in Figure 3 are four 4-input function generators F, G, H, J.
  • the outputs of function generators F and G (F' and G' , respectively) are combined with a fifth independent input BFF in five-input-function multiplexer F5B to produce output F5B', which can be any function of five inputs, or some functions of up to nine inputs .
  • the outputs of function generators H and J (H' and J' , respectively) are combined with a fifth independent input BHH in five-input-function multiplexer F5A to produce output F5A' , which can be any function of five inputs, or some functions of up to nine inputs.
  • the outputs F5A' and F5B' of five-input-function multiplexers F5A and F5B are combined with a sixth independent input BGG in a first six-input-function multiplexer F6B, and with a different sixth independent input BJJ in a second six-input-function multiplexer F6A.
  • the two six-input-function multiplexers F6A and F6B therefore produce two outputs F6A' and F6B' , respectively.
  • One of outputs F6A' and F6B' can be any function of six inputs; the other output can be any function of six inputs provided that five inputs are shared between the two 6-input functions . Some functions of up to nineteen inputs can also be generated in a single CLE.
  • the CLE of Figure 3 can be viewed as two slices SA, SB.
  • Each slice SA, SB comprises two 4-input function generators (H and J, F and G, respectively) , one five-input-function multiplexer (F5A, F5B, respectively) , and one six-input- function multiplexer (F6A, F6B, respectively) .
  • FIG. 4A and 4B A second CLE in accordance with the invention is shown in Figures 4A and 4B.
  • the CLE is implemented in two slices.
  • Figures 4A and 4B each showing one slice, must be viewed together as shown in the key at the top of Figure 4A.
  • Programmable (configurable) bits controlling the function of the CLE are shown as small boxes containing an "x" .
  • the CLE of Figures 4A and 4B includes four function generators: F and G in Figure 4B, and H and J in Figure 4A.
  • Function generator F has four inputs Fl , F2 , F3 , F4 ;
  • function generator G has four inputs Gl, G2 , G3 , G4;
  • function generator H has four inputs Hi, H2 , H3 , H4;
  • function generator J has four inputs Jl, J2 , J3 , J4.
  • Each of function generators F, G, H, J also has a data-in input DI and an output 0.
  • each function generator F, G has a write strobe WS input WSF, WSG, respectively, generated in write strobe generator WB from clock input signal CKO optionally inverted by multiplexer 69B, set/reset input signal SRO optionally inverted by multiplexer 60B, and input signal BF optionally inverted by multiplexer VF .
  • Each function generator H, J has a write strobe WS input WSH, WSJ, respectively, generated in write strobe generator WA from clock input signal CK1 optionally inverted by multiplexer 69A, set/reset input signal SRI optionally inverted by multiplexer 6OB, and input signal BH optionally inverted by multiplexer VH.
  • Function generators F, G, H, J of Figures 4A and 4B have the ability to operate as shift registers as well as small RAMs and lookup tables.
  • Write strobe signal WS controls the shifting function and the RAM write cycle.
  • Data-in port DI carries a data signal (in this embodiment derived from input signals BF, BH, BG, BJ) for writing to an addressed memory cell.
  • a data signal in this embodiment derived from input signals BF, BH, BG, BJ
  • the shift register data input signal is taken from BF, BG, BH, BJ, respectively.
  • Write strobe generators WB, WA generate write strobe signals WSF and WSG, WSH and WSJ, respectively. Signals WSF, WSG, WSH, WSJ strobe data into their respective function generators during a write cycle when the function generators are configured as RAM, and cause a shift when the function generators are configured as shift registers .
  • the use of function generators as RAM is described in pages 4-11 through 4-23 of the Xilinx 1996 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
  • the function generator of this embodiment can therefore be configured as a look-up table, a shift register, a 16x1 RAM, half of a 16x1 dual-ported RAM (when the two function generators in a slice are paired together) , half of a 16x2 RAM, or half of a 32x1 RAM (when the two function generators in a slice are paired together) . Not all combinations of function generator configurations are supported in a single slice. The supported combinations are detailed below.
  • write strobe signals WSF and WSG are controlled by write strobe generator WB .
  • a High (logic 1) pulse on function generator input WS causes a write to occur to the function generator look-up table, to either the first memory cell of the look-up table (if configured as a shift register) or to an addressed cell (if configured as a RAM) .
  • Write strobe generator WB functions as follows in the supported combinations of function generator configurations : a) when function generators F and G are both configured as look-up tables, write strobe signals WSF and WSG are held Low (logic 0) ; b) when function generator G is configured as a 16x1 RAM or shift register and function generator F is configured as a look-up table, write strobe signal WSF remains Low while write strobe signal WSG pulses High when
  • SRO is active (Low or High, depending on whether multiplexer 60B is inverting or not) and CKO makes the proper transition (falling or rising, depending on whether multiplexer 69B is inverting CKO or not) ;
  • function generators F and G are configured as a single 32x1 RAM, one but not both of write strobe signals WSF and WSG pulses High, when SRO is active and CKO makes the proper transition.
  • the generated High pulse occurs on write strobe signal WSF if multiplexer VF is non-inverting and input signal BF is High or if multiplexer VF is inverting and input signal BF is low, otherwise the High pulse occurs on write strobe signal WSG.
  • SRO acts as a write enable and CKO acts as a clock to a synchronous RAM or shift register, while BF serves as a fifth address bit when the two function generators in a slice are configured as a 32- bit RAM.
  • Write strobe signals WSH and WSJ are generated by write strobe generator WA and controlled by input signals SRI, CKl, and BH, in a corresponding fashion.
  • AND gates 61F, 61G, 61H, 61J and multiplexers 81F, 81G, 81H, 81J, CF, CG, CH, CJ implement multiplier and carry logic functions.
  • each of multiplexers 81F, 81G, 81H, 81J has separate programmable memory cells that determine the multiplexer output.
  • the two multiplexers in each slice (81F and 81G, 81H and 81J) share memory cells and therefore have the same programmed functionality.
  • each slice has a separate carry chain.
  • One carry chain is from input signal CINO to output signal COUT0 and incorporates the outputs of function generators F and G.
  • the other carry chain is from input signal CINl to output signal COUT1 and incorporates the outputs of function generators H and J.
  • Each slice further includes five-input-function multiplexer F5A, F5B and six-input-function multiplexer F6A, F6B.
  • multiplexer F6A receives an input signal on west-going line F5W from the output of multiplexer F5B in Figure 4B.
  • six-input-function multiplexer F6B receives an input signal on east-going line F5E from the output of multiplexer F5A in Figure 4A.
  • Multiplexer F6A receives a second input signal from multiplexer F5A
  • multiplexer F6B receives a second input signal from multiplexer F5B.
  • Multiplexer F5A receives inputs from outputs 0 of function generators H and J.
  • Multiplexer F5B receives inputs from outputs O of function generators F and G.
  • the CLE of this embodiment receives four extra control signals on lines BF, BH, BG, and BJ. These lines can be programmably inverted using multiplexers VF, VH, VG, and VJ, respectively, and control several useful functions .
  • the five-input function multiplexers F5A, F5B are controlled by lines BH, BF, respectively.
  • the six-input function multiplexers F6A, F6B are controlled by lines BJ, BG, respectively.
  • a user can form a four-input multiplexer using multiplexer F5A and the outputs of function generators H and J, with function generators H and J each configured as a two-input multiplexer.
  • a four-input multiplexer can be formed using multiplexer F5B and the outputs of function generators F and G.
  • a user can form an eight-input multiplexer using either multiplexer F6A or multiplexer F6B receiving inputs from both multiplexers F5A and F5B, each of which is receiving outputs from its respective function generators.
  • multiplexer F5A the memory cells in function generators H and J can operate as a 32-bit RAM.
  • multiplexer F5B the memory cells in function generators F and G can operate as a 32-bit RAM.
  • Lines BF, BH, BG, BJ serve as multiplexer control lines or RAM address lines, in addition to other functions as later described.
  • Registers RX, RY, RZ, RV generate outputs XQ, YQ, ZQ, VQ, respectively.
  • Clock inputs to registers RX, RY, RZ, RV are designated by open triangles with apexes pointing into these registers.
  • Clock enable inputs CE can be disabled using AND-gates 62A, 62B. (AND-gates 62A, 62B are controlled by a programmable memory cell that provides one of the inputs to each AND-gate.)
  • Registers RX, RY, RZ, RV can be set or reset either synchronously or asynchronously through set port S or reset port R.
  • Set/reset input signals SRO, SRI are controlled by multiplexers 60A, 6OB and AND-gates 67A, 67B. Inputs SRO, SRI (if enabled by AND-gates 67A, 67B) can set or reset the registers.
  • Set/reset control units R81B, R82B, R81A, R82A are programmably controlled to either set or reset registers RX, RY, RZ, RV, respectively.
  • Registers RX, RY, RZ, RV can also be configured as latches, the choice being made by a programmable memory cell shared between the two registers in each slice.
  • XOR gates SF, SG, SH, SJ generate the sum portion of an addition or multiplication.
  • Multiplexers MF, MG, MH, MJ select between signals to place onto output lines X, Y, Z, V, respectively.
  • Multiplexers MF and MH select between the related function generator output signal, sum output signal, and five-input function multiplexer output signal.
  • Multiplexers MG and MJ select between the related function generator output signal, sum output signal, and six-input function multiplexer output signal.
  • the function generator F, G, H, J output signal is selected when a logical function of up to four inputs is chosen.
  • the five-input function multiplexer F5A, F5B output signal is selected when one of a limited set of nine-input functions is chosen, including any logical function of five inputs, a 4-to-l multiplexer, and any other function that can be implemented as two four-input functions feeding a 2- to-1 multiplexer.
  • the six-input function multiplexer F6A, F6B output signal is selected when one of a limited set of 18-input functions is chosen, including any logical function of six inputs, an 8-to-l multiplexer, and any other function that can be implemented as the output of two five-input function multiplexers F5A, F5B feeding a 2-to-l multiplexer.
  • the sum output signal of XOR gates SF, SG, SH, SJ is selected when an appropriate arithmetic operation such as addition, subtraction or multiplication is implemented.
  • Multiplexers OF, OG, OH, OJ allow the carry chain to bypass the related function generator. Multiplexers OF, OG, OH, OJ select whether the respective carry multiplexer CF, CG, CH, CJ is controlled by the function generator output signal 0 or whether the carry chain bypasses the function generator by propagating the carry-in signal to the next stage along the carry chain. Multiplexers CA, CB allow additional access onto their respective carry chains by selecting either a carry-in signal CINO, CINl (buffered in this embodiment by inverters I121B and I122B, I121A and I122A, respectively) or an input signal BF, BH as the starting point for the carry chain in the CLE.
  • Multiplexers DF, DH select a signal to be loaded into related registers RX, RZ either from the outputs of multiplexers MF, MH, or from input signals BF, BH, respectively.
  • Multiplexers DG, DJ select a signal to be loaded into related registers RY, RV either from the outputs of multiplexers MG, MJ, or from input signal lines BG, BJ, respectively.
  • Multiplexers BB, BA are bypass multiplexers that can apply carry-out signals COUTO, C0UT1 to output lines YB, VB, or can forward input signals BG, BJ to output lines YB, VB to route a signal generated on one side of the CLE to a destination on the other side of the CLE.
  • AND-gates BRB, BRA allow input signals BG, BJ to serve as se /reset signals to registers RX, RY, RZ, RV, or alternatively allows input signals BG, BJ to be decoupled from registers RX, RY, RZ, RV so that input signals BG, BJ can be used for other purposes, such as controlling multiplexers F6B, F6A or providing a DI signal to function generators G, J, without setting or resetting the registers.
  • a logic 0 in the memory cells controlling AND-gates BRB, BRA decouples lines BG, BJ from set/reset control units R81B, R82B, R81A, R82A; while a logic 1 in the associated memory cell enables AND-gates BRB, BRA to use the signals on BG, BJ to set or reset registers RX, RY, RZ, RV as determined by set/reset control units R81B, R82B, R81A, R82A.
  • the duplicated six-input-function multiplexer or function generator of the present invention offers the benefits of: 1) optionally implementing two different 6- input functions having five shared inputs and two shared 5- input multiplexers or function generators; 2) implementing an 8-to-l multiplexer using only four 4-input function generators; 3) optionally implementing only one 6-input function but making the output thereof available at either of two exit points on an FPGA tile boundary, thereby reducing the number of required interconnect lines; 4) optionally selecting the six-input function multiplexer or function generator with the most advantageously placed unshared input; 5) a much simpler software model, with corresponding software speed and ease of software development; and 6) approximately equal delays between corresponding nodes in the two slices of the CLE, further simplifying FPGA mapping, placing, routing, and delay estimation software.
  • the present invention provides a new and useful method of generating 6-input functions in an FPGA CLE, and further provides a new and useful method of implementing an 8-to-l multiplexer using only four 4-input function generators.

Abstract

The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a first six-input-function multiplexer or function generator, and with a different sixth independent input in a second six-input-function multiplexer or function generator. According to another aspect of the invention, the CLE is implemented in two similar portions called 'slices'. Each slice has a separate carry chain. In a CLE with four function generators, each carry chain incorporates the outputs of two function generators.

Description

CONFIGURABLE LOGIC ELEMENT FOR FPGA
BACKGROUND OF THE INVENTION Field of the Invention The invention relates to programmable integrated circuit devices, more particularly to a Configurable Logic Element (CLE) in a field programmable logic device.
Description of the Background Art Field Programmable Gate Arrays (FPGAs) typically include an array of tiles. Each tile includes a Configurable Logic Element (CLE) connectable to CLEs in other tiles through programmable interconnect lines . The interconnect lines typically provide for connecting each CLE to each other CLE.
CLEs typically include combinatorial function generators, which are often implemented as 4-input lookup tables .
Some CLEs can also implement any 5-input function by selecting between the outputs of two 4-input function generators with another CLE input. One such CLE, implemented in the Xilinx XC4000-Series FPGAs, is described in pages 4-11 through 4-23 of the Xilinx 1996 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) A portion of an XC4000-Series CLE implementing a 5-input function generator is shown in Figure 1. The outputs F' and G' of the two function generators F and G can be optionally combined with a third signal Hi in a third function generator 3H to form output 3H' . The 3H function generator can implement any function of the three inputs (256 functions) , including a 2-to-l multiplexer that can be used when a 5-input function is desired. When function generators F and G share the same four inputs (Fl/Gl, F2/G2, F3/G3, F4/G4) and function generator 3H is programmed to function as a 2-to-l multiplexer, output 3H' can represent any function of up to five inputs (Fl/Gl, F2/G2, F3/G3, F4/G4, Hi) . When the inputs to function generators F and G are independent, output 3H' can represent some functions of up to nine inputs (Fl, F2 , F3 , F4, Gl, G2 , G3 , G4, Hi). Function generator 3H can be replaced by a 2-to-l multiplexer, with signal HI selecting between outputs F' and G', as disclosed in U.S. Patent No. 5,349,250 entitled "Logic Structure and Circuit for Fast Carry" by Bernard J. New. Replacing the function generator of Figure 1 with a 2- to-1 multiplexer reduces the number of supported functions with up to nine inputs, but still provides any function of up to five inputs and reduces the silicon area required to implement a five-input-func ion generator. An FPGA using two 4-input function generators and a 2-to-l multiplexer to implement a five input function generator is the XC5200 family of products from Xilinx, Inc. The XC5200 CLE is described in pages 4-188 through 4-190 of the Xilinx 1996 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
A CLE capable of generating 6-input functions is described as implemented in the ORCATM 0R2C FPGAs from Lucent Technologies Inc. ("ORCA" is a trademark of Lucent Technologies Inc.) This CLE is described in pages 2-9 through 2-20 of the Lucent Technologies October 1996 Data Book entitled "Field-Programmable Gate Arrays", available from Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103. A portion of an ORCA OR2C CLE implementing a 6-input function generator is shown here in Figure 2. The CLE of Figure 2 comprises four 4-input function generators QLUT0 , QLUTl, QLUT2, QLUT3. Function generator QLUT0 has four inputs B0, Bl, B2, B3 and function generator QLUTl has four inputs Bl, B2, B3 , B4. Outputs QL0 and QLl of function generators
QLUT0 and QLUTl, respectively, can be selected between in 2- to-1 multiplexer MUX0 with CLE input signal B4 acting as a select line to form output M0. Multiplexer MUX0 therefore can provide functions of five input signals BO, Bl, B2 , B3 , B4. Similarly, function generator QLUT2 has four inputs AO , Al, A2 , A3 and function generator QLUT3 has four inputs Al, A2 , A3, A4. Outputs QL2 and QL3 of function generators QLUT2 and QLUT3 , respectively, can be optionally combined in 2-to-l multiplexer MUX3 with CLE input signal A4 acting as a select line to form output M3. Multiplexer MUX3 therefore can provide functions of five input signals AO, Al , A2 , A3, A4. Multiplexer outputs MO and M3 can optionally be combined in 2-to-l multiplexer MUX6 with CLE input signal CO acting as a select line to form output Ml . When input signals AO, Al, A2 , A3, A4 are shared with input signals BO, Bl, B2 , B3 , B4, respectively, multiplexer output Ml can represent functions of up to six inputs (A0/B0, Al/Bl, A2/B2, A3/B3, A4/B4, CO).
One advantage of including four function generators in a single CLE is the ability to implement circuits requiring three or four function generators, such as 6-input functions, in a single CLE, thereby improving the performance of the circuit. (Connections between CLE outputs and inputs are typically slower than internal connections within a single CLE.) However, one disadvantage is that the resulting software model for the CLE is more complicated than the software model for a smaller, simpler CLE. FPGA mapping, placing, routing, and delay estimation software tools require a CLE software model in order to implement a user's design. The more complicated the CLE software model, the more complicated it becomes to write the mapping, placing, routing, and delay estimation software, and the longer the software takes to run. Therefore, it is desirable to increase the number of function generators in a CLE without increasing the complexity of the software model. Additionally, the amount of logic that can be placed in an FPGA is often limited by the amount of interconnect available, particularly in high-density designs (i.e., designs using a high percentage of the available logic blocks) . Adding enough interconnect lines to support high- density designs allows a larger percentage of the available logic blocks to be used, but is costly in terms of silicon area because of the silicon required to programmably interconnect the lines . The silicon area for the extra interconnect lines is wasted for designs that do not require the extra interconnect lines. It is therefore desirable to minimize the number of required interconnect lines, rather than adding additional lines for high-density designs.
SUMMARY OF THE INVENTION The invention provides a Configurable Logic Element
(CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four 4-input function generators . The outputs of first and second function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs. Additionally, the multiplexer or function generator can provide some functions of up to nine inputs, since none of the inputs are shared. One 6-input function that is particularly useful is a 4-to-l multiplexer, which is a function frequently used in FPGA customer designs. The outputs of the third and fourth function generators are similarly combined.
The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a first six-input-function multiplexer or function generator, and with a different sixth independent input in a second six-input-function multiplexer or function generator. The two six-input-function multiplexers or function generators therefore produce two outputs. One of the outputs can be any function of six inputs; the other output can be a related function of six inputs, where five inputs and two five-input-function multiplexers or function generators are shared between the two 6-input functions. Some functions of up to nineteen inputs can also be generated in a single CLE, since none of the inputs are shared. One 11-input function that is particularly useful is an 8-to-l multiplexer, which is a function frequently used in FPGA customer designs . The CLE of the invention is believed to be the first CLE able to generate an 8-to-l multiplexer using only four 4-input function generators . When the sixth input is also shared, the two 6-input functions are the same, and the same output signal appears at two exit points on the CLE.
One method of minimizing the number of required interconnect lines in an FPGA is to provide additional exit points for CLE outputs. When two exit points are provided, an output signal can use either exit point, and therefore has a wider choice of interconnect paths than when restricted to one exit point. It is also easier for the software to route the signal, and fewer of the available interconnect lines need be used. In a CLE according to the invention, multiple exit points for a six-input-function output are provided.
Similarly, multiple entry points for CLE input signals improve routing flexibility. Since either of two six-input function generators can be used, each having one input independent of the other, logic can be placed in the six- input function generator having the most desirable input connection.
In one embodiment, the CLE is organized into two similar portions called "slices", each slice comprising two function generators, one five-input-function multiplexer, and one six-input-function multiplexer. The two slices are symmetric , and in one embodiment are laid out as mirror images of each other. Therefore, a software model for a single slice can be used by the FPGA mapping, placing, routing, and delay estimation software, resulting in a much simpler model than would be required to model the entire CLE. A simpler model decreases software runtime and simplifies the software development process. Additionally, using a similar layout for the two slices results in approximately equal delays between corresponding nodes in the two slices of the CLE and also provides a considerable saving to the FPGA vendor of time and money during the design cycle. Further, when the same layout is used for both slices the CLE is the same size with two six-input- function multiplexers as it would be if only one six-input- function multiplexer were provided. Therefore, in this embodiment, the second six-input-function multiplexer provides several benefits while using little or no additional silicon area.
In other embodiments, either the five-input-function multiplexers, the six-input-function multiplexers, or both, have additional inputs, thereby further increasing the number of functions that can be implemented in the CLE. In other embodiments, the number of functions supported by the CLE is increased by using 3-input function generators instead of the five-input-function multiplexers, the six- input-function multiplexers, or both.
According to another aspect of the invention, each slice has a separate carry chain. In a CLE with four function generators, each carry chain incorporates the outputs of two function generators .
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows a portion of a prior art CLE that can evaluate 5-input functions.
Figure 2 shows a portion of a prior art CLE that can evaluate 6-input functions.
Figure 3 shows the function generators and multiplexers for a single CLE according to a first embodiment of the invention.
Figures 4A and 4B show the internal logic for one CLE according to a second embodiment of the invention. To view the entire CLE, Figures 4A and 4B must be viewed together as shown in the key at the top of Figure 4A.
DETAILED DESCRIPTION OF THE DRAWINGS A First CLE According to the Invention
Figure 3 shows a simplified block diagram of a portion of a first CLE according to the invention. Included in Figure 3 are four 4-input function generators F, G, H, J. The outputs of function generators F and G (F' and G' , respectively) are combined with a fifth independent input BFF in five-input-function multiplexer F5B to produce output F5B', which can be any function of five inputs, or some functions of up to nine inputs . The outputs of function generators H and J (H' and J' , respectively) are combined with a fifth independent input BHH in five-input-function multiplexer F5A to produce output F5A' , which can be any function of five inputs, or some functions of up to nine inputs. The outputs F5A' and F5B' of five-input-function multiplexers F5A and F5B are combined with a sixth independent input BGG in a first six-input-function multiplexer F6B, and with a different sixth independent input BJJ in a second six-input-function multiplexer F6A. The two six-input-function multiplexers F6A and F6B therefore produce two outputs F6A' and F6B' , respectively. One of outputs F6A' and F6B' can be any function of six inputs; the other output can be any function of six inputs provided that five inputs are shared between the two 6-input functions . Some functions of up to nineteen inputs can also be generated in a single CLE.
The CLE of Figure 3 can be viewed as two slices SA, SB. Each slice SA, SB comprises two 4-input function generators (H and J, F and G, respectively) , one five-input-function multiplexer (F5A, F5B, respectively) , and one six-input- function multiplexer (F6A, F6B, respectively) .
A Second CLE According to the Invention
A second CLE in accordance with the invention is shown in Figures 4A and 4B. In this embodiment, the CLE is implemented in two slices. To view the entire CLE, Figures 4A and 4B, each showing one slice, must be viewed together as shown in the key at the top of Figure 4A. Programmable (configurable) bits controlling the function of the CLE are shown as small boxes containing an "x" .
The CLE of Figures 4A and 4B includes four function generators: F and G in Figure 4B, and H and J in Figure 4A. Function generator F has four inputs Fl , F2 , F3 , F4 ; function generator G has four inputs Gl, G2 , G3 , G4; function generator H has four inputs Hi, H2 , H3 , H4; and function generator J has four inputs Jl, J2 , J3 , J4. Each of function generators F, G, H, J also has a data-in input DI and an output 0. In addition, each function generator F, G has a write strobe WS input WSF, WSG, respectively, generated in write strobe generator WB from clock input signal CKO optionally inverted by multiplexer 69B, set/reset input signal SRO optionally inverted by multiplexer 60B, and input signal BF optionally inverted by multiplexer VF . Each function generator H, J has a write strobe WS input WSH, WSJ, respectively, generated in write strobe generator WA from clock input signal CK1 optionally inverted by multiplexer 69A, set/reset input signal SRI optionally inverted by multiplexer 6OB, and input signal BH optionally inverted by multiplexer VH.
Function generators F, G, H, J of Figures 4A and 4B have the ability to operate as shift registers as well as small RAMs and lookup tables. Write strobe signal WS controls the shifting function and the RAM write cycle.
Data-in port DI carries a data signal (in this embodiment derived from input signals BF, BH, BG, BJ) for writing to an addressed memory cell. When function generators F, G, H, J are configured as shift registers, the shift register data input signal is taken from BF, BG, BH, BJ, respectively.
Write strobe generators WB, WA generate write strobe signals WSF and WSG, WSH and WSJ, respectively. Signals WSF, WSG, WSH, WSJ strobe data into their respective function generators during a write cycle when the function generators are configured as RAM, and cause a shift when the function generators are configured as shift registers . The use of function generators as RAM is described in pages 4-11 through 4-23 of the Xilinx 1996 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
The function generator of this embodiment can therefore be configured as a look-up table, a shift register, a 16x1 RAM, half of a 16x1 dual-ported RAM (when the two function generators in a slice are paired together) , half of a 16x2 RAM, or half of a 32x1 RAM (when the two function generators in a slice are paired together) . Not all combinations of function generator configurations are supported in a single slice. The supported combinations are detailed below.
In this embodiment, write strobe signals WSF and WSG are controlled by write strobe generator WB . A High (logic 1) pulse on function generator input WS causes a write to occur to the function generator look-up table, to either the first memory cell of the look-up table (if configured as a shift register) or to an addressed cell (if configured as a RAM) .
Write strobe generator WB functions as follows in the supported combinations of function generator configurations : a) when function generators F and G are both configured as look-up tables, write strobe signals WSF and WSG are held Low (logic 0) ; b) when function generator G is configured as a 16x1 RAM or shift register and function generator F is configured as a look-up table, write strobe signal WSF remains Low while write strobe signal WSG pulses High when
SRO is active (Low or High, depending on whether multiplexer 60B is inverting or not) and CKO makes the proper transition (falling or rising, depending on whether multiplexer 69B is inverting CKO or not) ; c) when function generators F and G are configured as a dual-ported 16x1 RAM, a 16x2 RAM, or a pair of shift registers, write strobe signals WSF and WSG pulse High together when SRO is active and CKO makes the proper transition; d) when function generators F and G are configured as a single 32x1 RAM, one but not both of write strobe signals WSF and WSG pulses High, when SRO is active and CKO makes the proper transition. The generated High pulse occurs on write strobe signal WSF if multiplexer VF is non-inverting and input signal BF is High or if multiplexer VF is inverting and input signal BF is low, otherwise the High pulse occurs on write strobe signal WSG. As can be seen from the above description, SRO acts as a write enable and CKO acts as a clock to a synchronous RAM or shift register, while BF serves as a fifth address bit when the two function generators in a slice are configured as a 32- bit RAM.
Write strobe signals WSH and WSJ are generated by write strobe generator WA and controlled by input signals SRI, CKl, and BH, in a corresponding fashion.
AND gates 61F, 61G, 61H, 61J and multiplexers 81F, 81G, 81H, 81J, CF, CG, CH, CJ implement multiplier and carry logic functions. In Figures 4A and 4B, each of multiplexers 81F, 81G, 81H, 81J has separate programmable memory cells that determine the multiplexer output. In another embodiment, the two multiplexers in each slice (81F and 81G, 81H and 81J) share memory cells and therefore have the same programmed functionality.
In the embodiment of Figures 4A and 4B, each slice has a separate carry chain. One carry chain is from input signal CINO to output signal COUT0 and incorporates the outputs of function generators F and G. The other carry chain is from input signal CINl to output signal COUT1 and incorporates the outputs of function generators H and J. Each slice further includes five-input-function multiplexer F5A, F5B and six-input-function multiplexer F6A, F6B. In Figure 4A, multiplexer F6A receives an input signal on west-going line F5W from the output of multiplexer F5B in Figure 4B. In Figure 4B, six-input-function multiplexer F6B receives an input signal on east-going line F5E from the output of multiplexer F5A in Figure 4A. Multiplexer F6A receives a second input signal from multiplexer F5A, and multiplexer F6B receives a second input signal from multiplexer F5B. Multiplexer F5A receives inputs from outputs 0 of function generators H and J. Multiplexer F5B receives inputs from outputs O of function generators F and G.
The CLE of this embodiment receives four extra control signals on lines BF, BH, BG, and BJ. These lines can be programmably inverted using multiplexers VF, VH, VG, and VJ, respectively, and control several useful functions . The five-input function multiplexers F5A, F5B are controlled by lines BH, BF, respectively. The six-input function multiplexers F6A, F6B are controlled by lines BJ, BG, respectively. A user can form a four-input multiplexer using multiplexer F5A and the outputs of function generators H and J, with function generators H and J each configured as a two-input multiplexer. Similarly, a four-input multiplexer can be formed using multiplexer F5B and the outputs of function generators F and G. A user can form an eight-input multiplexer using either multiplexer F6A or multiplexer F6B receiving inputs from both multiplexers F5A and F5B, each of which is receiving outputs from its respective function generators. Further, with multiplexer F5A, the memory cells in function generators H and J can operate as a 32-bit RAM. With multiplexer F5B, the memory cells in function generators F and G can operate as a 32-bit RAM. Lines BF, BH, BG, BJ serve as multiplexer control lines or RAM address lines, in addition to other functions as later described.
Registers RX, RY, RZ, RV generate outputs XQ, YQ, ZQ, VQ, respectively. Clock inputs to registers RX, RY, RZ, RV are designated by open triangles with apexes pointing into these registers. Clock enable inputs CE can be disabled using AND-gates 62A, 62B. (AND-gates 62A, 62B are controlled by a programmable memory cell that provides one of the inputs to each AND-gate.) Registers RX, RY, RZ, RV can be set or reset either synchronously or asynchronously through set port S or reset port R. (The choice of synchronous or asynchronous is made by a programmable memory cell shared between the two registers in each slice.) Set/reset input signals SRO, SRI are controlled by multiplexers 60A, 6OB and AND-gates 67A, 67B. Inputs SRO, SRI (if enabled by AND-gates 67A, 67B) can set or reset the registers. Set/reset control units R81B, R82B, R81A, R82A are programmably controlled to either set or reset registers RX, RY, RZ, RV, respectively. Registers RX, RY, RZ, RV can also be configured as latches, the choice being made by a programmable memory cell shared between the two registers in each slice.
XOR gates SF, SG, SH, SJ generate the sum portion of an addition or multiplication. Multiplexers MF, MG, MH, MJ select between signals to place onto output lines X, Y, Z, V, respectively. Multiplexers MF and MH select between the related function generator output signal, sum output signal, and five-input function multiplexer output signal. Multiplexers MG and MJ select between the related function generator output signal, sum output signal, and six-input function multiplexer output signal. The function generator F, G, H, J output signal is selected when a logical function of up to four inputs is chosen. The five-input function multiplexer F5A, F5B output signal is selected when one of a limited set of nine-input functions is chosen, including any logical function of five inputs, a 4-to-l multiplexer, and any other function that can be implemented as two four-input functions feeding a 2- to-1 multiplexer. The six-input function multiplexer F6A, F6B output signal is selected when one of a limited set of 18-input functions is chosen, including any logical function of six inputs, an 8-to-l multiplexer, and any other function that can be implemented as the output of two five-input function multiplexers F5A, F5B feeding a 2-to-l multiplexer. The sum output signal of XOR gates SF, SG, SH, SJ is selected when an appropriate arithmetic operation such as addition, subtraction or multiplication is implemented.
Multiplexers OF, OG, OH, OJ allow the carry chain to bypass the related function generator. Multiplexers OF, OG, OH, OJ select whether the respective carry multiplexer CF, CG, CH, CJ is controlled by the function generator output signal 0 or whether the carry chain bypasses the function generator by propagating the carry-in signal to the next stage along the carry chain. Multiplexers CA, CB allow additional access onto their respective carry chains by selecting either a carry-in signal CINO, CINl (buffered in this embodiment by inverters I121B and I122B, I121A and I122A, respectively) or an input signal BF, BH as the starting point for the carry chain in the CLE.
Multiplexers DF, DH select a signal to be loaded into related registers RX, RZ either from the outputs of multiplexers MF, MH, or from input signals BF, BH, respectively. Multiplexers DG, DJ select a signal to be loaded into related registers RY, RV either from the outputs of multiplexers MG, MJ, or from input signal lines BG, BJ, respectively. Multiplexers BB, BA are bypass multiplexers that can apply carry-out signals COUTO, C0UT1 to output lines YB, VB, or can forward input signals BG, BJ to output lines YB, VB to route a signal generated on one side of the CLE to a destination on the other side of the CLE. AND-gates BRB, BRA allow input signals BG, BJ to serve as se /reset signals to registers RX, RY, RZ, RV, or alternatively allows input signals BG, BJ to be decoupled from registers RX, RY, RZ, RV so that input signals BG, BJ can be used for other purposes, such as controlling multiplexers F6B, F6A or providing a DI signal to function generators G, J, without setting or resetting the registers. A logic 0 in the memory cells controlling AND-gates BRB, BRA decouples lines BG, BJ from set/reset control units R81B, R82B, R81A, R82A; while a logic 1 in the associated memory cell enables AND-gates BRB, BRA to use the signals on BG, BJ to set or reset registers RX, RY, RZ, RV as determined by set/reset control units R81B, R82B, R81A, R82A.
Summary The duplicated six-input-function multiplexer or function generator of the present invention offers the benefits of: 1) optionally implementing two different 6- input functions having five shared inputs and two shared 5- input multiplexers or function generators; 2) implementing an 8-to-l multiplexer using only four 4-input function generators; 3) optionally implementing only one 6-input function but making the output thereof available at either of two exit points on an FPGA tile boundary, thereby reducing the number of required interconnect lines; 4) optionally selecting the six-input function multiplexer or function generator with the most advantageously placed unshared input; 5) a much simpler software model, with corresponding software speed and ease of software development; and 6) approximately equal delays between corresponding nodes in the two slices of the CLE, further simplifying FPGA mapping, placing, routing, and delay estimation software. Thus it will be understood that the present invention provides a new and useful method of generating 6-input functions in an FPGA CLE, and further provides a new and useful method of implementing an 8-to-l multiplexer using only four 4-input function generators. Those having skill in the relevant arts of the invention will now perceive various modifications and additions which may be made as a result of the disclosure herein of the preferred embodiment. Accordingly, all such modifications and additions are deemed to be within the scope of the invention, which is to be limited only by the appended claims and their equivalents .

Claims

CLAIMSWhat is claimed is :
1. A Configurable Logic Element (CLE) having first and second inputs, the CLE comprising: means for generating a first 5-input function; means for generating a second 5-input function; means for generating a first 6-input function from said first input, said means for generating a first 5-input function, and said means for generating a second 5-input function; and means for generating a second 6-input function from said second input, said means for generating a first 5-input function, and said means for generating a second 5-input function.
2. A Configurable Logic Element (CLE) comprising: at least four 4-input function generators, each having at least one output; and means for combining no more than four of said function generator outputs to implement an 8-to-l multiplexer.
3. A Configurable Logic Element (CLE) comprising: a plurality of function generators each having inputs and at least one output; a plurality of carry chains, each such carry chain incorporating said outputs of at least one such function generator; and an input multiplexer having a plurality of inputs; wherein: at least one such input multiplexer input can drive through said input multiplexer at least one said input of at least one such function generator incorporated in each such carry chain.
4. A Configurable Logic Element (CLE) comprising: a plurality of function generators each having inputs and at least one output; a plurality of carry chains, each such carry chain incorporating said outputs of at least one such function generator; and an output multiplexer having a plurality of outputs; wherein: at least one such output multiplexer output can be driven through said output multiplexer by at least one said output of at least one such function generator incorporated in each such carry chain.
AMENDED CLAIMS
[received by the International Bureau on 11 May 1998 (11.05.98); original claim 2 amended; remaining claims unchanged (1 page)]
1. A Configurable Logic Element (CLE) having first and second inputs, the CLE comprising: means for generating a first 5-input function; means for generating a second 5-input function; means for generating a first 6-input function from said first input, said means for generating a first 5-input function, and said means for generating a second 5-input function; and means for generating a second 6-input function from said second input, said means for generating a first 5-input function, and said means for generating a second 5-input function.
2. (Amended) A Configurable Logic Element (CLE) comprising: at least four 4-input function generators, each having at least one output; and means for combining no more than four of said function generator outputs to implement [an] a dynamically controlled 8-to-l multiplexer.
3. A Configurable Logic Element (CLE) comprising: a plurality of function generators each having inputs and at least one output; a plurality of carry chains, each such carry chain incorporating said outputs of at least one such function generator; and an input multiplexer having a plurality of inputs; wherein: at least one such input multiplexer input can drive through said input multiplexer at least one said input of at least one such function generator incorporated in each such carry chain.
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