WO1999025015A1 - Self-cleaning etch process - Google Patents
Self-cleaning etch process Download PDFInfo
- Publication number
- WO1999025015A1 WO1999025015A1 PCT/US1998/021865 US9821865W WO9925015A1 WO 1999025015 A1 WO1999025015 A1 WO 1999025015A1 US 9821865 W US9821865 W US 9821865W WO 9925015 A1 WO9925015 A1 WO 9925015A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- chamber
- etching
- gas
- cleaning
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/905—Cleaning of reaction chamber
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98953598A EP1029345A1 (en) | 1997-11-12 | 1998-10-15 | Self-cleaning etch process |
JP2000519917A JP2001523044A (en) | 1997-11-12 | 1998-10-15 | Automatic cleaning etching process |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/969,122 | 1997-11-12 | ||
US08/969,122 US6136211A (en) | 1997-11-12 | 1997-11-12 | Self-cleaning etch process |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999025015A1 true WO1999025015A1 (en) | 1999-05-20 |
Family
ID=25515212
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/021865 WO1999025015A1 (en) | 1997-11-12 | 1998-10-15 | Self-cleaning etch process |
Country Status (6)
Country | Link |
---|---|
US (2) | US6136211A (en) |
EP (1) | EP1029345A1 (en) |
JP (1) | JP2001523044A (en) |
KR (1) | KR100530246B1 (en) |
TW (1) | TW506019B (en) |
WO (1) | WO1999025015A1 (en) |
Cited By (7)
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EP1087423A2 (en) * | 1999-09-24 | 2001-03-28 | Applied Materials, Inc. | Method for etching films on substrates, for cleaning etch chambers, and apparatus therefore |
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WO2002025728A2 (en) * | 2000-09-21 | 2002-03-28 | Infineon Technologies North America Corp. | Dual thickness gate oxide fabrication method using plasma surface treatment |
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Also Published As
Publication number | Publication date |
---|---|
JP2001523044A (en) | 2001-11-20 |
EP1029345A1 (en) | 2000-08-23 |
US6136211A (en) | 2000-10-24 |
KR100530246B1 (en) | 2005-11-22 |
TW506019B (en) | 2002-10-11 |
US6699399B1 (en) | 2004-03-02 |
KR20010032030A (en) | 2001-04-16 |
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