WO1999044113A3 - Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices - Google Patents

Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices Download PDF

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Publication number
WO1999044113A3
WO1999044113A3 PCT/US1999/004247 US9904247W WO9944113A3 WO 1999044113 A3 WO1999044113 A3 WO 1999044113A3 US 9904247 W US9904247 W US 9904247W WO 9944113 A3 WO9944113 A3 WO 9944113A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory devices
nonvolatile memory
information
flash memory
sectors
Prior art date
Application number
PCT/US1999/004247
Other languages
French (fr)
Other versions
WO1999044113A9 (en
WO1999044113A2 (en
Inventor
Petro Estakhri
Berhanu Iman
Original Assignee
Lexar Media Inc
Petro Estakhri
Berhanu Iman
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=21855540&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO1999044113(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Lexar Media Inc, Petro Estakhri, Berhanu Iman filed Critical Lexar Media Inc
Priority to EP10012048.4A priority Critical patent/EP2306321B1/en
Priority to AU29750/99A priority patent/AU2975099A/en
Priority to JP54391299A priority patent/JP3792259B2/en
Priority to EP99911004A priority patent/EP0983550A4/en
Publication of WO1999044113A2 publication Critical patent/WO1999044113A2/en
Publication of WO1999044113A3 publication Critical patent/WO1999044113A3/en
Publication of WO1999044113A9 publication Critical patent/WO1999044113A9/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/102External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0613Improving I/O performance in relation to throughput
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638Organizing or formatting or addressing of data
    • G06F3/064Management of blocks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658Controller construction arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/08Address circuits; Decoders; Word-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/76Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G11C29/765Masking faults in memories by using spares or by reconfiguring using address translation or modifications in solid state disks
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/82Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7203Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7208Multiple device management, e.g. distributing data over multiple flash devices

Abstract

The present invention includes a digital system (600) having a controller semiconductor device (510) coupled to a host (504) and a nonvolatile memory bank (506) including a plurality of nonvolatile memory devices (670, 672). The controller transfers information, organized in sectors, with each sector including a user data portion and an overhead portion, between the host and the nonvolatile memory bank and stores and reads two bytes of information relating to the same sector simultaneously within two nonvolatile memory devices. Each nonvolatile memory device is defined by a row of memory locations wherein corresponding rows of at least two semiconductor devices maintain two sectors of information therein with the overhead information related to the two sectors maintained in one of the memory rows of the nonvolatile memory device. Thirty two sectors of information define a block identified by a virtual physical block address with a block of information expanding between two memory devices.
PCT/US1999/004247 1998-02-25 1999-02-25 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices WO1999044113A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP10012048.4A EP2306321B1 (en) 1998-02-25 1999-02-25 Increasing memory performance in flash memory devices by performing simultaneous write operation to multiple devices
AU29750/99A AU2975099A (en) 1998-02-25 1999-02-25 Increasing memory performance in flash memory devices by performing simultaneouswrite operation to multiple devices
JP54391299A JP3792259B2 (en) 1998-02-25 1999-02-25 Increased memory performance in flash memory devices by simultaneous write operations to multiple devices
EP99911004A EP0983550A4 (en) 1998-02-25 1999-02-25 Increasing memory performance in flash memory devices by performing simultaneous write operation to multiple devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/030,697 1998-02-25
US09/030,697 US6081878A (en) 1997-03-31 1998-02-25 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

Publications (3)

Publication Number Publication Date
WO1999044113A2 WO1999044113A2 (en) 1999-09-02
WO1999044113A3 true WO1999044113A3 (en) 1999-10-07
WO1999044113A9 WO1999044113A9 (en) 1999-11-11

Family

ID=21855540

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/004247 WO1999044113A2 (en) 1998-02-25 1999-02-25 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

Country Status (5)

Country Link
US (4) US6081878A (en)
EP (2) EP0983550A4 (en)
JP (6) JP3792259B2 (en)
AU (1) AU2975099A (en)
WO (1) WO1999044113A2 (en)

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