WO1999047937A3 - Flexible test environment for automatic test equipment - Google Patents

Flexible test environment for automatic test equipment Download PDF

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Publication number
WO1999047937A3
WO1999047937A3 PCT/US1999/005953 US9905953W WO9947937A3 WO 1999047937 A3 WO1999047937 A3 WO 1999047937A3 US 9905953 W US9905953 W US 9905953W WO 9947937 A3 WO9947937 A3 WO 9947937A3
Authority
WO
WIPO (PCT)
Prior art keywords
test
steps
nodes
flexible
environment
Prior art date
Application number
PCT/US1999/005953
Other languages
French (fr)
Other versions
WO1999047937A2 (en
Inventor
Peter L Hansen
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Priority to IL13853999A priority Critical patent/IL138539A0/en
Priority to AU30103/99A priority patent/AU3010399A/en
Priority to KR1020007010392A priority patent/KR20010042050A/en
Publication of WO1999047937A2 publication Critical patent/WO1999047937A2/en
Publication of WO1999047937A3 publication Critical patent/WO1999047937A3/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31912—Tester/user interface
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture

Abstract

A flexible test environment (250) for automatic test equipment, whereby sequences of steps for developing and executing test programs are specified using hierarchical trees (254-258) of nodes. The nodes in one tree (254) include end leaves that correspond with the test program development steps, and the nodes in another tree (256) include end leaves that correspond with the test program execution steps. Further, the end leaves in both trees have a plurality of associated properties, which are used for specifying test program flow and for indicating methods to be called when the steps are executed. The test environment can be easily adapted to a distributed tester architecture.
PCT/US1999/005953 1998-03-20 1999-03-18 Flexible test environment for automatic test equipment WO1999047937A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IL13853999A IL138539A0 (en) 1998-03-20 1999-03-18 Flexible test environment for automatic test equipment
AU30103/99A AU3010399A (en) 1998-03-20 1999-03-18 Flexible test environment for automatic test equipment
KR1020007010392A KR20010042050A (en) 1998-03-20 1999-03-18 Flexible test environment for automatic test equipment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/045,436 US6128759A (en) 1998-03-20 1998-03-20 Flexible test environment for automatic test equipment
US09/045,436 1998-03-20

Publications (2)

Publication Number Publication Date
WO1999047937A2 WO1999047937A2 (en) 1999-09-23
WO1999047937A3 true WO1999047937A3 (en) 1999-11-04

Family

ID=21937861

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/005953 WO1999047937A2 (en) 1998-03-20 1999-03-18 Flexible test environment for automatic test equipment

Country Status (5)

Country Link
US (2) US6128759A (en)
KR (1) KR20010042050A (en)
AU (1) AU3010399A (en)
IL (1) IL138539A0 (en)
WO (1) WO1999047937A2 (en)

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Also Published As

Publication number Publication date
WO1999047937A2 (en) 1999-09-23
KR20010042050A (en) 2001-05-25
AU3010399A (en) 1999-10-11
US6128759A (en) 2000-10-03
IL138539A0 (en) 2001-10-31
US6449744B1 (en) 2002-09-10

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