WO1999062172A1

WO1999062172A1 - Phase-locked loops

Info

Publication number: WO1999062172A1
Application number: PCT/GB1999/001393
Authority: WO
Inventors: Neil Andrew Mcdonald; Melvin Paul Clarkson
Original assignee: Marconi Communications Limited
Priority date: 1998-05-23
Filing date: 1999-05-05
Publication date: 1999-12-02
Also published as: GB2337649A; GB2337649B; AU3722599A; GB9811108D0

Abstract

A phase-locked loop having a phase detector and a voltage controlled oscillator is provided for a smart card. The voltage controlled oscillator has a comparator (40), a switch (48) and a capacitor (50). The capacitor (50) charges when the switch (48) is open. When an input voltage (44) and a reference voltage (46), both of which are supplied to the comparator (40), are equal, the comparator (40) produces an output signal (42) to close the switch (48) and discharge the capacitor (50). Between an input to the comparator (40) which is used to supply it with the input voltage (44) and the capacitor (50) there is provided a resistor (66). Voltage is dropped across the resistor (66) so that the comparator (40) produces the output signal (42) when the sum of the voltage drop and voltage at the capacitor (50) equals the reference voltage (66). In this way, delays within the voltage controlled oscillator can be compensated for an ideal operation across its frequency range can be obtained.

Description

PHASE-LOCKED LOOPS

This invention relates to phase-locked loops. It is particularly, but not

exclusively, related to a phase-locked loop located in a portable token, for example a

card, which is used to perform a transaction.

Contactless tokens work on, or close to, a terminal which provides power. This

power is supplied via a RF (radio frequency) induction field which is referred to as a

carrier field. In compliance with international standards a widely used carrier field

frequency is 13.56MHz. Power is transferred from an aerial in the terminal to an aerial

on the token and is akin to the terminal being a primary coil of a transformer and the

token being a secondary coil. Current induced in the token aerial is used to obtain an

unregulated DC voltage in the token. Power and data from the terminal are obtained

from this unregulated DC voltage. In particular embodiments both the terminal and the token each have a single aerial each of which may comprise a coil having one or more

turns.

As well as power being transmitted from the terminal to the token, data is

transmitted from the terminal to the token and vice versa. The exchange of data is used

to perform a transaction. To transmit data to the token the terminal modulates it onto

the carrier field. To transmit data to the terminal the token switches an impedance, such

as a resistance, to modulate the amplitude of the carrier field at the teirninal as the token

draws extra power from the terminal aerial due to switching action. A schematic

representation of a transaction system is shown in Figure 1 which shows a transaction

system comprising a terminal 2 and a token, for example a contacdess smart card, 3.

Communication between the terminal 2 and the token 3 occurs across an inductive coupling comprising a terminal coil 4 and a token coil 5. Signals received by the token coil 5 are rectified and then demodulated in a

demodulator 6. A phased-locked loop 10 is used to obtain a clean version of the

demodulated signal and a data detector 7 is used to detect any data present on the

demodulated signal. As is discussed below, the demodulated signal may comprise a

signal which is used to derive a clock for the token. The demodulated signal and the

data are supplied to a microprocessor 8. To transmit data from the token 3 to the

terminal 2, the switch 9, under control of the microprocessor, switches an impedance

into and out of circuit. The frequency at which the impedance is switched, that is the

switch tone, is derived from the carrier field. The switch tone is typically a sixteenth of

the carrier field frequency, that is 13.56MHz ÷ 16 = 847kHz. Operation of the token 3

is more fully explained in GB9801442.6. In the following description it is assumed that

such a clock tone is modulated onto the carrier field. Of course, it need not be.

It is preferred to derive a clock for the token from a clock signal provided by the terminal. Although the token clock can be derived directly from the carrier field, a more

flexible token/terminal interface can be obtained if the clock is obtained from a clock

signal provided as a separate clock tone which is modulated onto the carrier field. A

transaction system operating in this way is described in UK patent application

GB9706019.8.

Amplitude modulation is typically used by the terminal to send the data and the

clock tone. Alternatively, frequency modulation (FM) and phase modulation (PM) may

be used. Of these two, PM is preferred because it is easier to meet requirements of RFI

regulations.

The unregulated voltage generated in the token has modulated on it data and the clock tone. The unregulated voltage is regulated by a regulator to provide power for the token. A signal representative of the data and the clock tone is extracted from the

unregulated voltage by a demodulator circuit. A rectifier could additionally be used in

this task. The extracted signal is fed into a phase-locked loop (PLL). This locks on to

the clock tone frequency. Since it contains a divider (÷n) in its feedback loop the input

tone is multipUed (xn) to provide a suitably high clock frequency for a processor on the

token. If the data is present as a PM on the clock tone, the PLL can also obtain the data

from the extracted signal.

Typical frequencies for the clock tone are from 125kHz to 625kHz. If a divider

of eight is used in the PLL to provide the clock for the token, this provides a clock in the

range lMHz to 5MHz.

In the following description a phase-locked loop and a voltage controlled oscillator are described. Although they are specifically discussed in relation to

contactless tokens, it will be apparent that the principles underlying the invention apply

to phase-locked loops and voltage controlled oscillators generally, and particularly to

their use in integrated circuits where external control and compensation are not easy to

achieve.

A known phase-locked loop (PLL) 10 is shown in Figure 2. A phase detector

12 receives an input signal 14 and a feedback signal 16 and, if there is a phase

difference, produces an error signal 18. Once it has been cleaned by a filter 20 to

remove high frequency noise, it is provided to a voltage controlled oscillator (NCO) 22

as a NCO input voltage V_vco 24. The VCO 22 produces a NCO output signal 26 having

a frequency which is dependent on the V_vco 24. The VCO 22 is configured such that the

VCO output signal 26 produced is 16 times the resultant feedback signal 16, that is approximately 16 times the input signal 14. The VCO output signal 26 passes through a divider 28 which divides it by two to produce a signal 30 generally suitable for use as

a clock. The VCO signal 26 is then further divided by eight by a divider 32 to produce

the feedback signal 16. When used in a token, the input signal 14 is the output of the

demodulator 6 which extracts the clock tone from the unregulated voltage generated in

the token 3.

The VCO 22 is shown in greater detail in Figure 3. In essence the VCO 22

operates by using a comparator 40 to generate a switch control signal 42 when a

comparator voltage 44 reaches the level of a reference voltage V ^46. Production of

the switch control signal 42 causes a switch 48 to close. This causes a capacitor 50 to

discharge thus causing the comparator voltage 44 to fall. The comparator voltage 44

therefore falls to a value below V_REF 46, (at which point the capacitor 50 is almost fully discharged) and so the switch control signal 42 is no longer produced and the switch 48

opens. Once the switch 42 has opened, the capacitor 50 begins to charge which causes

the comparator voltage 44 to rise towards V_REP 46. If a constant current I flows into the

capacitor 50 it charges linearly. Repeated charging and discharging of the capacitor 50

causes the comparator 40 to produce a series of feedback pulses whic are used as a

VCO output signal 52. It should be noted that the VCO output signal 52 in Figure 3 is

equivalent to the VCO output signal 26 in Figure 2.

The VCO 22 is provided with a constant current source. In this embodiment of

a voltage controlled oscillator, the current source comprises a PMOS FET 58 having a

high input impedance and a resistor 56. V _vco 24 is applied to the gate of the FET 58.

The source terminal of the FET 58 is connected to the resistor 56 whose other terminal

is connected to a positive supply voltage (V_supply) 54. Therefore the voltage across the

resistor 56 is V_supply -V_gs-V_vco, where V_gs is the voltage across the gate and source terminals of the FET 58. Therefore, the current I supplied to the capacitor 50 is equal

to the current through the resistor 56 which is linearly proportional to V _vco 24 since

V_supply and V_gs are constant. In this case as V_vco 24 is increased the current I that flows

decreases and the time it takes to charge the capacitor 50 increases. As a result the

frequency of the VCO output 52 decreases. Therefore, in this case the VCO has a

negative gain, that is a decrease in V_vco causes the frequency of the VCO output 52 to

increase and vice versa.

Assuming the VCO is ideal and that there is no time delay in the VCO 22, the

time period of oscillation t_p is

cv R,EF t = (1) p

where C is the capacitance of the capacitor 50. However the VCO is not ideal and will have a time delay t-j , sometimes referred to as an amplifier delay, caused by time taken

for the comparator 40 and the switch 48 to respond. Therefore the real time period of

oscillation t_ is t_p+t_d .

Detection of data by the PLL 10 is discussed in relation to Figures 4 and 5 which

show detection of a single item of data which is modulated on the carrier field, and

therefore on the clock tone, by PM. Assuming steady state, the frequencies of the VCO

output signal 26 matches the input signal 14 multiplied by the value n, that is 16, of the

dividers 28 and 32. As the phase of the input signal 14 suddenly changes due to the

presence of the item of data, the error signal 18 is generated by the phase detector 12.

Once the error signal has been suitably filtered by the high frequency filter 20, it is applied to the VCO 22 which causes the frequency of the VCO output 52 to change temporarily to correct the phase difference. Similar principles apply to frequency

modulation (FM), which results in the frequency changing.

However, the time delay t_d of the VCO 22 prevents the VCO output signal 26

from changing linearly with V_vco 24.

If the input signal 14 is of high frequency, then the sampling rate of the phase

detector 12 is high. This is simply because at a high frequency there will be a larger

number of phase differences detected per second than at a low frequency. Conversely,

if the input signal 14 is of lower frequency, then the sampling rate of the phase detector

12 is lower. The settling time of the changed VCO output signal 26 depends on the gain

of the PLL which depends on the gain of its constituent parts. The phase detector 12

and the divider 28 and 32 have fixed gains with respect to frequency.

Referring specifically to Figure 4, if the input signal 14 is of low frequency, and therefore the sampling rate of the phase detector 12 is low, then a high VCO gain is

undesirable. On receiving a modulation of the input signal 14 the phase detector 12

produces the error signal 18 and provides a filtered input to the VCO 22. However, with

a low sampling rate, the VCO 22 tends to overshoot and undershoot thus providing an

oscillatory response until the VCO 22 settles at a frequency matched to that of the input

signal 14.

Figure 5 shows how this problem is reduced if the VCO 22 has a low gain.

Although the phase detector 12 still samples at a low rate, the VCO output 52 does not

increase so quickly and so does not tend to overshoot and undershoot to the same

degree. Therefore, the oscillatory response of the VCO 22 is damped relative to a high

gain VCO.

If the input signal 14 is of high frequency, the sampling rate of the phase detector 12 is high and a high gain VCO 22 can be used since there is much less tendency to

overshoot. As a result the settling time of the PLL 10 is lower. This allows high baud

rates in which phase modulation of the clock tone by data is more rapid, for example,

106kbaud for data with the clock tone having its phase changed every six cycles of tone.

If the gain of the VCO 22 was lower it would increase the settling time by over damping

the response and so would lower the maximum data transmission rate possible between

the terminal 2 and the token 3.

Therefore, in order for the PLL 10 to detect data from the modulated input signal

14 efficientiy it is desirable for the VCO 22 to have a high gain at high frequencies and

a low gain at low frequencies. This is shown in Figure 6. However, the response of a

typical VCO 22 is shown in Figure 7. The time delay t_d is not significant at lower frequencies because it is small relative to the time period t_p . However, at higher frequencies, the capacitor is charging and discharging at a higher rate. Therefore, as the

frequency becomes larger, t_p becomes smaller and t_d dominates. As V_vco 24 tends to

zero, the frequency tends to l/t_d.

According to a first aspect of the invention there is provided a voltage controlled

oscillator comprising a comparator, a switch and a charge storage means, the comparator

being arranged to produce an output signal to activate the switch and discharge the

charge storage means when an input voltage and a reference voltage have a pre-

determined relationship, wherein, in use, a voltage drop is provided between an input

of the comparator and the charge storage means such that the comparator produces the

output signal when the sum of the voltage drop and a voltage across the charge storage

means has the predetermined relationship to the reference voltage. Preferably the predetermined relationship is that the input voltage is equal to the

reference voltage.

Preferably a current supply is used to control the oscillator frequency which is

derived from a voltage signal across an input resistor.

Preferably the voltage signal is filtered to remove high frequency noise.

Preferably the presence of the voltage drop means that the voltage at the charge

storage means only has to reach a value equal to the reference voltage minus the voltage

drop in order for the output signal to be produced. A practical effect of this may be that

the charge storage means requires a lower voltage to have been built up before it is

discharged. As a result the charge storage means may charge and discharge more quickly than in the absence of the voltage drop. If the value of the voltage drop is chosen correctly, the time period saved in charging of the charge storage means is

substantially equal to the time delay, that is the comparator delay, which causes non- ideal operation of the voltage controlled oscillator. In this way the time delay can be

substantially compensated for and an ideal input voltage/output frequency characteristic

produced. Alternatively, the time delay can be over or under-compensated for to

produce a desirable non-ideal characteristic.

Conveniently the charge storage means comprises a capacitor.

According to a second aspect of the invention there is provided a phase-locked

loop comprising a phase detector and a voltage controlled oscillator according to the

first aspect of the invention.

According to a third aspect of the invention there is provided a token comprising

a phase-locked loop according to the second aspect of the invention.

According to a fourth aspect of the invention there is provided a transaction system comprising a terminal and at least one token according to the third aspect of the

invention.

An embodiment of the invention will now be described by way of example only

with reference to the accompanying drawings in which:

Figure 1 shows a transaction system;

Figure 2 shows a phase-locked loop;

Figure 3 shows a voltage controlled oscillator;

Figure 4 shows a time/input voltage characteristic of a voltage controlled

oscillator; Figure 5 shows a modified time/input voltage characteristic of a voltage

controlled oscillator;

Figure 6 shows a desired input voltage/output frequency characteristic of a

voltage controlled oscillator;

Figure 7 shows a typical input voltage/output frequency characteristic of a

voltage controlled oscillator according to the prior art; and

Figure 8 shows a voltage controlled oscillator according to the invention.

Figures 1 to 7 have been described above.

Figure 8 shows a schematic VCO 60 according to the invention. It shares a

number of features in common with the VCO 22 described in relation to Figure 3 and

so corresponding features have been given corresponding reference numerals.

The VCO 60 is provided with a constant current source as described in relation

to Figure 3. In order to compensate for the time delay t_d , the VCO 60 has a resistor 66

having a resistance R_c. Since a constant current is flowing through a fixed resistance there is a fixed voltage V_R across the resistor 66 equal to I_CR_C. In operation, the time period of oscillation t_p is equal to the time taken for the voltage across the capacitor 50,

V_c , to reach such a value so as to increase the comparator voltage 44 to be equal to V_REF

46. Therefore, since there is a fixed voltage across the resistor 66, it takes less time for

V_c to reach a value sufficiently high such that the comparator voltage 44 equals

46.

In order to trigger the comparator 40 and cause a switch control signal 42 to be

produced, the sum of V_c and V_R must equal to V^, that is the trigger voltage of the

comparator 40. Therefore V_REF = V_R + V_c = I_CR_C + V_c.

Adapting equation 1 above, the real time period t_ris

CV_r t = +t_

. C{V_REF -I_CR_C) ^

I ^'d

CV REF

-CR_C +t_d

Therefore, if the magnitude of the expression CR_cis equal to t_d, that is if an

appropriate value of R_c is chosen, the time delay t_d in the VCO 60 is compensated for

by the capacitor 50 charging more quickly because it only needs to charge from ground

to V_REP-V_R in order to trigger the comparator 40. The time delay t_d due to the

comparator 40 and the switch 48 is in the order of 20ns. If the capacitor 50 has a

capacitance of lpf, the resistor 66 should have a value of 20kΩ to compensate fully for Use of an appropriate value of Rc provides a VCO 60 with a constant gain over

a range of frequencies. Referring back to the original problem, it is desired for a VCO

to have the input voltage/output frequency characteristic shown in Figure 6. If the

resistance value of the resistor 66 is increased further, the delay t_dis overcompensated

for and the equivalent of a negative delay -t_n (where t_n = t_d- CR_C) is provided. This

leads to a real time of oscillation t_r= t_p -t_π, where t_n is constant and t_p is varied under

control. Therefore, as t_p is reduced and approaches t__ the frequency will increase rapidly

thus resulting in a larger gain. Where t_p is large with respect to the magnitude of t_, , -t,, has little effect and so the gain becomes approximately constant.

Claims

1. A voltage controlled oscillator comprising a comparator, a switch and a charge

storage means, the comparator being arranged to produce an output signal to

activate the switch and discharge the charge storage means when an input

voltage and a reference voltage have a pre-determined relationship, wherein, in

use, a voltage drop is provided between an input of the comparator and the

charge storage means such that the comparator produces the output signal when

the sum of the voltage drop and a voltage across the charge storage means has

the predetermined relationship to the reference voltage.

2. An oscillator according to Claim 1, wherein the predetermined relationship is that the input voltage is equal to the reference voltage.

3. An oscillator according to any one of the preceding claims, wherein the value of the voltage drop is chosen such as to produce a desired gain characteristic of the

oscillator.

4. An oscillator according to Claim 3, characterised in that the oscillator has one

or more associated internal time delays and in that the value of the voltage drop

is chosen such as to compensate for the one or more internal time delays.

5. An oscillator according to any one of the preceding claims, wherein the charge

storage means comprises a capacitor.

6. An oscillator according to Claim 4, wherein the charge storage means is a

capacitor and a resistor is provided in series with the capacitor to produce the

voltage drop, a product of a capacitance value of the capacitor and a resistance

value of the resistor being chosen to substantially equal the time-delay value of

the one or more internal time delays.

7. An oscillator according to any one of the preceding claims, wherein a current

supply is used to control the oscillator frequency, the current supply being

derived from a voltage signal across an input resistor.

8. An oscillator according to Claim 7, wherein the voltage signal is filtered to remove high frequency noise.

9. An oscillator substantially as described herein with reference to Figures 6 and

8 of the accompanying drawings.

10. A phase-locked loop comprising a voltage controlled oscillator according to any

one of the preceding claims, and a phase detector.

11. A phase-locked loop substantially as described herein with reference to Figures

2, 6 and 8 of the accompanying drawings.

12. A token comprising a phase-locked loop according to Claim 10 or Claim 11.

13. A token substantially as described herein with reference to Figures 1, 2, 6 and

8 of the accompanying drawings.

14. A transaction system comprising a terminal and at least one token according to

Claim 12 or Claim 13.

15. A transaction system substantially as described herein with reference to Figures 1, 2, 6 and 8 of the accompanying drawings.