WO2000013382B1 - Feher keying (fk) modulation and transceivers including clock shaping processors - Google Patents

Feher keying (fk) modulation and transceivers including clock shaping processors

Info

Publication number
WO2000013382B1
WO2000013382B1 PCT/US1999/019909 US9919909W WO0013382B1 WO 2000013382 B1 WO2000013382 B1 WO 2000013382B1 US 9919909 W US9919909 W US 9919909W WO 0013382 B1 WO0013382 B1 WO 0013382B1
Authority
WO
WIPO (PCT)
Prior art keywords
clock
signal
shaped
data
clock signals
Prior art date
Application number
PCT/US1999/019909
Other languages
French (fr)
Other versions
WO2000013382A1 (en
Inventor
Kamilo Feher
Original Assignee
Kamilo Feher
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kamilo Feher filed Critical Kamilo Feher
Priority to AU57964/99A priority Critical patent/AU5796499A/en
Priority to CA002341883A priority patent/CA2341883A1/en
Priority to EP99945351A priority patent/EP1110356A4/en
Publication of WO2000013382A1 publication Critical patent/WO2000013382A1/en
Publication of WO2000013382B1 publication Critical patent/WO2000013382B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4902—Pulse width modulation; Pulse position modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0004—Modulated-carrier systems using wavelets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/70703—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation using multiple or variable rates
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2637—Modulators with direct modulation of individual subcarriers

Abstract

Ultra high spectral efficient Feher Keying (FK) Modulation and Demodulation (Modem), Baseband Processing (BBP), Intermediate Frequency (IF) and Radio Frequency (RF) signal generation and processing methods and implementations, including Clock Modulated (CM) and Shaped Clocked (SC) Transmitters-Receivers (Transceivers) are disclosed. In the FK modulator, specified clock converted and clock shaped signal parameters are generated. These are based on the input data signal patterns (1.1) and are generated by means of control signals (1.11), which are designed in the data input signal interface data signal and/or clock signal encoder units (1.8). The selectable clock signal parameters include symmetrical and non-symmetrical clock signals, shaped band-limited continuous clock signal patterns, shaped encoded clock signals, variable rise and fall time clock signals, clock signals having adjustable on and off duration, multilevel and shaped clock signals and asynchronous clock signal information transmission means, where asynchronous clocking (1.3, 1.4) is referenced to the incoming data source signals (1.1).

Claims

AMENDED CLAIMS[received by the International Bureau on 9 March 2000 (09.03.00); original claims 1 , 2, 3 and 14 amended; new claims 15-27 added; remaining claims unchanged (6 pages)]
1. A structure comprising: a shaped clock signal generator receiving a data signal having a data bit rate and generating a shaped clock signal, said shaped clock signal generator being synchronous or asynchronous with the data bit rate of the received data signal ; and a data signal processor having a receiver port and a control signal generation means for selecting the shaped clock signal for further transmission and/or modulation.
2. A structure comprising: a splitter receiving an input signal and splitting said input signal into a plurality of signal streams; a clock generator receiving one of said plurality of signal streams and generating a clock signal; at least one shaped clock generator means receiving said clock signal and generating at least one shaped clock signal; a set of input ports for receiving said at least one shaped clock signal; a selector switch for selecting a particular one of the shaped clock signals, said selector switch having a first input interface port coupled to receive data-based selection control signals, and a set of input ports coupled to the shaped clock signals; and an output interface port coupled to said selector switch output.
3. A system architecture for use with a transmitter, said system architecture comprising: a data input interface for receiving input data and for generating an input data based clock selector signal; a plurality of input ports for receiving a plurality of clock signals including shaped clock signals and unshaped clock signals; a set of one or more clock generators generating processed clock signals, at least some of which processed clock signals differing from each other in one or more clock parameters; a selector switch for selecting a particular one of said processed clock signals; and a data interface output port for receiving said selected processed clock signal and communicating it to said transmitter.
4. A structure comprising: a clock generator which provides clock signals to two or more clock transition time shifting and clock shaping signal generators; a data input port and connection to a data interface input encoder for the generation of clock selector data signal by said data input interface encoder; a switch to choose, based on said clock selector data signal, one of the clock transition time-shifted shaped clock signals and connect the selected signal to the data interface output unit; and a data interface output unit for connecting the selected signal to the transmission medium or further signal processing.
5. A transmit signal processor structure comprising: a first clock signal generator having a first set of clock shaping parameters; a second clock signal generator having a second set of clock shaping parameters, said second set of clock shaping parameters having at least one parameter different from that of the first set of clock signal shaping parameters; a data input receive circuitry and processor for selection of one of the said first or second clock shaped signals; a switch for switching between the first set and second set of shaped clock parameters; and an output interface port to provide the selected signal to the transmission medium.
6. A spectral saving data and clock signal processing system comprising: data signal and clock signal processing means to provide a clock modulated signal having changeable distances between the rising edges and falling edges of the modulated clock signals; and control means having its input connected to the data signal source and its output connected to edge distance switch selection means; and digital interface output means to connect the clock modulated signal to the interface of the subsequent signal processor.
7. A clock signal modulator comprising: a data input interface means to provide data signals to an asynchronous pure clock source; an asynchronous pure clock generator means to provide a pure clock signal; and a selector switch means which is controlled by the data interface means to provide a shorter distance between the falling edge and rising edge of the clock modulated signal for a zero state data signal and a longer distance between the falling edge and rising edge of the clock modulated signal for a one-state data signal.
8. A clock converter system comprised of: an input data interface means for controlling the selection process of the shaped clock signal which is provided to the interface output unit means; a clock signal shaping means to provide smoothed continuous clock signals to the clock signal selection means having one or more different clock signal parameters; and an output signal processing means to accept the smoothed different clock signal parameter processed clock converted signals.
9. A clock modulated signaling system comprising: an input data interface means to provide control signal generation and selection means of shaped clock signals; an interface means to provide signal processing means for modulating the clock modulated baseband signal by means of a cross-correlated quadrature modulator system; an output amplifier means to connect the cross-correlated quadrature modulated signal to the transmission medium; demodulation means to demodulate the received quadrature modulated signal; and signal processor means to decode and regenerate the clock modulated signal.
10. An architecture comprising: a data interface input for receiving input data and for providing an input data-based clock selector data signal; a set of input ports for receiving a set of shaped clock signals and of not-shaped clock signals; a set of one or more clock generators which differ from each other in one or more clock parameters; a selector switch for selecting one of the processed clock signals; and a data interface output port for receiving said selected signal and providing it to the transmitter circuitry.
11. A method comprising steps: receiving a data signal; generating a shaped clock signal in response to said received data signal; generating a control signal for selecting said generated shaped clock signal; and processing said selected shaped clock signal for transmission or modulation.
12. The method in Claim 11 , wherein said shaped clock signal is generated synchronously with a data bit rate of said received data signal.
13. The method in Claim 11, wherein said shaped clock signal is generated asynchronously with a data bit rate of said received data signal.
14. A method of signaling using clock modulated signals, said method comprising: selecting at least one shaped clock signal; cross-correlating and quadrature modulating said selected at least one shaped clock signal; amplifying said cross-correlated quadrature modulated shaped clock signal; transmitting said amplified cross-correlated quadrature modulated shaped clock signal; receiving said transmitted amplified cross-correlated quadrature modulated shaped clock signal; demodulating said received shaped clock signal; and decoding said received demodulated shaped clock signal and regenerating said selected shaped clock signal.
15. The method of signaling in claim 14, wherein said shaped clock signals are selected from the group consisting of: shaped symmetrical clock signals, shaped non-symmetrical clock signals, two-level non- symmetrical clock signals, multilevel non-symmetrical clock signals, variable rise and different non-symmetrical fall time clock signals, asynchronous clock signal information, and combinations thereof.
16. The method of signaling in claim 14, wherein said shaped clock signals include clock signals having sinusoidal and square wave components.
17. The method of signaling in claim 14, wherein said shaped clock signals include clock signals having at least one first shaped clock having a longer duration relative to a second shaped clock and said second shaped clock having a shorter duration relative to said first shaped clock.
18. The method of signaling in claim 14, wherein said shaped clock signals include clock signals having at least one shaped clock having a rounded-off longer duration and a second shaped clock having a shaped rounded-off shorter duration.
19. The method of signaling in claim 14, wherein said shaped clock signals include clock signals having variable amplitude clock levels, and wherein a first clock level is used for a 1 logical state and a second clock level is used for a 0 logical state of quadrature I and Q signal patterns.
20. The method of signaling in claim 14, wherein said shaped clock signals include clock signals having a longer than 50% high state duration for the one state data and a shorter than 50%o high state duration for the zero state data.
21. A system comprising: a shaped clock signal generator receiving a data signal having a data bit rate and generating a shaped clock signal, said shaped clock signal generator being either synchronous or asynchronous with the data bit rate of the received data signal; and a data signal processor having a receiver port and a control signal generation circuit for selecting said shaped clock signal.
22. The system in claim 21 , wherein said shaped clock signals are selected from the group consisting of: shaped symmetrical clock signals, shaped non-symmetrical clock signals, two-level non-symmetrical clock signals, multilevel non-symmetrical clock signals, variable rise and different non-symmetrical fall time clock signals, asynchronous clock signal information, and combinations thereof.
23. The system in claim 21, wherein said shaped clock signals include clock signals having sinusoidal and square wave components.
24. The system in claim 21 , wherein said shaped clock signals include clock signals having at least one first shaped clock having a longer duration relative to a second shaped clock and said second shaped clock having a shorter duration relative to said first shaped clock.
25. The system in claim 21 , wherein said shaped clock signals include clock signals having at least one shaped clock having a rounded-off longer duration and a second shaped clock having a shaped rounded-off shorter duration.
26. The system in claim 21, wherein said shaped clock signals include clock signals having variable amplitude clock levels, and wherein a first clock level is used for a 1 logical state and a second clock level is used for a 0 logical state of quadrature I and Q signal patterns.
27. The system in claim 21, wherein said shaped clock signals include clock signals having a longer than 50% high state duration for the one state data and a shorter than 50% high state duration for the zero state data.
PCT/US1999/019909 1998-08-31 1999-08-30 Feher keying (fk) modulation and transceivers including clock shaping processors WO2000013382A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU57964/99A AU5796499A (en) 1998-08-31 1999-08-30 Feher keying (fk) modulation and transceivers including clock shaping processors
CA002341883A CA2341883A1 (en) 1998-08-31 1999-08-30 Feher keying (fk) modulation and transceivers including clock shaping processors
EP99945351A EP1110356A4 (en) 1998-08-31 1999-08-30 Feher keying (fk) modulation and transceivers including clock shaping processors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9861298P 1998-08-31 1998-08-31
US60/098,612 1998-08-31

Publications (2)

Publication Number Publication Date
WO2000013382A1 WO2000013382A1 (en) 2000-03-09
WO2000013382B1 true WO2000013382B1 (en) 2000-05-11

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Country Status (5)

Country Link
US (3) US6198777B1 (en)
EP (1) EP1110356A4 (en)
AU (1) AU5796499A (en)
CA (1) CA2341883A1 (en)
WO (1) WO2000013382A1 (en)

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US7245668B2 (en) 2007-07-17
US20060088121A1 (en) 2006-04-27
EP1110356A4 (en) 2003-05-28
US20010016013A1 (en) 2001-08-23
US6198777B1 (en) 2001-03-06
CA2341883A1 (en) 2000-03-09
US7035344B2 (en) 2006-04-25
WO2000013382A1 (en) 2000-03-09
EP1110356A1 (en) 2001-06-27
AU5796499A (en) 2000-03-21

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