WO2000019530A1

WO2000019530A1 - Vertical field effect transistor with an interior gate and method for producing the same

Info

Publication number: WO2000019530A1
Application number: PCT/DE1999/003139
Authority: WO
Inventors: Thoai-Thai Le; Jürgen Lindolf; Eckhard Brass; Helmut Schneider
Original assignee: Siemens Aktiengesellschaft
Priority date: 1998-09-30
Filing date: 1999-09-29
Publication date: 2000-04-06
Also published as: DE19844997A1

Abstract

The invention relates to a vertical MOS transistor which is characterized by a gate (10) which is arranged in a trench and which is annularly enclosed by the channel (15), the source (12) and the drain (6). The transistor is especially suitable for use as selection transistor of a DRAM cell in which the capacitor trench (KG) is arranged directly below the transistor trench (TG).

Description

description

Vertical field effect transistor with internal gate and manufacturing process

The requirement for high integration density in integrated circuits means in particular a reduction in the gate length for field effect transistors. With gate lengths of 0.5 to 0.2 μm and below, for example, this results in a large increase in short-channel effects, for example:

1) Short Channel Effect: the stronger influence of the space charge zones of the source and drain regions causes a decrease in the threshold voltage U _th .

2) Narrow channel effect: the proportion of the channel edge areas with radial space charge zone that increases in relation to the channel width leads to an increase in Uh.

3) Punch Through Effect: the overlap occurring for smaller gate lengths, the space charge zones emerging from the drain and source regions in the channel, causes an increasing breakdown of the potential barrier in the channel. This results in a drastic rise in leakage currents below the threshold voltage and poorer on / off current behavior. In order to keep the leakage current density low, the gate oxide thickness must be reduced. This in turn has a negative impact on the dielectric strength, the service life and the current carrying capacity of the transistor.

In order to avoid disadvantageous short channel effects despite a high integration density, vertical field effect transistors are known, ie the channel is arranged vertically relative to the substrate surface. This enables longer gate lengths without increasing the horizontal space requirement. An example of such a vertical transistor is the so-called Surrounding Gate Transistor, in which a vertical channel is surrounded by a gate on all sides. Such an SGT transistor is described in the article by K. Sunoushi et al. in IEDM 98-23, 2.1.1. described. The gate controls all four Sides of the channel. A disadvantage of this concept is the low mobility of the charge carriers in the channel, which worsens the electrical properties of the transistor.

An important area of application for field effect transistors is the use as a selection transistor in a memory cell, especially a DRAM memory cell. Since the integration density is a very important criterion here, the use of vertical selection transistors seems increasingly interesting.

The object of the present invention is therefore to provide a vertical field effect transistor with improved electrical properties, which can be used as a selection transistor of a memory cell. Another task is to specify a DRAM memory cell with a vertical selection transistor. Finally, another task is the specification of appropriate manufacturing processes.

These tasks are solved by a transistor with the

Features of claim 1, a memory cell with the features of claim 4 or by a method with the features of claim 6.

In the transistor according to the invention are source, drain and

Channel arranged on the side wall of a trench (hereinafter referred to as transistor trench) in a semiconductor substrate. The gate is housed inside the transistor trench, it being insulated from the trench wall by a gate dielectric and from the trench bottom by a buried insulation layer. The source, drain and channel are designed in a ring around the transistor trench, so the channel surrounds the gate in a ring. The buried insulation layer preferably has a greater layer thickness than the gate dielectric. Furthermore, in the vicinity of the substrate surface, an insulating layer thickened with respect to the gate dielectric can be applied the wall of the transistor trench. Both measures serve to minimize the gate capacitance.

The small space requirement of the gate electrode (1F ² , where F denotes the minimum structure size) enables a high integration density of such transistors. Since the transistor channel consists of a single-crystal substrate, such a transistor has good electrical properties, such as a long service life, high dielectric strength and high mobility of the charge carriers. The narrow channel effect is avoided by the closed, ring-shaped channel without a channel edge area, so that the adjustability of U _{TH is} improved.

Furthermore, a substrate connection can be implemented in a simple manner, as usual by contacting a p ^{+ region} in the substrate surrounding the transistor. In addition to low complexity and space requirements, an influence of the gate voltage on the substrate potential is largely avoided in contrast to transistors with a surrounding gate.

The transistor is particularly suitable as a selection transistor of a DRAM trench cell. In such an arrangement, it is provided according to the invention that a capacitor trench, in which the storage capacitor is accommodated, is arranged below the transistor trench. The storage electrode is located inside the capacitor trench and is insulated from its wall and bottom by a capacitor dielectric. At the upper end of the capacitor trench, an electrical connection to the drain is provided via a location on the trench wall that is not covered with the dielectric. The counter electrode is formed by the semiconductor substrate; For this purpose, it can be provided that the substrate around the capacitor trench is more heavily doped.

This connection is preferably made via a conductive contact structure which rests on the storage electrode and contacts the trench wall at the level of the drain. The contact Layer, which forms the upper end of the capacitor trench, is isolated from the gate in the transistor trench by the buried insulating layer on the bottom of the transistor trench.

Such a memory cell is characterized by a particularly small space requirement, since the transistor is manufactured directly above the capacitor.

The manufacturing method for the transistor provides for using a mask to first produce the transistor trench with the depth required for the transistor and to produce a protective layer on the trench wall which leaves at least the trench wall free in the lower region, ie in the vicinity of the bottom of the transistor trench. This exposed part of the trench wall, which runs around the entire circumference of the transistor trench, is then doped with a dopant which has the conductivity type opposite to the semiconductor substrate. As a result, an annular drain region running around the transistor trench is produced at a predetermined depth in the semiconductor substrate. The protective layer serves as a doping mask. A suitable doping method is in particular the plasma immersion implantation. A gate dielectric is created on the wall of the transistor trench and a buried insulation layer is produced on the floor, for which purpose either the protective layer is removed and a gate dielectric or a buried insulation layer is applied, or the protective layer itself or part of the protective layer is used as a gate dielectric or as buried insulation layer used. The gate is produced in the interior of the transistor trench, the bottom of which is now covered with a buried insulation layer and the side wall of which is covered with the gate dielectric, preferably by filling with doped polysilicon and then etching back to the level of the substrate surface. The gate dielectric can then be thickened in the vicinity of the semiconductor substrate surface, in particular by oxidation of the exposed surface of the gate and then removing the oxide layer formed in the central region of the upper gate surface, ie except for an oxide edge.

Finally, a source region is ring-shaped implanted around the transistor trench, and a word line is made running over the transistor trench, which contacts the exposed central region of the gate surface. The source region is contacted with a bit line on the semiconductor substrate surface. The contact is preferably made on only one side of the trench, in other words the annular source region is produced asymmetrically, so that its lateral extension on one side of the trench has the area required for contact.

The manufacturing method for a memory cell provides for firstly etching a trench into a semiconductor substrate which is deeper than the transistor trench already explained. The lower section of this trench is called the capacitor trench, the upper section represents the transistor trench.

A capacitor dielectric is produced at the edge and on the bottom of the capacitor trench, and the capacitor trench is then filled with an electrode material. It is preferably provided that the wall of the transistor trench is exposed after this step. The bottom of the transistor trench is therefore formed by the electrode material and (near the trench wall) by the capacitor dielectric.

The above-described method for producing the selection transistor is then carried out in the transistor trench, that is to say the protective layer is first produced, etc. In order to produce the contact between the capacitor dielectric and drain, provision is preferably made for the exposed (not covered by the protective layer) after doping the drain. covered) bottom of the transistor trench with a contact layer, which rests on the electrode material and connects to the drain on the wall of the transistor trench, thereby ensuring an electrical connection. The buried insulation layer, which represents the insulation of the transistor trench bottom and the drain from the subsequent gate, is then applied to this contact layer.

The advantage of this method is that the transistor in the trench can be largely self-aligned.

The invention is explained in more detail below on the basis of exemplary embodiments which are illustrated in the drawings. Shown are: FIGS. 1-8: a cross section through a

Semiconductor substrate to which the manufacture of the

Transistor are illustrated, being as

Embodiment a DRAM cell was selected.

FIG. 1: a deep trench G is etched into a Si semiconductor substrate 1 (p-doped) using a trench mask 2, the lower section of which represents the capacitor trench KG and the upper section of which represents the transistor trench TG. The entire trench G is lined with a capacitor dielectric and then filled with an electrode material, preferably with n-doped polysilicon 4. The capacitor dielectric 3 and the electrode material 4 are etched back so far that only the capacitor trench remains filled with it, but the transistor trench TG is completely empty.

FIG. 2: the protective layer 5 serving as a drain implantation mask is then produced. For this purpose, a triple layer consisting of silicon nitride 5a / silicon oxide 5b / silicon nitride 5can is applied to the wall and bottom of the transistor trench. Then the upper nitride layer is first anisotropically and selectively etched to the oxide layer, then the exposed oxide is selective using an isotropic etching process removed to nitride, and finally nitride is etched again isotropically and selectively to the oxide. This results in a protective layer which leaves the bottom and the lower region of the transistor trench wall free, the vertical extent of the exposed transistor trench wall roughly corresponding to the layer thickness of the protective layer. The storage electrode 4 and the capacitor dielectric 3 are exposed at the bottom of the transistor trench. The remaining area of the transistor trench wall is covered with the protective layer, ie the triple layer mentioned. The drain is then doped, for which purpose a plasma immersion implantation with ions of an n-type dopant is preferably used (FIG. 3). As a result, an annular n-doped region is generated on the trench wall above the capacitor trench in the p-doped silicon substrate and forms the drain region of the vertical transistor.

FIG. 4: Then the upper silicon nitride layer 5c and the silicon oxide layer 5b of the protective layer 5 are removed using a suitable method. The transistor trench TG is filled with n-doped polysilicon, then this polysilicon is etched back to a contact layer 7 at the bottom of the transistor trench. The thickness of the contact layer can range from 50 to 100 nin. The type of process control ensures that it is electrically connected to both the storage electrode 4 and the drain 6. The contact between the storage electrode and the drain takes place in a self-aligned manner. An oxidation step is then carried out, in which the upper part of the contact layer 7 is converted into a silicon oxide 8. This silicon oxide represents the buried insulating layer 8. Its layer thickness is approximately 30 to 80 nm. During the oxidation, the silicon nitride layer 5a remaining on the trench wall serves as an oxidation mask.

Figure 5: the remaining part of the protective layer 5 is removed selectively to the buried insulating layer 8. Thereby the walls of the transistor trench TG are exposed, while the bottom of the transistor trench is covered with the buried insulating layer 8.

Figure 6: On the wall of the transistor trench, a gate oxide 9 is generated by an oxidation step. The transistor trench is then filled with a gate material, for example with doped polysilicon, the polysilicon 10 being etched back to the substrate surface. N-doped or p-doped polysilicon can be used as gate 10. With regard to the later implantation of the source region, n-polysilicon is preferred.

FIG. 7: the surface of the gate 10 is oxidized, the central part of the oxide layer formed on the gate is then removed again with the aid of a mask, so that only the remains of the oxide layer 11 remain in the vicinity of the trench wall. These residues of the oxide layer 11 form an insulating layer with a greater layer thickness than the gate dielectric 9. The trench mask 2, which serves as an oxidation mask for the substrate surface during the oxidation just carried out, is then removed — preferably directly after the oxidation.

FIG. 8: With a suitable mask, a source region 12 is produced by implantation in the substrate surface, which surrounds the trench in a ring. On one side, the doped region 12 is brought out so far that a connection for a bit line can be made here. The gate 10 is provided with one that runs over the transistor trench

Word line 13 contacted. The word line preferably consists of polysilicon with the same doping as the gate. The source region 12 is connected with a bit line 14. The channel is formed by a region 15 of the semiconductor substrate 1 which extends in a ring shape around the transistor trench. Although shown using the example of a DRAM cell, the vertical transistor according to the invention can also be used for other purposes. The drain is generally connected to a suitable buried conductive structure as a connection. The manufacturing process is changed accordingly:

In order to produce only the transistor, the trench is only produced in accordance with the depth of the transistor trench TG and the protective layer is then produced (corresponding to FIG. 2). A protective layer can also be used as the doping mask for the drain, which additionally covers the bottom of the transistor trench, in which, after exposing an annular region of the lower trench wall, a further layer is produced only on the trench bottom.

Claims

claims

1. Vertical MOS transistor in a semiconductor substrate (1),

- in which a gate (10) is arranged inside a transistor trench (TG) located in the semiconductor substrate,

- In which the transistor trench wall with a gate dielectric

(9) and the transistor trench bottom are covered with a buried insulating layer (8), in which a drain region (6) of a doped region in the semiconductor substrate (1) is subsequently formed on a lower region of the transistor trench wall,

a source region (12) is formed from a doped region of the semiconductor substrate subsequent to the trench wall in the upper region of the transistor trench,

- In which the source region (12), the drain region (6) and the transistor channel (15) each surround the gate (10) in a ring.

2. Transistor according to claim 1, wherein the buried insulating layer (8) on the bottom of the transistor trench has a greater layer thickness than the dielectric (9) on the trench wall.

3. Transistor according to one of claims 1 to 2, wherein the gate dielectric (9) in the vicinity of the semiconductor substrate surface is thickened (11).

4. Memory cell with a vertical MOS transistor according to one of claims 1 to 3 as a selection transistor and one

Storage capacitor,

- In which a capacitor trench (KG) is arranged in the semiconductor substrate (1) directly below the transistor trench (TG), the wall and bottom of which are covered with a capacitor dielectric (3),

- in which a storage electrode (4) is formed inside the capacitor trench, - In which the storage electrode (4) in the upper region of the capacitor trench (KG) has an electrical connection (7) to the drain (6).

5. Memory cell according to claim 4, wherein the storage electrode (4) and the electrical connection (7) made of doped polysilicon and the drain region (6) consist of monosilicon of the same conductivity type.

6. Manufacturing method for a transistor according to all of claims 1 to 3, with the following steps:

- Generation of a transistor trench (TG) in the semiconductor substrate

(1), - creating a protective layer (5) on the transistor trench wall, which leaves the trench wall free in the lower trench region,

Creating an annular drain region (6) by doping the exposed trench wall,

Generating a gate dielectric (9) on the trench wall and a buried insulating layer (8) on the trench bottom,

- creating a gate (10) inside the transistor trench,

- Creating an annular source region (12) by doping the semiconductor substrate surface around the transistor trench.

7. Manufacturing method for a memory cell according to claim 4 or 5,

- in which a trench with a capacitor trench as the lower section and a transistor trench as the upper section is etched in a semiconductor substrate (1),

in which a storage dielectric (3) and an electrode material (4) are applied to the trench wall and the trench bottom in the capacitor trench,

in which a conductive contact structure (7) is produced at the upper edge of the capacitor trench, which connects the electrode material (4) to the trench wall, - In which a vertical MOS transistor is produced in transistor trench using the method according to claim 6.

8. The method according to claim 6 or 7, in which a plurality of partial layers (5a, 5b, 5c) are applied to the wall and on the bottom of the transistor trench in order to produce the protective layer (5),

- in which the uppermost partial layer (5c) is then removed by anisotropic etching on the transistor trench bottom, - in which an underlying partial layer (5b, 5c) is then removed by isotropic etching on the trench bottom and the lower region of the trench wall.

9. The method according to claim 8, wherein the protective layer (5) consists of a triple layer consisting of silicon nitride / silicon oxide / silicon nitride.

10. Manufacturing method according to one of claims 6 to 9, in which after completion of the drain region (6) on the bottom of the transistor trench (TG), a thermal oxide is produced as a buried insulating layer (8).

11. The production method according to claim 10, in which after generation of the thermal oxide (8) on the bottom of the transistor trench, at least the lowermost partial layer of the protective layer (5) is removed and then the wall of the transistor trench is insulated with a gate dielectric (9).

12. Manufacturing method according to one of claims 6 to 11, in which the transistor trench is filled with doped polysilicon to produce the gate (10).

13. Manufacturing method according to one of claims 6 to 12, in which the gate dielectric (9) is thickened on the wall of the transistor trench in the vicinity of the semiconductor substrate surface by oxidation.

14. Manufacturing method according to one of claims 7 to 13, in which after the doping of the drain region (6) a doped polysilicon layer (7) is applied as a contact layer on the electrode material (4) in the capacitor trench.