WO2000025362A1 - Leistungshalbleiter und herstellungsverfahren - Google Patents
Leistungshalbleiter und herstellungsverfahren Download PDFInfo
- Publication number
- WO2000025362A1 WO2000025362A1 PCT/DE1999/003395 DE9903395W WO0025362A1 WO 2000025362 A1 WO2000025362 A1 WO 2000025362A1 DE 9903395 W DE9903395 W DE 9903395W WO 0025362 A1 WO0025362 A1 WO 0025362A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- power semiconductor
- doped
- sulfur
- selenium
- edge
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052717 sulfur Inorganic materials 0.000 claims abstract description 14
- 239000011593 sulfur Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 230000000903 blocking effect Effects 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052711 selenium Inorganic materials 0.000 claims description 8
- 239000011669 selenium Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 230000035515 penetration Effects 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 125000004429 atom Chemical group 0.000 claims 2
- 125000003748 selenium group Chemical group *[Se]* 0.000 claims 1
- 125000004434 sulfur atom Chemical group 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 14
- 235000012431 wafers Nutrition 0.000 description 9
- 238000000926 separation method Methods 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000012864 cross contamination Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
Definitions
- the present invention relates to a power semiconductor according to the preamble of the independent device claim and a method for producing a power semiconductor.
- edge terminations must be provided for both the forward blocking p-n junction and the reverse blocking junction. In the case of very large-area power semiconductors, this can be achieved by machining the edge areas.
- the components can be lapped or sandblasted, e.g. Generate so-called positive or negative angles, which cause a decrease in the electric field strength in the peripheral area when the reverse voltage is applied by widening the space charge zone.
- a disadvantage in the production of a separation diffusion in the prior art is the high load on the semiconductor material, which is due to the required diffusion temperatures of around 1240 ° C. and the long driving times, during which the semiconductor substrate must be kept at the diffusion temperature. Driving times of at least 50 hours are common even with wafer thicknesses of only 300 micrometers. lent.
- Another problem associated with the formation of a separation diffusion through aluminum is that it cannot be masked by silicon dioxide, SiO 2 . For this reason, no aluminum diffusions are generally carried out in semiconductor production lines for ICs, because it is feared here that the lack of maskability in later operation of the production line can lead to cross-contamination, for example due to a deterioration of a gate oxide.
- the object of the present invention is to provide something new for commercial use.
- a basic idea of the present invention is therefore to simplify the formation of edge terminations exclusively on one side of the semiconductor substrate by providing a doped region which runs from top to bottom to create an ohmic connection and is doped with sulfur or selenium. It has been recognized that such a sulfur or selenium doping, which extends from an edge termination on the upper side to a lower side semiconductor region, has considerable advantages over previously known doping of separation diffusion regions. Sulfur in particular has the advantage that the diffusion rate in silicon is very high, which makes it possible to carry out the doping with sulfur by diffusion at low temperatures and / or short times. This not only reduces the material load, but also allows economic use of production lines and faster production of a semiconductor as a whole. While selenium also contains the n-doping compounds suitable for the invention. has the properties for the reason mentioned
- Each edge termination can preferably be formed by doping, for example as doping with a lateral concentration variation as described in the previously cited US Pat. No. 4,672,738.
- the preferably sulfur-doped or selenium-doped area is typically provided on an edge or an edge of the finished power semiconductor, in order to create a connection to the underside from an edge termination for the reverse blocking capability. It is possible to make the sulfur-doped or selenium-doped region so wide that a semiconductor wafer can be sawn conveniently at this point. The sulfur or selenium-doped area is then on a saw edge. Since the sulfur-doped or selenium-doped region has donor properties, that is to say it has an n-conductivity, the low-doped base zone, which is necessary for realizing the desired blocking voltage, will be correspondingly p-doped.
- the second, higher doped base zone will therefore be n-doped accordingly.
- the cathode-side emitter will be p-doped and the anode-side node typically located on the underside.
- the silicon substrate With typical thicknesses and basic doping of the silicon substrate, it is sufficient to diffuse about 10 14 to 10 16 atoms / cm 2 into the substrate as an implantation dose.
- the surrounding areas to be protected from the sulfur implantation can be easily masked with photoresist or silicon dioxide.
- the masking layer thickness can be, for example, 1 micrometer, which experience has shown to be sufficient.
- the simple masking allows sulfur or selenium to be driven into the silicon from both sides of the substrate. In this way, the diffusion time can only be reduced from one side to about a quarter compared to diffusion.
- FIG. 1 shows a part of a cross section through a silicon wafer with structures for a power semiconductor of the present invention.
- FIG. 1 shows a cross section through a silicon wafer on a cutout on which two power semiconductors la and lb to be separated later are formed together with their edge regions.
- the intended dividing line 2 is shown in dashed lines and the edge regions of the power semiconductors la and lb are mirror-symmetrical to the dividing line 2, so that only the structure of the edge region to the left of the dividing line 2 from the power semiconductor la is to be described below.
- the section shown also only shows the edge regions of the power semiconductor, where in principle no contacts, gate arrangements and the like are provided, as are required and known in power components, in which the arrangement of the present invention to be described can be used.
- power components are, for example, IGBTs, thyristors, turn-off thyristors (GTO), etc.
- the edge region of a power semiconductor 1 a blocking on both sides comprises an n-doped underside anode 3, a lightly p-doped base zone 4, a second ba- Siszone 5 with higher n-doping and an edge termination 6 to the surface 7 of the power semiconductor la, which is formed for the forward blocking ability of the power semiconductor la.
- a distance 8 approximately corresponding to the substrate thickness of the semiconductor substrate and spaced from the edge termination 6, an n-doped edge termination 9 is provided for the reverse blocking capability.
- a sulfur- or selenium-doped separation diffusion zone 10 now leads from the n-doped emitter region 3 provided on the underside through the semiconductor substrate to the edge termination 9 and thereby provides an ohmic connection between the edge termination due to the donor properties of the sulfur or selenium introduced into the silicon wafers for the reverse blocking capability 9 and the n-doped underside region 3.
- the semiconductor described can e.g. are produced as follows:
- the necessary semiconductor structures such as gate connections, emitters, collectors, etc. are initially provided in the silicon wafer.
- the edge seals 6 and 9 are realized in a known manner, for example by field rings, field plates and / or, as shown, by a VLD structure in a manner known per se on the surface of the power semiconductor, that is to say on the cathode side.
- a mask is then applied to the substrate at those locations at which the separation diffusion is to be created.
- the width of the areas left by the masking f is sufficient to be able to separate the components 1 a and 1 b later in the middle of this area along the line 2, and yet a width at the remaining edge transverse to the connecting line of about three to four penetration depths the space charge zone into the sulfur or selenium doped zone
- the wafer is then heated to a temperature of 1200 ° C. until the dopant fronts diffusing into the silicon from both sides have run into one another.
- the wafer After cooling, the wafer can be sawn along line 2 and the component can be contacted in the usual way.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000578849A JP2002528913A (ja) | 1998-10-23 | 1999-10-22 | 電力用半導体及び製造方法 |
EP99959223A EP1135808B1 (de) | 1998-10-23 | 1999-10-22 | Leistungshalbleiter und herstellungsverfahren |
DE59913394T DE59913394D1 (de) | 1998-10-23 | 1999-10-22 | Leistungshalbleiter und herstellungsverfahren |
US09/840,549 US6683328B2 (en) | 1998-10-23 | 2001-04-23 | Power semiconductor and fabrication method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19848984.6 | 1998-10-23 | ||
DE19848984 | 1998-10-23 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/840,549 Continuation US6683328B2 (en) | 1998-10-23 | 2001-04-23 | Power semiconductor and fabrication method |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000025362A1 true WO2000025362A1 (de) | 2000-05-04 |
Family
ID=7885456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/003395 WO2000025362A1 (de) | 1998-10-23 | 1999-10-22 | Leistungshalbleiter und herstellungsverfahren |
Country Status (5)
Country | Link |
---|---|
US (1) | US6683328B2 (de) |
EP (1) | EP1135808B1 (de) |
JP (1) | JP2002528913A (de) |
DE (1) | DE59913394D1 (de) |
WO (1) | WO2000025362A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1063700A3 (de) * | 1999-06-22 | 2006-04-19 | Infineon Technologies AG | Substrat für Hochspannungsmodule |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4882214B2 (ja) * | 2004-09-17 | 2012-02-22 | 富士電機株式会社 | 逆阻止型絶縁ゲート形半導体装置およびその製造方法 |
US8759935B2 (en) * | 2011-06-03 | 2014-06-24 | Infineon Technologies Austria Ag | Power semiconductor device with high blocking voltage capacity |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2809165A (en) * | 1956-03-15 | 1957-10-08 | Rca Corp | Semi-conductor materials |
US2954308A (en) * | 1956-05-21 | 1960-09-27 | Ibm | Semiconductor impurity diffusion |
US4672738A (en) * | 1984-09-28 | 1987-06-16 | Siemens Aktiengesellschaft | Method for the manufacture of a pn junction with high breakdown voltage |
DE19531369A1 (de) * | 1995-08-25 | 1997-02-27 | Siemens Ag | Halbleiterbauelement auf Siliciumbasis mit hochsperrendem Randabschluß |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56126968A (en) * | 1980-03-10 | 1981-10-05 | Mitsubishi Electric Corp | Semiconductor device |
US4605944A (en) * | 1984-09-11 | 1986-08-12 | Sanyo Electric Co., Ltd. | LED array device for printer |
JPS61291491A (ja) * | 1985-06-19 | 1986-12-22 | Mitsubishi Monsanto Chem Co | りん化ひ化ガリウム混晶エピタキシヤルウエハ |
JPS6481271A (en) * | 1987-09-22 | 1989-03-27 | Nec Corp | Conductivity-modulation type mosfet |
US5268586A (en) * | 1992-02-25 | 1993-12-07 | North American Philips Corporation | Vertical power MOS device with increased ruggedness and method of fabrication |
EP0654829A1 (de) * | 1993-11-12 | 1995-05-24 | STMicroelectronics, Inc. | MOS-gesteuerte doppelt-diffundierte Halbleiteranordnungen mit erhöhter Dichte |
US5486718A (en) * | 1994-07-05 | 1996-01-23 | Motorola, Inc. | High voltage planar edge termination structure and method of making same |
TW286435B (de) * | 1994-07-27 | 1996-09-21 | Siemens Ag | |
US5760462A (en) * | 1995-01-06 | 1998-06-02 | President And Fellows Of Harvard College | Metal, passivating layer, semiconductor, field-effect transistor |
US5949124A (en) * | 1995-10-31 | 1999-09-07 | Motorola, Inc. | Edge termination structure |
FR2753837B1 (fr) * | 1996-09-25 | 1999-01-29 | Composant de protection a retournement bidirectionnel a claquage en surface | |
GB2327295A (en) * | 1997-07-11 | 1999-01-20 | Plessey Semiconductors Ltd | MOS controllable power semiconductor device |
US5959345A (en) * | 1997-11-28 | 1999-09-28 | Delco Electronics Corporation | Edge termination for zener-clamped power device |
US6281521B1 (en) * | 1998-07-09 | 2001-08-28 | Cree Research Inc. | Silicon carbide horizontal channel buffered gate semiconductor devices |
-
1999
- 1999-10-22 DE DE59913394T patent/DE59913394D1/de not_active Expired - Lifetime
- 1999-10-22 JP JP2000578849A patent/JP2002528913A/ja active Pending
- 1999-10-22 WO PCT/DE1999/003395 patent/WO2000025362A1/de active IP Right Grant
- 1999-10-22 EP EP99959223A patent/EP1135808B1/de not_active Expired - Lifetime
-
2001
- 2001-04-23 US US09/840,549 patent/US6683328B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2809165A (en) * | 1956-03-15 | 1957-10-08 | Rca Corp | Semi-conductor materials |
US2954308A (en) * | 1956-05-21 | 1960-09-27 | Ibm | Semiconductor impurity diffusion |
US4672738A (en) * | 1984-09-28 | 1987-06-16 | Siemens Aktiengesellschaft | Method for the manufacture of a pn junction with high breakdown voltage |
DE19531369A1 (de) * | 1995-08-25 | 1997-02-27 | Siemens Ag | Halbleiterbauelement auf Siliciumbasis mit hochsperrendem Randabschluß |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1063700A3 (de) * | 1999-06-22 | 2006-04-19 | Infineon Technologies AG | Substrat für Hochspannungsmodule |
EP1818980A3 (de) * | 1999-06-22 | 2010-08-11 | Infineon Technologies AG | Substrat für Hochspannungsmodule |
Also Published As
Publication number | Publication date |
---|---|
JP2002528913A (ja) | 2002-09-03 |
EP1135808B1 (de) | 2006-05-03 |
DE59913394D1 (de) | 2006-06-08 |
US6683328B2 (en) | 2004-01-27 |
EP1135808A1 (de) | 2001-09-26 |
US20010042870A1 (en) | 2001-11-22 |
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