WO2000028664A8 - Fully integrated tuner architecture - Google Patents

Fully integrated tuner architecture

Info

Publication number
WO2000028664A8
WO2000028664A8 PCT/US1999/026700 US9926700W WO0028664A8 WO 2000028664 A8 WO2000028664 A8 WO 2000028664A8 US 9926700 W US9926700 W US 9926700W WO 0028664 A8 WO0028664 A8 WO 0028664A8
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
filter
filters
receiver
image
Prior art date
Application number
PCT/US1999/026700
Other languages
French (fr)
Other versions
WO2000028664A2 (en
WO2000028664A3 (en
Inventor
Pieter Vorenkamp
Klaas Bult
Frank Carr
Christopher M Ward
Ralph Duncan
Tom W Kwan
James Y C Chang
Haideh Khorramabadi
Original Assignee
Broadcom Corp
Pieter Vorenkamp
Klaas Bult
Frank Carr
Christopher M Ward
Ralph Duncan
Tom W Kwan
James Y C Chang
Haideh Khorramabadi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=27574786&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2000028664(A8) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Broadcom Corp, Pieter Vorenkamp, Klaas Bult, Frank Carr, Christopher M Ward, Ralph Duncan, Tom W Kwan, James Y C Chang, Haideh Khorramabadi filed Critical Broadcom Corp
Priority to EP99965786A priority Critical patent/EP1145430B1/en
Priority to DE69920273T priority patent/DE69920273T2/en
Priority to AU21479/00A priority patent/AU2147900A/en
Priority to AT99965786T priority patent/ATE276605T1/en
Publication of WO2000028664A2 publication Critical patent/WO2000028664A2/en
Publication of WO2000028664A8 publication Critical patent/WO2000028664A8/en
Publication of WO2000028664A3 publication Critical patent/WO2000028664A3/en

Links

Classifications

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    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
    • H03D3/18—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal by means of synchronous gating arrangements
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
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    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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    • H03G—CONTROL OF AMPLIFICATION
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    • H03J2200/00—Indexing scheme relating to tuning resonant circuits and selecting resonant circuits
    • H03J2200/10—Tuning of a resonator by means of digitally controlled capacitor bank
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjonction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned usingt local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
PCT/US1999/026700 1998-11-12 1999-11-12 Fully integrated tuner architecture WO2000028664A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP99965786A EP1145430B1 (en) 1998-11-12 1999-11-12 Integrated tuner architecture
DE69920273T DE69920273T2 (en) 1998-11-12 1999-11-12 INTEGRATED TUNER ARCHITECTURE
AU21479/00A AU2147900A (en) 1998-11-12 1999-11-12 Fully integrated tuner architecture
AT99965786T ATE276605T1 (en) 1998-11-12 1999-11-12 INTEGRATED TUNER ARCHITECTURE

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US10845998P 1998-11-12 1998-11-12
US10821098P 1998-11-12 1998-11-12
US10820998P 1998-11-12 1998-11-12
US60/108,209 1998-11-12
US60/108,459 1998-11-12
US60/108,210 1998-11-12
US11760999P 1999-01-28 1999-01-28
US60/117,609 1999-01-28
US13611699P 1999-05-26 1999-05-26
US13611599P 1999-05-26 1999-05-26
US60/136,115 1999-05-26
US60/136,116 1999-05-26
US13665499P 1999-05-27 1999-05-27
US60/136,654 1999-05-27
US15972699P 1999-10-15 1999-10-15
US60/159,726 1999-10-15

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CN108233877B (en) * 2017-12-27 2021-08-27 安徽华东光电技术研究所 Manufacturing process of low-noise amplifier

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