WO2000029822A1

WO2000029822A1 - Chip-scale packaged pressure sensor

Info

Publication number: WO2000029822A1
Application number: PCT/US1999/024568
Authority: WO
Inventors: Janusz Bryzek; David W. Burns; Sean S. Cahill; Steven S. Nasiri
Original assignee: Maxim Integrated Products, Inc.
Priority date: 1998-11-12
Filing date: 1999-10-19
Publication date: 2000-05-25
Also published as: WO2000029822A9; US6346742B1

Abstract

A chip-scale sensor package is described. In one embodiment, the chip-scale sensor package includes a semiconductor substrate having a sensor region, and a semiconductor cap having a recess. The semiconductor cap is bonded to the semiconductor substrate with a thermocompression bond to form a cavity therebetween. The semiconductor substrate is bonded to the semiconductor cap using different types of materials. The semiconductor substrate and/or the semiconductor cap may optionally include a semiconductor device such as an electronically trimmable integrated circuit fabricated thereon. In addition, the semiconductor substrate may optionally include an integral stress isolation flexible region for isolation of the sensor region.

Description

CHIP-SCALE PACKAGED PRESSURE SENSOR

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor pressure sensors, and specifically, to a chip-scale packaged pressure sensor.

2. Background Information

Figure 1 is a schematic cross section of a conventional silicon pressure sensor in a metal can package. As shown in Figure 1, the pressure sensor package consists of a silicon die 10 having an etched diaphragm 12, a backing wafer 14 usually made of Pyrex, a metal can 16 (e.g., TO-8 or TO-5) which houses the pressure sensor, metal pins 18 for providing external interconnection, and a pressure port 20. The metal can 16 is welded at 22 to maintain a vacuum reference in region 24, or in the case of differential or gage pressure measurements, a top-side pressure port 26 is provided.

Figure 2 is a schematic cross section of a conventional pressure sensor in a plastic package 28. The plastic package pressure sensor 28 consists of a silicon die 30 having a diaphragm 32, and a backing wafer 34 typically consisting of Pyrex, which is anodically bonded to the silicon die 30, to form a vacuum cavity 36 therebetween for providing absolute pressure measurements. The backing wafer 34 is attached to a bottom portion 46 of the plastic package 28 using an epoxy or RTV die attach. A gel overcoat 38 (e.g., silicon gel) is provided over the silicon die 30 for communicating pressure from external gaseous media. The plastic package 28 further includes a lid 40 having an opening 42 for directing external pressure to the sensor. The silicon gel provides a minimal amount of protection from adverse effects of the gaseous media for the sensor, circuits and wire interconnects.

SUMMARY OF THE INVENTION

In one embodiment, the present invention comprises a chip-scale sensor package. The chip-scale sensor package includes a semiconductor substrate having a sensor region, and a semiconductor cap having a recess. The semiconductor cap is bonded to the semiconductor substrate with a thermocompression bond to form a cavity therebetween. The semiconductor substrate and/or the semiconductor cap may optionally include one or more semiconductor devices such as an electronically trimmable integrated circuit fabricated thereon using conventional integrated circuit fabrication techniques. In addition, the semiconductor substrate may optionally include an integral stress isolation flexible region for isolation of the sensor region.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic cross section of a prior art silicon pressure sensor in a metal can package.

Figure 2 is a schematic cross section of a prior art pressure sensor in a plastic package.

Figure 3a is a schematic cross section of a chip- scale packaged pressure sensor according to one embodiment of the present invention. Figure 3b is a view of a portion of the pressure sensor of Figure 3a, taken on an expanded scale.

Figure 3c is a top view of the stress-isolated sensor die of Figure 3a according to one embodiment of the present invention.

Figure 3d is a perspective view of the stress- isolated region on a semiconductor die according to another embodiment of the present invention.

Figure 4 is a schematic cross section of the pressure sensor of Figure 3a further including electronic circuitry located within the bond ring.

Figure 5 is a schematic cross section of a gage or differential chip-scale packaged pressure sensor according to another embodiment of the present invention.

Figure 6 is a schematic cross section of the chip- scale packaged pressure sensor of Figure 3a having an optionally deposited protective coating.

Figure 7a is a perspective view of a ball grid array pressure sensor package according to one embodiment of the present invention.

Figure 7b is a schematic cross section of the ball grid array pressure sensor package of Figure 7a.

Figure 7c is a schematic cross section of a through-wafer via, taken on an expanded scale.

Figures 8a-81 illustrate several exemplary wafer- to-wafer bonding techniques using thermocompression bonding. Figure 9 illustrates an exemplary glass film wafer- to-wafer bonding configuration according to another embodiment of the present invention.

DETAILED DESCRIPTION

The present invention comprises a chip-scale packaged pressure sensor capable of measuring absolute, differential, or gage pressure with optional on-chip integration, electronic trimming, stress isolation, through-wafer vias for external connections, and specialized coatings for media isolation. The sensor capsule may be used as a stand-alone unit or inside a secondary housing.

In one embodiment, the chip-scale packaged pressure sensor comprises a semiconductor substrate having a sensor region, and a semiconductor cap having a recess. The semiconductor cap is bonded to the semiconductor substrate using a thermocompression bond to form a cavity therebetween, as will be described in more detail below. The semiconductor substrate and/or the semiconductor cap may optionally include one or more semiconductor devices such as an electronically trimmable integrated circuit fabricated thereon using conventional integrated circuit fabrication techniques . In addition, the semiconductor substrate may optionally include an integral stress isolation flexible region for isolating the sensor region from mounting and packaging stresses.

Figure 3a is a schematic cross section of a chip- scale packaged pressure sensor 50 according to a first embodiment of the present invention. As shown in Figure 3a, the pressure sensor 50 comprises a silicon cap wafer 54 having a recess 56, and a sensor die 52 that includes a silicon diaphragm 60 and an integral stress isolation flexible region 62. The integral stress isolation flexible region 62 protects and isolates the diaphragm 60 from thermal and mounting stresses in the peripheral (or frame) region 124 of the die 52. The flexible diaphragm 60 includes piezoresistive elements (not shown) for sensing stress in the diaphragm 60. A bond ring 58 is used to hermetically attach the cap wafer 54 to the sensor die 52 under vacuum and form a vacuum cavity therebetween for providing an absolute pressure reference. The bond ring 58 comprises a ring of thermocompression bond material as will be described with respect to Figures 8a-81.

Figure 3b is a view of a portion of the pressure sensor 50 of Figure 3a, taken on an expanded scale. As shown in Figure 3b, the stress isolation flexible region 62 includes a horizontal member 110 integral with the frame region 124, and a vertical member 112 having a first end integral with a second end of the horizontal member 110, and a second end integral with a rim region 122. Prior to formation of the horizontal and vertical members 110 and 112, and the diaphragm 60, an oxide layer 114 is formed in the silicon substrate sensor die 52. The oxide layer 114 is formed in the silicon substrate sensor die 52 using, but not limited or restricted to, a Silicon Implanted with Oxygen ("SIMOX") or Bonded and Etched Silicon-on-Insulator ("BESOI") technique commonly known in the art. The oxide layer 114 provides a suitable etch stop for a bottom side etch. A silicon epitaxial layer 116 (e.g., N-) is then deposited, as needed, above the oxide layer 114 to increase the thickness of the diaphragm 60. Moderately doped P-type layers 130 and 132 are formed in the epitaxial layer 116. A second oxide layer 126 is disposed over the epitaxial layer 116 extending across the width of the sensor die 52. After depositing the second oxide layer 126, the upper trench 120 is formed, as will be described in more detail below. The second oxide layer 126 is etched in at least three places including an etch on the outside of the bond ring 58 for placing a metal contact or pad 77, and at both sides of the stress isolation region 62, as shown by numerals 134 and 136. A pad 77 is placed over the etch outside of the bond ring 58, and a metal interconnect layer 128 is placed between etches 134 and 136. The doped P-type layer 130 connects the metal contact 128 at numeral 134, under the bond ring 58, to the pad 77. The doped P-type layer 132 connects the metal contact 128 at numeral 136 to circuitry in the diaphragm region 60 such as a piezoresistive element (not shown) . This provides interconnection between the piezoresistive elements disposed on the diaphragm 60 (and other circuitry inside the bonding ring 58) and one or more pads 77 outside of the bonding ring 58. The second oxide layer 126 also isolates the P-type layer 130 from the thermocompression bond ring 58.

The horizontal and vertical members 110 and 112 are formed by vertically etching lower and upper trenches 118 and 120 from the bottom and top of the sensor die 52, respectively. A series of silicon and oxide etch steps are utilized to complete the upper trench 120. Formation of the horizontal and vertical members 110 and 112 is achieved using an etching process such as, but not limited or restricted to, deep reactive ion etching ("D-RIE") of silicon, a known etching technique which allows deep trenches to be etched in silicon with high aspect ratios and nearly vertical walls on each side of the wafer. The pressure-sensitive diaphragm 60 can also be etched using the D-RIE technique, and may be done at the same time as the backside etch used to form the horizontal member 110.

Accuracy in the thickness of the horizontal member 110 and deformable diaphragm 60 is enhanced by the inclusion of the oxide layer 114 at a depth from the top surface equal to the desired thickness of the diaphragm, since the etch rate of such oxide is much slower than that of bulk silicon. Though silicon-on-insulator ("SOI") material is used in cases where a thin, highly uniform diaphragm 60 is desired, standard material (non- SOI) may be used in conjunction with a timed etch to provide thicker diaphragm layers. Electric discharge machining or other micromachining techniques may also be used to form the flexible horizontal and vertical members 110 and 112, if desired.

In one embodiment, the horizontal and vertical members 110 and 112 each have an aspect ratio (length to thickness) of approximately 10 to 1. That is, the length of each member is approximately ten times the thickness of the respective member, thereby providing good flexibility to confine externally generated stresses to the frame region 124 only. Other aspect ratios, as low as 1:1 or greater than 10:1, may be used depending on a number of factors including, but not limited to, the amount of stress that the frame region 124 may be subjected to, the thickness of the diaphragm 60, etc. The stress isolation flexible region 62 so formed is integral with the outer frame region 124. The horizontal and vertical members 110 and 112 support a nominally rigid rim region 122 with the same providing an isolated, rigid support for the pressure-sensitive diaphragm 60. Figure 3c is a top view of the stress-isolated sensor die of Figure 3a according to one embodiment of the present invention. In the embodiment shown, the diaphragm 60 is shaped as a square. However, the diaphragm may be formed of any shape such as, for example, a circular diaphragm. Four piezoresistive elements (not shown) are disposed on the surface of the diaphragm 60 and are connected in a Wheatstone bridge configuration for sensing bending stresses and providing an output signal in response thereto. The lower trench 118 defines the horizontal member 110 (see Figure 3b) whereas the upper trench 120 fabricated in close proximity to the lower trench 118 forms the vertical member 112 (see Figure 3b) . Cross-over regions for electrical interconnections are not shown.

Figure 3d is a perspective view of the stress- isolated region 60 on a semiconductor die according to another embodiment of the present invention. A bridge region 140 is provided over the upper trench 120 for routing metal traces to and from the stress-isolated region 60 (e.g., the traces that are connected to the piezoresistive elements) . Supplemental isolation may optionally be provided by using a rectangular upper trench 142 near the bridge region 140.

Figure 4 illustrates the pressure sensor 50 of Figure 3a further including electronic circuitry located within the bond ring 58. Active electronic circuitry may be located and fabricated inside the bond ring 58 of the sensor die 52, as shown by numerals 64 and 65. In addition, active electronic circuitry may be located on either the top-side (not shown) or bottom-side, as shown by numeral 66, of the cap wafer 54. Fabricating the electronic circuitry within the bond ring 58 environmentally protects the same from gaseous and/or fluid media. The cap wafer 54 may contain etched holes for wire bond access to the sensor die 52 (see, e.g., Figure 7b) .

Active electronic circuitry may be optionally fabricated directly on the sensor die 52 for amplification, signal correction, etc., before the cap wafer 54 and the sensor die 52 are joined. An exemplary active electronic circuitry includes electronically trimmable circuitry which eliminates the need for laser trimming. While the embodiments illustrated in the drawings have the circuitry outboard of the flexible stress isolation region 62 , some or all of the circuitry, such as zero offset compensation, scale factor correction, and amplification circuitry may be located in the thick rim region 122, as shown by numeral 65, to also isolate such circuitry from stress imposed from or through the package. Alternatively, circuitry may be fabricated on the diaphragm 60.

Figure 5 is a schematic cross section of a gage or differential chip-scale packaged pressure sensor according to another embodiment of the present invention. In this embodiment, a second pressure port 68 is etched in the cap wafer 54 to provide top-side access for gage or differential sensing. Alternatively, the pressure port may be formed by slots in the vicinity of the bond ring region 58. Additional protection against corrosive media can be attained by the use of protective coatings such as silicon nitride, silicon carbide, amorphous diamond or polymeric films deposited on a bottom-side 70 of the sensor die 52, as shown in Figure 6. Front-side protective coatings may be provided in addition to or in lieu of the bottom-side protective coating. Additionally, a coating may also be deposited from the top of the sensor die 52 to protect the diaphragm, wire traces, and co-fabricated integrated circuitry, particularly in the case of gage or differential sensors .

Figure 7a is a perspective view of a ball grid array ("BGA") pressure sensor package according to one embodiment of the present invention. Referring to Figure 7a, a set of pads 72 is provided to form a micro BGA on the cap wafer 54. This view shows the optional top-side pressure port 68 (as shown in Figure 5) on top of the cap wafer 54. The top-side pressure port 68 includes a seal ring 74 there-around for attaching a pressure port to provide environmental protection of bonding pads. The pads 72 are electrically connected to circuitry on the sensor die 52 by a series of through- the-wafer holes. Figure 7b is a schematic cross section of the BGA pressure sensor package of Figure 7a. This view shows a series of vias 76 that provide the interconnection between pads 77 on the sensor die 52 and pads 72 on the cap wafer 54. An optional second cavity 88 may be formed between the sensor die 52 and cap wafer 54.

Figure 7c illustrates a view of a through-wafer via, taken on an expanded scale. D-RIE is used to form holes completely through the cap wafer 54, which is then oxidized to form an oxide layer 78, and then through- plated with metal 80 (e.g., MOCVD aluminum). Subsequent patterning provides the electrical interconnections between the front and back of the cap wafer 54.

The present invention utilizes various materials to incorporate thermocompression bonds to form semiconductor sensors . These materials provide wafer- to-wafer hermetic bonds , have reasonable step coverage over underlying topology, and are compatible with existing integrated circuit ("IC") processing. Aluminum and gold metallurgical systems have widespread use in integrated circuit metal interconnects and pad builds. These materials have thermocompression bonds with other IC-compatible materials, such as germanium and polysilicon or single crystal silicon, respectively. By way of illustration, a bond ring comprising aluminum, gold, or polysilicon may be formed on the sensor die 52, while the silicon cap wafer 54 may be coated with germanium, uncoated, or gold coated, respectively. The two wafers (sensor die 52 and silicon cap 54) are placed in physical contact under elevated temperature and pressure to form the bond.

The silicon cap wafer 54 has a cavity inside the bond ring region, to allow for deflections of the deformable diaphragm 60 and to form a vacuum chamber for absolute sensor capsules or a controlled environment for other semiconductor devices . The cap wafer 54 may also have one or more recesses (see, e.g., cavity 88 in Figure 7b) for clearance between the cap wafer and underlying devices . The recesses and cavities may be formed by etching the cap wafer, or they may be formed by a thick ring of thermocompression bond material, such as that obtained by a plating operation. The thermocompression wafer bond temperature is selected to be higher than any post-bond sequence, such as hard die attach, and lower than the temperature at which degradation of the active devices occurs. The thermocompression temperature range is preferably between 180°C to 500°C.

Figures 8a-81 illustrate several exemplary wafer- to-wafer bonding approaches using thermocompression bonding (such as, but not limited or restricted to, eutectic bonding) . As shown in Figure 8a, a thin film of germanium 82 is deposited onto the silicon cap wafer 54 and a corresponding aluminum ring 84 is deposited on the sensor die wafer 84 (shown on the field oxide 86) . After surface cleaning, the wafers are aligned in a special fixture and inserted into a wafer-to-wafer bonder. Bonding is performed at elevated temperatures while pressing the wafers together. In one embodiment, an aluminum-germanium thermocompression bond is used with a eutectic temperature of 424°C. A vacuum ambient may be incorporated into the cavities by pumping down the bonding chamber prior to elevating the temperature. When the wafers are bonded, predefined recesses and cavities are formed in regions, as shown by numerals 56 and 88 in Figure 7b.

Figure 8b shows a deposited aluminum film 90 on top of the germanium 82 which provides a protective layer against oxidation of the germanium 82 and allows the same cleaning cycles to be performed on the cap and sensor wafers 52 and 54, respectively. A thermal oxide 92 may optionally be incorporated underneath the germanium 82, as shown in Figure 8c, and may optionally be incorporated underneath the germanium 82 and the aluminum film 90, as shown in Figure 8d.

Figures 8e-8h illustrate a gold-silicon thermocompression bond. Figure 8e shows a gold bond ring 94 located on a field oxide 86 of the sensor die wafer 52. Figure 8f shows that the gold bond ring 94 of the sensor die wafer 52 may be bonded to a thin film of gold 96 deposited onto the silicon cap wafer 54. In one embodiment, the gold-silicon eutectic temperature is at 363°C. In an alternative embodiment, as shown in Figure 8g, the gold bond ring 94 deposited on the sensor die wafer 52 is bonded to a layer of polysilicon 98, which is deposited on a layer of thermal oxide 100, of the cap wafer 54. Figure 8h shows a layer of thermal oxide 100 optionally incorporated underneath the gold layer 96 on the silicon cap wafer 54.

In yet another embodiment, a polysilicon bond ring 102 is provided on the sensor die wafer 52 with a field oxide 86 incorporated therebetween, as shown in Figure 8i. In this embodiment, a layer of gold 96 is deposited on the silicon cap wafer 52 to complete the thermocompression wafer-to-wafer bonding materials. A variation of Figure 8i includes depositing a layer of gold 94 on top of the polysilicon 102 , as shown in Figure 8j . A further variation of Figure 8i includes incorporating a layer of thermal oxide 92 underneath the gold layer 96 of the silicon cap wafer 54, as shown in Figure 8k. Figure 81 shows the combination of the thermocompression bonding material of the sensor die wafer 52 of Figure 8j and thermocompression bonding material of the silicon cap wafer 54 of Figure 8k. Additional adhesion layers and barrier layers may also be included.

Figure 9 illustrates an exemplary glass film wafer- to-wafer bonding configuration according to another embodiment of the present invention. In this embodiment, a low temperature glass film 104, such as a borophosphosilicate glass, which provides a good seal over underlying metal traces and active devices, is used.

The present invention solves numerous packaging problems by providing an integral vacuum reference, integral stress isolation flexible region, and compatibility with co-fabricated integrated electronic circuits for a single-chip solution without the requirement for laser trimming. The present invention further includes an optional coating to eliminate costly barrier diaphragms and optional through-wafer vias for top-side and/or bottom-side interconnection as a surface mounted or ball grid array component. The chip-scale packaged pressure sensor of the present invention may be used in conjunction with signal compensation, conversion, communication electronics, and the like.

While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art.

Claims

CLAIMSWhat is claimed is :

1. A chip-scale sensor package, comprising: a semiconductor substrate including a sensor region; and a semiconductor cap including a recess, wherein the semiconductor cap is bonded to the semiconductor substrate with a thermocompression bond to form a cavity therebetween.

2. The chip-scale sensor package of claim 1, wherein the semiconductor substrate comprises at least one semiconductor device fabricated thereon.

3. The chip-scale sensor package of claim 2, wherein the at least one semiconductor device comprises an electronically trimmable integrated circuit.

4. The chip-scale sensor package of claim 1, wherein the semiconductor cap comprises at least one semiconductor device fabricated thereon.

5. The chip-scale sensor package of claim 4, wherein the at least one semiconductor device comprises an electronically trimmable integrated circuit.

6. The chip-scale sensor package of claim 1, wherein the sensor region comprises a deformable diaphragm for sensing external pressure.

7. The chip-scale sensor package of claim 6, wherein the cavity forms a hermetically sealed integral pressure vacuum reference.

8. The chip-scale sensor package of claim 1, wherein the semiconductor cap is bonded to the semiconductor substrate at a temperature ranging between 180°C and 500°C.

9. The chip-scale sensor package of claim 8, wherein the semiconductor cap is bonded to the semiconductor substrate using aluminum and germanium.

10. The chip-scale sensor package of claim 8, wherein the semiconductor cap is bonded to the semiconductor substrate using gold and polycrystalline silicon.

11. The chip-scale sensor package of claim 8, wherein the semiconductor cap is bonded to the semiconductor substrate using gold and single-crystal silicon.

12. The chip-scale sensor package of claim 8, wherein the semiconductor cap is bonded to the semiconductor substrate using a low-temperature glass bond.

13. The chip-scale sensor package of claim 8, wherein the semiconductor cap is bonded to the semiconductor substrate and forms a hermetically sealed reference pressure.

14. The chip-scale sensor package of claim 1 further comprising an integral stress isolation flexible region.

15. The chip-scale sensor package of claim 14 wherein the stress isolation flexible region includes : a first member including a first end coupled to a frame region of the semiconductor die, and a second end; and a second member including a first end coupled to the second end of the first member, and a second end coupled to a rim region of the semiconductor die.

16. The chip-scale sensor package of claim 15 wherein a first wall etch is used to define the first member and a second wall etch is used such that the combination of the first and second wall etches define the second member.

17. The chip-scale sensor package of claim 1, wherein the semiconductor cap includes holes for wire bonding.

18. The chip-scale sensor package of claim 1, wherein the semiconductor cap includes a pressure port for gage and differential pressure sensing.

19. The chip-scale sensor package of claim 1, wherein the semiconductor cap includes a plurality of holes which allow electrical interconnection through the semiconductor cap.

20. The chip-scale sensor package of claim 1, wherein the semiconductor substrate includes a plurality of holes which allow electrical interconnection through the semiconductor substrate.

21. The chip-scale sensor package of claim 1 further comprising a protective coating deposited on a bottom side of the semiconductor substrate and alternatively on a top side of the semiconductor cap to protect the environmentally exposed surfaces.

22. A chip-scale sensor package, comprising: a semiconductor substrate including a diaphragm and a stress isolation flexible region to isolate the diaphragm; and a semiconductor cap including a recess, wherein the semiconductor cap is bonded to the semiconductor substrate with a thermocompression bond to form a cavity therebetween.

23. The chip-scale packaged sensor of claim 22, wherein the semiconductor substrate includes integrated circuits which are electronically trimmable.

24. The chip-scale packaged sensor of claim 22, wherein the semiconductor cap includes integrated circuits which are electronically trimmable.

25. The chip-scale packaged sensor of claim 22 further comprising a protective coating deposited on the semiconductor substrate and alternatively the semiconductor cap for protecting the environmentally exposed surfaces.

26. A chip-scale sensor method, comprising the acts of: providing a semiconductor substrate including a diaphragm; providing a semiconductor cap including a recess region; bonding the semiconductor cap to the semiconductor substrate using a thermocompression bond to form a vacuum cavity therebetween.