WO2000034999A3 - An epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof - Google Patents

An epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof Download PDF

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Publication number
WO2000034999A3
WO2000034999A3 PCT/US1999/027359 US9927359W WO0034999A3 WO 2000034999 A3 WO2000034999 A3 WO 2000034999A3 US 9927359 W US9927359 W US 9927359W WO 0034999 A3 WO0034999 A3 WO 0034999A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
preparation
epitaxial
silicon
silicon wafer
Prior art date
Application number
PCT/US1999/027359
Other languages
French (fr)
Other versions
WO2000034999A2 (en
WO2000034999A9 (en
Inventor
Gregory M Wilson
Jon A Rossi
Charles C Yang
Original Assignee
Memc Electronic Materials
Gregory M Wilson
Jon A Rossi
Charles C Yang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memc Electronic Materials, Gregory M Wilson, Jon A Rossi, Charles C Yang filed Critical Memc Electronic Materials
Priority to JP2000587366A priority Critical patent/JP2002532875A/en
Priority to KR1020017005942A priority patent/KR20010092733A/en
Priority to EP19990960473 priority patent/EP1142010A2/en
Publication of WO2000034999A2 publication Critical patent/WO2000034999A2/en
Publication of WO2000034999A3 publication Critical patent/WO2000034999A3/en
Publication of WO2000034999A9 publication Critical patent/WO2000034999A9/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/10—Heating of the reaction chamber or the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/913—Active solid-state devices, e.g. transistors, solid-state diodes with means to absorb or localize unwanted impurities or defects from semiconductors, e.g. heavy metal gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y10T428/249961—With gradual property change within a component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y10T428/249978—Voids specified as micro

Abstract

This invention is directed to a novel process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon. In one embodiment, the process comprising heating a surface of a wafer starting material to remove a silicon oxide layer from the surface. Within about 30 seconds after removing the silicon oxide layer from the surface, the surface is exposed to an atmosphere comprising silicon to deposit a silicon epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175 °C while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant. Afterwards, the heated epitaxial wafer is cooled at a rate of at least about 10 °C/sec.
PCT/US1999/027359 1998-12-09 1999-11-18 An epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof WO2000034999A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000587366A JP2002532875A (en) 1998-12-09 1999-11-18 Epitaxial silicon wafer having internal gettering and method of manufacturing the same
KR1020017005942A KR20010092733A (en) 1998-12-09 1999-11-18 An epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof
EP19990960473 EP1142010A2 (en) 1998-12-09 1999-11-18 Epitaxial silicon wafer with intrinsic gettering and method for the preparation thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11154698P 1998-12-09 1998-12-09
US60/111,546 1998-12-09
US09/250,908 1999-02-16
US09/250,908 US6284384B1 (en) 1998-12-09 1999-02-16 Epitaxial silicon wafer with intrinsic gettering

Publications (3)

Publication Number Publication Date
WO2000034999A2 WO2000034999A2 (en) 2000-06-15
WO2000034999A3 true WO2000034999A3 (en) 2000-11-16
WO2000034999A9 WO2000034999A9 (en) 2001-04-19

Family

ID=26809017

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/027359 WO2000034999A2 (en) 1998-12-09 1999-11-18 An epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof

Country Status (7)

Country Link
US (3) US6284384B1 (en)
EP (1) EP1142010A2 (en)
JP (1) JP2002532875A (en)
KR (1) KR20010092733A (en)
CN (1) CN1329751A (en)
TW (1) TWI228549B (en)
WO (1) WO2000034999A2 (en)

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US6284384B1 (en) 2001-09-04
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