WO2000065647A1 - Chip scale package - Google Patents
Chip scale package Download PDFInfo
- Publication number
- WO2000065647A1 WO2000065647A1 PCT/US2000/010785 US0010785W WO0065647A1 WO 2000065647 A1 WO2000065647 A1 WO 2000065647A1 US 0010785 W US0010785 W US 0010785W WO 0065647 A1 WO0065647 A1 WO 0065647A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- die
- contact
- wafer
- metal
- slot
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Definitions
- This invention relates to semiconductor device packages and the method of making such packages and more specifically relates to a chip-scale package and method of its manufacture.
- Semiconductor device packages are well known for housing and protecting semiconductor die and for providing output connections to the die electrodes.
- the semiconductor die are diced from a large parent wafer in which the die diffusions and metallizing are made in conventional wafer processing equipment.
- Such die may be diodes, field effect transistors, thyristors and the like.
- the die are fragile and the die surfaces must be protected from external environment. Further, convenient leads must be connected to the die electrodes for connection of the die in electrical circuits.
- such die are singulated from the wafer, as by sawing, and the bottom of the die is mounted on and connected to a portion of a lead frame which has identical sections to receive respective die.
- the top electrodes of the die are then commonly wire bonded to other portions of the lead frame, and a molded insulation housing is then formed over each lead frame section enclosing the die, and permitting lead portions of the lead frame to penetrate through the molded housing to be available for external connection.
- a support surface such as a printed circuit board or an IMS (insulation-metal- substrate) support surface.
- IMS insulation-metal- substrate
- chip-scale That is, the package of the present invention occupies very little more area than the actual area of the die. Thus, the invention reduces the package area (or "footprint") to close to the irreducible area of the die itself.
- the invention also provides a novel process for forming such chip-scale packages.
- semiconductor die are first processed in conventional wafer form.
- the completed semiconductor wafer is then bonded to a bottom contact wafer which is preferably made of a metal having thermal expansion characteristics similar to those of silicon, and, typically may be of molybdenum or tungsten.
- the die bottom will have a bottom electrode of any suitable metal and is preferably overcoated with silver.
- the base contact plate or wafer preferably has a metallized
- the bottom surface of the silicon wafer and top surface of the base contact can be connected by diffusion bonding, soldering, eutectic bonding or the like.
- the top contact wafer is similarly of a material having thermal expansion characteristics matched to that of silicon and its bottom surface can be metallized with silver, matching the metallized top surface of the electrode, or electrodes, on the die wafer surface.
- the top contact is further processed so that the contact sections for each die location are pre-cut to define separate contact portions when the devices are singulated.
- the separated cuts are filled in with a suitable plastic such as an epoxy or polyamide.
- a bottom groove in the top contact is filled with a plastic filler also encloses respective device areas and defines a thinned area.
- top metal wafer and base metal wafer are then bonded to the silicon die wafer in a common bonding or soldering operation, with the top electrode contacts aligning with and contacting the contact areas of the respective die.
- the bonded assembly is then saw-cut to singulate each die (in the conventional die streets) with its respective top and base contacts covering the full top and bottom die area.
- the die junctions are well protected and wire bond or pressure connections can be easily made to the top and bottom contacts.
- Figure 1 is an exploded view of the top and bottom contacts and silicon die in wafer form.
- Figure 2 is a bottom view of the top contact of Figure 1 to show the pattern of machined cuts in the wafer for use with a MOSgated wafer die having source and gate electrodes on its top surface.
- Figure 3 shows the wafers of Figures 1 and 2 brought together for bonding.
- Figure 4 is an exploded view of one of the bonded die of Figures 1 and 3 after singulation.
- Figure 5 is an exploded view of a die made in accordance with the invention, but having a different top electrode pattern.
- Figures 6 and 7 show the die of Figure 5 in its assembled condition.
- FIG. 1 there is shown one die section taken from an assembly of three wafers 10, 11 and 12.
- the wafers will have a much larger extent than that shown, and typically can contain hundreds or even thousands of die identical to that detailed in Figure 1.
- the die wafer 11 is a silicon wafer which has been conventionally processed to define a power MOSFET which may be that shown in U.S. patent 5,008,725.
- each of the die in the wafer 11 will have a bottom aluminum drain electrode 12a, a top source electrode 13 and a gate electrode 14.
- Each die will be separated from other die in wafer 11 by "streets" which provide a small area for saw cutting the die apart.
- Other devices could be used such as diode die, thyristor die and the like.
- Wafer 10 in Figure 1 is a base contact wafer and is preferably of a metal having expansion characteristics matched to those of silicon and may be molybdenum or tungsten or the like.
- the top surface of wafer 10 may have a silver metallized surface layer 20.
- the bottom surface of aluminum contact 12a may also be metallized with silver. Metals other than silver can be used.
- Wafer 12 in Figures 1 and 2 is also of an expansion metal such as molybdenum, but has a surface configuration which matches the top electrodes of the die in wafer 11.
- the gate contact portions 30 of wafer 12 are fully isolated from the source contact portions 31 (after the die are singulated).
- a series of intersecting grooves 32 are formed in the bottom of wafer 12 and define saw cut regions 33 ( Figure 3) for singulating the die.
- Thru- cut slots 34 shown shaded in Figure 2 separate the gate contacts 30 from the source contacts 31 after singulation.
- thru-cut slots 34 and shallower slots 32 are preferably back-filled with plastic (epoxy or polyamide) as shown in Figure 3.
- FIG. 1 shows the assembly process of the three wafers 10, 11 and 12 of Figure 1 in which the wafers 11 and 12 are carefully aligned with one another to match up the respective source and gate electrodes. Thereafter, wafers 10, 11 and 12 are simultaneously bonded together as by soldering, diffusion bonding, eutectic bonding or any other desired bonding process.
- Figure 4 shows a singulated die in exploded form. It will be apparent that the present invention is applicable to numerous types of device, including diodes, thyristors and FETs of all varieties. Suitable adjustments will be made in the contact wafers, depending on the shape of the electrodes in the die wafer.
- Figure 5 shows a MOSFET die 40 with a different surface pattern in which a gate pad 41 has gate fingers 42 extending therefrom and insulated from a source electrode surface 43, as in U.S. Patent
- the upper source expansion contact 50 will have suitable undercuts (not shown) which avoid contact with gate pad 41 and its extending fingers 42.
- the top expansion contact wafer will then have separated gate portion 51 and source portion 50 which are otherwise the same as those of the embodiment of Figures 1 to 4.
- Figure 7 shows a protective insulation filter 60 surrounding the edge of die 40 and insulating gate electrode 51 from source electrode 50.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU49745/00A AU4974500A (en) | 1999-04-22 | 2000-04-21 | Chip scale package |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13054099P | 1999-04-22 | 1999-04-22 | |
US60/130,540 | 1999-04-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2000065647A1 true WO2000065647A1 (en) | 2000-11-02 |
WO2000065647B1 WO2000065647B1 (en) | 2000-12-21 |
Family
ID=22445165
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/010785 WO2000065647A1 (en) | 1999-04-22 | 2000-04-21 | Chip scale package |
Country Status (4)
Country | Link |
---|---|
US (2) | US6281096B1 (en) |
AU (1) | AU4974500A (en) |
TW (1) | TW483093B (en) |
WO (1) | WO2000065647A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5858459A (en) * | 1996-02-22 | 1999-01-12 | Micron Technology, Inc. | Cassette invertor apparatus and method |
TW504427B (en) * | 2001-09-25 | 2002-10-01 | Honeywell Int Inc | Composition, methods and devices for high temperature lead-free solder |
US6917090B2 (en) * | 2003-04-07 | 2005-07-12 | Micron Technology, Inc. | Chip scale image sensor package |
US7034385B2 (en) * | 2003-08-05 | 2006-04-25 | International Rectifier Corporation | Topless semiconductor package |
DE102006034679A1 (en) | 2006-07-24 | 2008-01-31 | Infineon Technologies Ag | Semiconductor module with power semiconductor chip and passive component and method for producing the same |
JP2012195388A (en) * | 2011-03-15 | 2012-10-11 | Toshiba Corp | Semiconductor device manufacturing method and semiconductor device |
US9728935B2 (en) * | 2015-06-05 | 2017-08-08 | Lumentum Operations Llc | Chip-scale package and semiconductor device assembly |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4962062A (en) * | 1987-09-11 | 1990-10-09 | Nissan Motor Company, Limited | Method of tightly joining two semiconductor substrates |
US6087719A (en) * | 1997-04-25 | 2000-07-11 | Kabushiki Kaisha Toshiba | Chip for multi-chip semiconductor device and method of manufacturing the same |
Family Cites Families (27)
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US4063272A (en) * | 1975-11-26 | 1977-12-13 | General Electric Company | Semiconductor device and method of manufacture thereof |
US5130767C1 (en) * | 1979-05-14 | 2001-08-14 | Int Rectifier Corp | Plural polygon source pattern for mosfet |
US5008725C2 (en) * | 1979-05-14 | 2001-05-01 | Internat Rectifer Corp | Plural polygon source pattern for mosfet |
US5216278A (en) | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5241133A (en) | 1990-12-21 | 1993-08-31 | Motorola, Inc. | Leadless pad array chip carrier |
US5151388A (en) * | 1991-05-07 | 1992-09-29 | Hughes Aircraft Company | Flip interconnect |
US5273940A (en) * | 1992-06-15 | 1993-12-28 | Motorola, Inc. | Multiple chip package with thinned semiconductor chips |
US5592025A (en) | 1992-08-06 | 1997-01-07 | Motorola, Inc. | Pad array semiconductor device |
US5352926A (en) | 1993-01-04 | 1994-10-04 | Motorola, Inc. | Flip chip package and method of making |
US5355283A (en) | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
US5734201A (en) | 1993-11-09 | 1998-03-31 | Motorola, Inc. | Low profile semiconductor device with like-sized chip and mounting substrate |
US5467253A (en) | 1994-06-30 | 1995-11-14 | Motorola, Inc. | Semiconductor chip package and method of forming |
US5892273A (en) | 1994-10-03 | 1999-04-06 | Kabushiki Kaisha Toshiba | Semiconductor package integral with semiconductor chip |
US5583376A (en) | 1995-01-03 | 1996-12-10 | Motorola, Inc. | High performance semiconductor device with resin substrate and method for making the same |
JP2679681B2 (en) | 1995-04-28 | 1997-11-19 | 日本電気株式会社 | Semiconductor device, package for semiconductor device, and manufacturing method thereof |
US5844168A (en) | 1995-08-01 | 1998-12-01 | Minnesota Mining And Manufacturing Company | Multi-layer interconnect sutructure for ball grid arrays |
KR0157899B1 (en) | 1995-09-22 | 1998-12-01 | 문정환 | Coupling structure for bonding semiconductor device of subsrate |
US5674785A (en) | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
JPH09213753A (en) | 1995-11-30 | 1997-08-15 | Ricoh Co Ltd | Connecting structure for semiconductor device and printed board |
US5578841A (en) * | 1995-12-18 | 1996-11-26 | Motorola, Inc. | Vertical MOSFET device having frontside and backside contacts |
US5866939A (en) | 1996-01-21 | 1999-02-02 | Anam Semiconductor Inc. | Lead end grid array semiconductor package |
US5731709A (en) | 1996-01-26 | 1998-03-24 | Motorola, Inc. | Method for testing a ball grid array semiconductor device and a device for such testing |
KR100231276B1 (en) | 1996-06-21 | 1999-11-15 | 황인길 | Semiconductor package structure and its manufacturing method |
US5866949A (en) | 1996-12-02 | 1999-02-02 | Minnesota Mining And Manufacturing Company | Chip scale ball grid array for integrated circuit packaging |
US5889332A (en) | 1997-02-21 | 1999-03-30 | Hewlett-Packard Company | Area matched package |
JPH10335567A (en) | 1997-05-30 | 1998-12-18 | Mitsubishi Electric Corp | Semiconductor integrated-circuit device |
US5831832A (en) | 1997-08-11 | 1998-11-03 | Motorola, Inc. | Molded plastic ball grid array package |
-
2000
- 2000-04-21 US US09/556,213 patent/US6281096B1/en not_active Expired - Lifetime
- 2000-04-21 WO PCT/US2000/010785 patent/WO2000065647A1/en active Application Filing
- 2000-04-21 AU AU49745/00A patent/AU4974500A/en not_active Abandoned
- 2000-04-21 TW TW089107552A patent/TW483093B/en not_active IP Right Cessation
-
2001
- 2001-04-23 US US09/840,439 patent/US6396091B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4962062A (en) * | 1987-09-11 | 1990-10-09 | Nissan Motor Company, Limited | Method of tightly joining two semiconductor substrates |
US6087719A (en) * | 1997-04-25 | 2000-07-11 | Kabushiki Kaisha Toshiba | Chip for multi-chip semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
WO2000065647B1 (en) | 2000-12-21 |
US6281096B1 (en) | 2001-08-28 |
US20010036695A1 (en) | 2001-11-01 |
TW483093B (en) | 2002-04-11 |
AU4974500A (en) | 2000-11-10 |
US6396091B2 (en) | 2002-05-28 |
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