WO2000069053A1

WO2000069053A1 - Power factor correction application

Info

Publication number: WO2000069053A1
Application number: PCT/EP2000/003800
Authority: WO
Inventors: Bernd Clauberg; Rick Liang
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 1999-05-07
Filing date: 2000-04-27
Publication date: 2000-11-16
Also published as: EP1095444A1; JP2002544754A; DE60000327T2; CN1302472A; CN1130814C; EP1095444B1; US6128205A; DE60000327D1

Abstract

Commercially available transition mode power factor correction integrated circuits have an output pin that is used to control a MOSFET in the power output circuit as well as a multiplier input pin that is used to set the peak current. Zero crossing distortion in the input line current is significantly decreased by reducing the range of the portion of rectified line voltage applied to the multiplier input. The range may be reduced by adding clamping device such as a Zener diode to the voltage divider used to sense the rectified line voltage, so that the peak value at the multiplier input is clamped if the rectified line voltage exceeds a certain value. Another technique changes the value of impedance in the voltage divider used to sense the rectified line voltage. The change in the divider impedance may be achieved by using a transistor to switch a resistor in and out of the divider and a detector circuit to turn the signal transistor ON or OFF as a function of the rectified line voltage.

Description

Power factor correction application.

The present invention relates to power factor correction in voltage applications, and more particularly to control circuits to adapt power factor correction integrated circuits to wide range applications.

Power factor correction ("PFC") pre-regulators are used in various voltage/power applications so that a quasi-sinusoidal current is drawn in-phase with the line voltage, thereby achieving a power factor ("PF") of very close to one. PF is the ratio of the real power transferred to the output and the apparent power (RMS line voltage times RMS line current)drawn from the power main, so that PF of one is desirable. A common technique for achieving power factor correction in low power applications such as lamp ballasts and low-end monitors is the transition mode ("TM") technique, which is used in many different

PFC integrated circuit products available from various manufacturers such as product numberL6561 available from SGS Thomson Microelectronics of Carrollton, Texas, and product number MC34262 available from Motorola, Inc., Semiconductor Products Sector of

Austin, Texas.

Figure 1 shows a wide range demonstration board electrical circuit 10. Circuit lOincludes a bridge circuit 20 that delivers a rectified voltage to a boost converter having as its essential elements a boost inductor 48 (in this case, the primary of a transformer), a catch diode 58, an output capacitor 66, and control circuitry that includes a TM PFC integrated circuit ("IC") 9, specifically product number L6561 available from SGS Thomson Microelectronics. The boost converter shown in Figure 1, which is useful for understanding the operation of the PFC IC 9, uses a switching technique to boost the rectified input voltage from the bridge circuit 20 to a regulated DC output voltage for delivery to a load (not shown) via terminals 68 and 70. The purpose of the PFC IC 9 is to shape its input current in a sinusoidal fashion to be in-phase with the input sinusoidal voltage so as to regulate the DC output voltage. The circuit 10 operates as follows. An input sinusoidal voltage at terminals 12 and 14is applied across bridge circuit 20 through fuse 16 and negative temperature coeffιcient(NTC) device 18. The instantaneous rectified line voltage from the bridge 20 is filtered by input high frequency filter capacitor 22 and applied across a voltage divider 30 having resistor 32, diode 36, resistor 42, capacitor 44, and an auxiliary winding of the boos tinductor 48 connected in series. The voltage in the divider 30 between the resistor 32 and diode 36 is applied to Vcc pin 8, and the Ncc input is used internally in the PFC IC 9 to generate an internal reference voltage. Capacitor 34 is connected to V_Cc pin 8 for filtering.

In the boost converter, a MOSFET 54 along with resistor 56 forms a controlled power switch path connected between the boost inductor 48 and ground for energizing and de-energizing the boost inductor 48. The gate of the MOSFET 54 is controlled by the GD output pin 7 of the PFC IC 9 as a function of various voltages applied as inputs to the PFCIC 9. These inputs are ZCD pin 5, COMP pin 2, IΝV pin 1, and MUTL pin 3.

ZCD pin 5 is connected through resistor 46 to the divider 30 at the auxiliary winding of the boost inductor 48 for the purpose of zero current detection and external

MOSFET triggering and disabling. Internally, the PFC IC 9 generates a start up signal on output GDpin 7 which turns ON MOSFET 54. Thereafter, the PFC IC 9 internally generates a signal on output GD pin 7 to turn ON the MOSFET 54 as the voltage across the boost inductor 48reverses. This feature allows transition mode operation.

COMP pin 2 and INN pin 1 are connected to a point between resistors 62 and 64,which form a voltage divider 60 across the output of the circuit 10. The PFC IC 9 compares a portion of the boosted output DC voltage at the terminals 68 and 70 with its internal reference voltage to maintain the pre-regulator output DC voltage constant. A feed back capacitor 50 is connected between pins 1 and 2 for frequency compensation. The PFC IC 9uses a two-level overvoltage protection scheme, initially decreasing the gate voltage of MOSFET 54 at GD pin 7 to provide a "soft braking" action when a rising output voltage is detected, and then turning OFF the MOSFET 54 to provide a "heavy braking" action if a continuing rise in the output voltage is detected. The voltage across the resistor 56 is applied to the CS input pin 4 of the PFC IC 9 to determine the exact time when the MOSFET 54 is to be turned OFF. MULT pin 3 is connected to a point between resistors 26 and 28 in a voltage divider24 to receive a portion of the instantaneous rectified line voltage. The PFC IC 9 uses the MULT input to set the peak current of the MOSFET 54 cycle by cycle. Typically, the MULT input signal is shaped like a rectified sinusoid. Capacitor 40 is connected to MULT pin 3 for filtering.

The various circuits and operation of the integrated circuit 20 are further described by Claudio Adragna in Application Note AN966: L6561 Enhanced Transition Mode Power Factor Corrector, SGS-Thompson Microelectronics, March 1998.

Transition mode PFC ICs from various manufacturers are attractive to product designers since they are placed in relatively simple circuits that require relatively few external components and a relatively low value of boost inductance. Applications that use PFC ICs in an up converter design generally use a sense resistor divider off the rectified line, such as for example, circuit 10 of Figure 1, which uses the divider 24 to provide the MULT input voltage at pin 3. Although this signal is a rectified sine wave, distortion occurs at the zero crossing of the input line current. This zero crossing distortion is negligible for low power, small input voltage range applications, but becomes quite large if the load power range is large and/or the input voltage range is large. Such wide range applications can cause input line current total harmonic distortion in excess of 10%, which is generally undesirable.

A need, therefore, exists for apparatus and methods to permit TM PFC ICs to be used in wide range applications without causing excessively high input line current THD.

Accordingly, an object of the present invention as realized in particular embodiments is to modify the multiplier input signal to a TM PFC circuit so as to reduce input current THD when the load power range is large and/or the input voltage range is large.

Another object of the present invention as realized in particular embodiments is to apply a limited rectified input voltage to the multiplier input of a TM PFC IC so as to reduce input current THD when the load power range is large and/or the input voltage range is large.

Yet another object of the present invention as realized in particular embodiments is to apply a clamped rectified input voltage to the multiplier input of a TM PFC IC so as to reduce input current THD when the load power range is large and/or the input voltage range is large.

A further object of the present invention as realized in particular embodiments is to actively change the value of a rectified input voltage divider resistor to decrease the voltage applied to the multiplier input of a TM PFC IC so as to reduce input current THD when the load power range is large and/or the input voltage range is large.

These and other objects are achieved in the various embodiments of the present invention. For example, one embodiment of the present invention is a power factor correction application comprising a transition mode power factor correction circuit having a multiplier input, an input voltage bus, a voltage divider coupled to the input voltage bus and having a first intermediate node coupled to the multiplier input of the power factor correction circuit, and a voltage range reducing circuit coupled to a second intermediate node of the voltage divider.

Another embodiment of the present invention is a wide range boost converter comprising a pair of line voltage input terminals; a rectifier circuit coupled to the line voltage input terminals; a Vcc bus coupled to the rectifier circuit; a ground bus coupled to the rectifier circuit; an input filter capacitor coupled between the Vcc bus and the ground bus; a first voltage divider coupled between the Ncc bus and the ground bus and comprising a first resistance, a second resistance, and a third resistance coupled in series; a first Zener diode having an ^-terminal coupled to the first voltage divider between the second and third resistances, and a »-terminal coupled to the ground bus; a boost inductor comprising a primary winding and an auxiliary winding, the primary winding having a first terminal coupled to the Ncc bus; a second voltage divider coupled between the Ncc bus and the ground bus, the second voltage divider comprising a fourth resistance, a first diode, a fifth resistance, a first capacitance, and the auxiliary winding of the boost inductor coupled in series, and further comprising a second Zener diode having an ^-terminal coupled between the first diode and the fifth resistance and a ^-terminal coupled to the ground bus; a catch diode having ajσ-terminal coupled to the second terminal of the primary winding of the boost inductor; a controlled power switch path having one terminal coupled between the primary winding of the boost inductor and the catch diode, and another terminal coupled to the ground bus, the controlled power switch path comprising a MOSFET transistor and a sixth resistance coupled in series; a positive regulated voltage output terminal coupled to an n- terminal of the catch diode; a negative regulated voltage output terminal coupled to the ground bus; a third voltage divider coupled between the positive and negative regulated voltage output terminals, the third voltage divider comprising a seventh resistance and an eighth resistance; an output capacitance coupled between the positive and negative regulated voltage output terminals; a ninth resistor having a first terminal coupled to the second voltage divider between the first capacitance and the auxiliary winding of the boost inductor; a tenth resistor having a first terminal coupled to the MOSFET transistor; and a transition mode power factor correction integrated circuit having an INN pin coupled to the third voltage divider between the seventh and eighth resistances, a COMP pin coupled to the INN pin through a second capacitance; a MULT pin coupled to the first voltage divider between the first and second resistances, a CS pin coupled to the controlled power switch path between the MOSFET transistor and the sixth resistance, a ZCD pin coupled to a second terminal of the ninth resistance, a GΝD pin coupled to the ground bus, a GD pin coupled to a second terminal of the tenth resistance, and a Ncc pin coupled to the second voltage divider between the fourth resistance and the first diode.

Embodiments of the invention will be discussed making use of a drawing. In the drawing

Figure 1 is a schematic circuit diagram of a prior art application circuit using a power factor correction integrated circuit.

Figure 2 is a schematic circuit diagram of a circuit in accordance with the present invention for clamping input voltage to a multiplier input pin of a power factor correction integrated circuit.

Figure 3 is a waveform diagram showing an input line current and a portion of the rectified input line voltage that is applied to a multiplier input pin of power factor correction integrated circuit, for the circuit of Figure 2 having a 26 watt lamp load at 120 volts and from which the Zener diode is omitted.

Figure 4 is a waveform diagram showing an input line current and a portion of the rectified input line voltage that is applied to a multiplier input pin of power factor correction integrated circuit, for the circuit of Figure 2 having a 26 watt lamp load at 120 volts and which includes the Zener diode as shown therein, for comparison with Figure 3. Figure 5 is a waveform diagram showing an input line current and a portion of the rectified input line voltage that is applied to a multiplier input pin of power factor correction integrated circuit, for the circuit of Figure 2 having a 26 watt lamp load at 277 volts and from which the Zener diode is omitted.

Figure 6 is a waveform diagram showing an input line current and a portion of the rectified input line voltage that is applied to a multiplier input pin of power factor correction integrated circuit, for the circuit of Figure 2 having a 26 watt lamp load at 277 volts and which includes the Zener diode as shown therein, for comparison with Figure 5.

Figure 7 is a waveform diagram showing an input line current and a portion of the rectified input line voltage that is applied to a multiplier input pin of power factor correction integrated circuit, for the circuit of Figure 2 having a two 26 watt lamp load at 120 volts and from which the Zener diode is omitted.

Figure 8 is a waveform diagram showing an input line current and a portion of the rectified input line voltage that is applied to a multiplier input pin of power factor correction integrated circuit, for the circuit of Figure 2 having a two 26 watt lamp load at 120 volts and which includes the Zener diode as shown therein, for comparison with Figure 7.

Figure 9 is a waveform diagram showing an input line current and a portion of the rectified input line voltage that is applied to a multiplier input pin of power factor correction integrated circuit, for the circuit of Figure 2 having a two 26 watt lamp load at 277 volts and from which the Zener diode is omitted.

Figure 10 is a waveform diagram showing an input line current and a portion of the rectified input line voltage that is applied to a multiplier input pin of power factor correction integrated circuit, for the circuit of Figure 2 having a two 26 watt lamp load at 277 volts and which includes the Zener diode as shown therein, for comparison with Figure 9.

Figure 11 is a schematic circuit diagram of a circuit in accordance with the present invention for changing the value of a resistance used to generate an input voltage to a multiplier input pin of a power factor correction integrated circuit.

Commercially available transition mode ("TM") power factor correction ("PFC")pre-regulator integrated circuits ("IC") typically have an output pin that is used to control a MOSFET in the power output circuit as well as a multiplier input pin that is used to set the peak current that is conducted by the MOSFET on a cycle-by-cycle basis. Zero crossing distortion in the input line current is seen when commercially available TM PFC ICs are used in wide range voltage applications, which include, for example, those having a large load power range and/or a large input voltage range. We have found that this zero crossing distortion is significantly decreased by reducing the range of the portion of rectified line voltage applied to the multiplier input of the TM PFC IC. The range may be reduced in any convenient manner. For example, one technique adds a clamping device to the voltage divider used to sense the rectified line voltage, so that the peak value at the PFC IC multiplier input is clamped if the rectified line voltage exceeds a certain value. A Zener diode is a suitable clamping device; other suitable clamping devices include varistors, avalanche diodes, MOSFETs, active clamping circuits, and diodes to fixed voltages, for example. Another technique actively changes the value of impedance in the voltage divider used to sense the rectified line voltage based on, for example, either the peak or average rectified line voltage. The change in the divider impedance may be achieved in any convenient manner, as for example by using a small signal transistor to switch a resistor in and out of the divider and a peak detector or average sense circuit to turn the signal transistor ON or OFF as a function of the rectified line voltage.

An illustrative circuit 100 that employs a clamping device to clamp the peak value at the PFC IC multiplier input is shown in Figure 2. An input sinusoidal voltage is applied to terminals 112 and 114, filtered by an electromagnetic interference ("EMI") filter 120, and applied across bridge circuit 130. Illustratively, the EMI filter 120 is a well-known circuit arrangement of inductors 122 and 124 and capacitors 126 and 128, although other well-known EMI filters are also suitable. Illustratively, the bridge circuit 130 includes diodes 132,134, 136 and 138 in a well known circuit arrangement, although other well known rectifier circuits and devices are also suitable. The rectified voltage output from the bridge circuit 130is carried on a Ncc bus 140 and a ground bus 142 and is applied across an input high frequency filter capacitor 144 and also across a voltage divider 150 having resistors 152,154, 156, 158, 160 and 162 connected in series. The input to the MULT pin 3 of the PFC IC9, illustratively product number L6561 available from SGS Thomson Microelectronics, is taken from a node between resistors 160 and 162. The ^-terminal of a Zener diode 146 is connected to a point between resistors 156 and 158 and the 7-terminal is connected to the ground bus 142. The other elements of the boost converter such as the voltage divider 30, the boost inductor 48, the MOSFET 54, and the voltage divider 60 are connected to the Ncc bus 140 and the ground bus 142 as shown in Figure 1, and the other connections to the PFC IC 9are as shown in Figure 1.

The operation of the circuit 100 is apparent from the waveforms shown in Figures 4,6, 8 and 10, which were obtained with the circuit 100, when compared to the wave forms shown in Figures 3, 5, 7 and 9, which were obtained with the circuit 100 from which the Zener diode 146 was omitted. Figures 3 through 10 were obtained with the various elements of the circuit 100 (Figure 2) and circuit 10 (Figure 1, excluding elements for which circuit 100 substitutes) having the values or equivalent values (where a component type is identified) as set forth in Tables 1 and 2 respectively. In addition, transformer 48 (Table 2)has a core such as Thomson-CSF type B1ET2910A (ETD 29x16x10mm) or equivalent, a primary 90T of Litz wire 10x0.2mm, a secondary 1 IT of |27 AWG (0.15mm), and a gap ofl.8mm for a total primary inductance of 0.7mH. TABLE 1

TABLE 2

It will be appreciated that these values are merely illustrative, and that the values of these various elements are selected based on such factors as line voltage, power dissipation, cost, availability, and circuit designer preference. Detailed information about type L6561PFC IC, which is suitable for use with circuit 100, and considerations for selecting component values for and applications for the circuit 10 are described by Claudio Adragnain Application Note AN966: L6561 Enhanced Transition Mode Power Factor Corrector, SGS-Thompson Microelectronics, March 1998, which hereby is incorporated herein by reference in its entirety. With respect to circuit 100, resistors 152, 154, 156 and 158 may be realized in a single resistor, but the use of separate smaller resistors is desirable where, for example, surface mounted components are used because of power dissipation and voltage rating considerations. The Zener diode 146 is shown with its ^-terminal connected to a point between the resistors 158 and 160, but the actual point of connection in the voltage dividerl 50 depends on the desired clamping effect and the characteristics of the Zener diode selected for use. A Zener diode having a higher reverse breakdown or placed in series with ordinary diodes would be connected to a point between, for example, resistors 154 and 156, while a Zener diode having a lower reverse breakdown and a higher rated power dissipation would be connected to a point between resistors 160 and 162. In general, suitable component values include those selected to result in waveforms generally like those of Figures 4, 6, 8and 10. Figures 3 and 4 are waveform traces comparing the input line current THD (upper waveforms) and the MULT input signal (lower waveforms) for, respectively, the circuit of Figure 2 with the Zener diode 146 omitted and with Zener diode 146 included, for a 26 watt lamp load at 120 volts. As can be seen in Figure 3, the MULT input signal (the lower waveform) is shaped like a rectified sinusoid, which is typical for circuits that use TM PFCICs. Distortion can be seen on the input line current, but the THD is below 10%. Specifically, in Figure 3 the power is 30.0 watts, the power factor ("PF") is 0.996, and THDis 8.7%. At this low power level, the advantages of the circuit 10 with the Zener diode 146are evident but are not significant. Specifically, in Figure 4 the power is 30.1 watts, the power factor ("PF") is 0.997, and THD is 7.6%.

Figures 5 and 6 are waveform traces comparing the input line current THD (upper waveforms) and the MULT input signal (lower waveforms) for, respectively, the circuit of Figure 2 with the Zener diode 146 omitted and with Zener diode 146 included, for a 26 watt lamp load at 277 volts. As can be seen in Figure 5, the input line current is heavily distorted. Specifically, in Figure 5 the power is 29.9 watts, PF is 0.987, and THD is an unacceptable 14.7%. However, as can be seen by comparing Figure 6 with Figure 5, the input line current in the circuit with the Zener diode is not as heavily distorted. Specifically, in Figure 6 the power is 30.1 watts, PF is 0.995, and THD is only 6.8%. Observe that the MULT input signal (the lower waveform) of Figure 6 is not shaped like the rectified sinusoid typically found in circuits that use TM PFC ICs and which is seen in Figure 5. In other words, the circuit 100 generates a unique reference signal for the multiplier input of the TM PFC IC 9that results in superior performance of the application circuit at large load power range and/or a large input voltage range.

Figures 7 and 8 are waveform traces comparing the input line current THD (upper waveforms) and the MULT input signal (lower waveforms) for, respectively, the circuit of Figure 2 with the Zener diode 146 omitted and with Zener diode 146 included, for a two 26watt lamp load at 120 volts. At this low input voltage range, the advantages of the circuit lOwith the Zener diode 146 are evident but are not significant. Specifically, in Figure 7 the power is 56.1 watts, PF is 0.997, and THD is 5.8%, while in Figure 8 the power is 57.3watts, PF is 0.998, and THD is 4.5%.

Figures 9 and 10 are waveform traces comparing the input line current THD (upper waveforms) and the MULT input signal (lower waveforms) for, respectively, the circuit of Figure 2 with the Zener diode 146 omitted and with Zener diode 146 included, for a two 26watt lamp load at 277 volts. As can be seen in Figure 9, the input line current is heavily distorted. Specifically, in Figure 9 the power is 56.1 watts, PF is 0.992, and THD is an unacceptable 12.5%. However, as can be seen by comparing Figure 10 with Figure 9, the input line current in the circuit with the Zener diode is not as heavily distorted. Specifically, in Figure 10 the power is 58 watts, PF is 0.998, and THD is only 4.5%. The resulting performance improvement with the use of circuit 100 is quite noticeable.

Figure 11 is a schematic circuit diagram of a circuit in accordance with the present invention for changing the value of a resistance used to generate an input voltage to the multiplier input pin of a power factor correction integrated circuit. The EMI circuit 1020, the bridge circuit 1030, the input capacitor 1044, and the divider 1050 function in the same manner as, respectively, the EMI circuit 120, the bridge circuit 130, the input capacitor 144,and the divider 150 of Figure 2. An average rectified line voltage detector 1080 operates by charging capacitor 1092 through resistor 1082 from the divider 1050 (illustratively from a point between resistors 1058 and 1060) when the rectified line voltage is high, and discharging the capacitor 1092 through resistor 1094 when the rectified line voltage is low. When the stored (averaged) voltage across the capacitor 1092 exceeds a threshold value established by Zener diode 1084 and resistors 1086 and 1088 (capacitor 1090 is a filtering capacitor), a voltage sufficient to turn ON transistor 1074 in the switched resistivity path 1070 is applied to its base to place resistor 1072 in parallel with the resistor 1062, thereby actively lowering the resistance between the multiplier pin 3 to ground and reducing the multiplier input voltage applied to the multiplier pin 3. It will be appreciated that the use of the particular average voltage detector 1080 is illustrative, and that other average voltage detectors as well as other type of detectors such as peak voltage detectors may be used. Moreover, the particular switched resistivity path 1070 is illustrative, and other types of components may be used to create a switched resistivity path and other techniques may be used to actively change any impedance in the rectified line voltage divider 1050 to in effect limit the multiplier input voltage range. Selection of particular component values depends on a number of factors such as the input line voltage, power dissipation, and component availability and cost, in a manner well known in the art.

The circuits of Figures 2 and 11 are suitable for a great variety of wide range voltage applications, including electronic lamp ballasts, AC-DC adapters, low power SMPS, low end monitors, power supplies, boost topology pre-regulators, PFC flyback topology, PFC buck-boost topology, and so forth.

The description of the invention and its applications as set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. Nariations and modifications of the embodiments disclosed herein are possible, and practical alternatives to and equivalents of the various elements of the embodiments are known to those of ordinary skill in the art. These and other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention as set forth in the following claims.

Claims

CLAIMS:

1. A power factor correction application comprising: a transition mode power factor correction circuit (9) having a multiplier input

(3); an input voltage bus (140, 1040); a voltage divider (150, 1050) coupled to the input voltage bus, the voltage divider having a first intermediate node coupled to the multiplier input of the power factor correction circuit and a second intermediate node; and a voltage range reducing circuit (146, 1070, 1080) coupled to the second intermediate node of the voltage divider.

2. A power factor correction application as in claim 1 wherein the voltage range reducing circuit comprises a threshold conductance device (146) coupled to the second intermediate node of the voltage divider (150).

3. A power factor correction application as in claim 2 wherein the threshold conductance device comprises a Zener diode (146).

4. A power factor correction application as in claim 1, wherein the transition mode power factor correction circuit comprises a boost converter equipped with an inductive element (48), a unidirectional element (58), a switching element (54) and a control circuit coupled with a control electrode of the switching element for rendering said switching element conducting and non-conducting, said multiplier input being part of said control circuit.

5. A power factor correction application as in claim 1, wherein the voltage range reducing circuit comprises: a voltage level detector (1080) having an input coupled to the input voltage bus and having an output; and a controllable impedance path (1070) coupled to a segment of the voltage divider and having an input coupled to the output of the voltage level detector.

6. A power factor correction application as in claim 1 further comprising a ground bus (142, 1042) and wherein the voltage divider (150, 1050) is coupled between the input voltage bus (140, 1040) and the ground bus.

7. A power factor correction application as in claim 3, further comprising at least one additional diode coupled between the Zener diode and the ground bus.

8. A power factor correction application as in claim 6, wherein: the voltage divider comprises a first resistance (1062), a second resistance

(1060), and a third resistance (1052, 1054, 1056, 1058) coupled in series, the first intermediate node being between the first and second resistances and the second intermediate node being between the second and third resistances; the voltage range reducing circuit comprises a voltage level detector (1080) coupled between the second intermediate node of the voltage divider and the ground bus (1042) and having an output; and the voltage range reducing circuit further comprises a controllable resistivity path (1070) coupled between the first intermediate node of the voltage divider and the ground bus and having an input coupled to the output of the voltage level detector.

9. A power factor correction application as in claim 8, wherein the voltage level detector comprises a voltage peak detector or a voltage averaging detector (1080).

10. A power factor correction application as in claim 8, wherein the controllable resistivity path comprises a resistor (1072) in series with a transistor (1074). applying the rectified line voltage to the voltage divider; and connecting the resistance in parallel to a segment (1062) of the voltage divider when the rectified line voltage is greater than the predetermined value.