WO2000077820A3 - Operating system page placement to maximize cache data reuse - Google Patents

Operating system page placement to maximize cache data reuse Download PDF

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Publication number
WO2000077820A3
WO2000077820A3 PCT/US2000/014851 US0014851W WO0077820A3 WO 2000077820 A3 WO2000077820 A3 WO 2000077820A3 US 0014851 W US0014851 W US 0014851W WO 0077820 A3 WO0077820 A3 WO 0077820A3
Authority
WO
WIPO (PCT)
Prior art keywords
pages
operating system
hot
conflict
memory
Prior art date
Application number
PCT/US2000/014851
Other languages
French (fr)
Other versions
WO2000077820A2 (en
Inventor
Bodo Parady
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to DE60001170T priority Critical patent/DE60001170T2/en
Priority to AT00937935T priority patent/ATE230860T1/en
Priority to AU53047/00A priority patent/AU5304700A/en
Priority to EP00937935A priority patent/EP1190438B1/en
Publication of WO2000077820A2 publication Critical patent/WO2000077820A2/en
Publication of WO2000077820A3 publication Critical patent/WO2000077820A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/126Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning

Abstract

A software methodology to control replacement of one or more selected pages within a cache memory in a computer system. The operating system designates one or more pages containing critical data, text or other digital information as hot pages within a physical system memory in the computer system and prevents replacement during execution of various application programs of these hot pages when cached. The operating system inhibits allocation of the conflict pages that would map to cache locations occupied by a cached hot page, thereby preserving the hot page within the cache memory. The conflict pages are placed at the bottom of a free list created in the system memory by the operating system. The operating system scans the free list using a pointer while allocating free system memory space at run-time. The system memory pages are allocated from the free list until the pointer reaches a conflict page. This allows the operating system to prevent the conflict pages from getting cached to the hot page location within the cache memory. The operating system can also allow a user to designate one or more hot pages during run-time. The user is warned when the number of hot pages reaches or exceeds a predetermined limit.
PCT/US2000/014851 1999-06-15 2000-05-30 Operating system page placement to maximize cache data reuse WO2000077820A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE60001170T DE60001170T2 (en) 1999-06-15 2000-05-30 OPERATING SYSTEM PAGE LOCATION TO MAXIMIZE CACHE DATA REUSE
AT00937935T ATE230860T1 (en) 1999-06-15 2000-05-30 OPERATING SYSTEM PAGE PLACEMENT TO MAXIMIZE CACHE DATA REUSE
AU53047/00A AU5304700A (en) 1999-06-15 2000-05-30 Operating system page placement to maximize cache data reuse
EP00937935A EP1190438B1 (en) 1999-06-15 2000-05-30 Operating system page placement to maximize cache data reuse

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/333,418 1999-06-15
US09/333,418 US6408368B1 (en) 1999-06-15 1999-06-15 Operating system page placement to maximize cache data reuse

Publications (2)

Publication Number Publication Date
WO2000077820A2 WO2000077820A2 (en) 2000-12-21
WO2000077820A3 true WO2000077820A3 (en) 2001-06-28

Family

ID=23302686

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/014851 WO2000077820A2 (en) 1999-06-15 2000-05-30 Operating system page placement to maximize cache data reuse

Country Status (6)

Country Link
US (1) US6408368B1 (en)
EP (1) EP1190438B1 (en)
AT (1) ATE230860T1 (en)
AU (1) AU5304700A (en)
DE (1) DE60001170T2 (en)
WO (1) WO2000077820A2 (en)

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US7111141B2 (en) * 2000-10-17 2006-09-19 Igt Dynamic NV-RAM
US8550922B2 (en) 2006-03-03 2013-10-08 Igt Game removal with game history
EP1470476A4 (en) * 2002-01-31 2007-05-30 Arc Int Configurable data processor with multi-length instruction set architecture
US6996676B2 (en) * 2002-11-14 2006-02-07 International Business Machines Corporation System and method for implementing an adaptive replacement cache policy
US6952760B2 (en) * 2003-05-21 2005-10-04 Sun Microsystems, Inc. Methods and systems for memory allocation
US7165147B2 (en) * 2003-07-22 2007-01-16 International Business Machines Corporation Isolated ordered regions (IOR) prefetching and page replacement
US20050091224A1 (en) * 2003-10-22 2005-04-28 Fisher James A. Collaborative web based development interface
US7418582B1 (en) 2004-05-13 2008-08-26 Sun Microsystems, Inc. Versatile register file design for a multi-threaded processor utilizing different modes and register windows
US7543132B1 (en) 2004-06-30 2009-06-02 Sun Microsystems, Inc. Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes
US7290116B1 (en) 2004-06-30 2007-10-30 Sun Microsystems, Inc. Level 2 cache index hashing to avoid hot spots
US7509484B1 (en) 2004-06-30 2009-03-24 Sun Microsystems, Inc. Handling cache misses by selectively flushing the pipeline
US7571284B1 (en) 2004-06-30 2009-08-04 Sun Microsystems, Inc. Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
US20060129740A1 (en) * 2004-12-13 2006-06-15 Hermann Ruckerbauer Memory device, memory controller and method for operating the same
US7487320B2 (en) * 2004-12-15 2009-02-03 International Business Machines Corporation Apparatus and system for dynamically allocating main memory among a plurality of applications
US7951008B2 (en) * 2006-03-03 2011-05-31 Igt Non-volatile memory management technique implemented in a gaming machine
US20080189495A1 (en) * 2007-02-02 2008-08-07 Mcbrearty Gerald Francis Method for reestablishing hotness of pages
US7747820B2 (en) * 2007-06-15 2010-06-29 Microsoft Corporation Managing working set use of a cache via page coloring
US20150052326A1 (en) * 2013-08-19 2015-02-19 International Business Machines Corporation User-controlled paging
CN109857681B (en) 2017-11-30 2023-07-18 华为技术有限公司 Cache address mapping method and related equipment
US20190034337A1 (en) * 2017-12-28 2019-01-31 Intel Corporation Multi-level system memory configurations to operate higher priority users out of a faster memory level
US11764940B2 (en) 2019-01-10 2023-09-19 Duality Technologies, Inc. Secure search of secret data in a semi-trusted environment using homomorphic encryption

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WO1983000758A1 (en) * 1981-08-18 1983-03-03 Schkolnick, Mario Thrashing reduction in demand accessing of a data base through an lru paging buffer pool
EP0568221A1 (en) * 1992-04-29 1993-11-03 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature

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Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1983000758A1 (en) * 1981-08-18 1983-03-03 Schkolnick, Mario Thrashing reduction in demand accessing of a data base through an lru paging buffer pool
EP0568221A1 (en) * 1992-04-29 1993-11-03 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DONG R. K., GILDEA M. C., SITLER W. R.: "LEAST RECENTLY USED APPARATUS ALTERATION TO MAINTAIN RETRIABLE DATA IN A MULTIPROCESSOR SYSTEM", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 27, no. 9, 1 February 1985 (1985-02-01), New York, US, pages 5339, XP002147071 *

Also Published As

Publication number Publication date
US6408368B1 (en) 2002-06-18
ATE230860T1 (en) 2003-01-15
AU5304700A (en) 2001-01-02
WO2000077820A2 (en) 2000-12-21
EP1190438A2 (en) 2002-03-27
DE60001170D1 (en) 2003-02-13
DE60001170T2 (en) 2003-07-31
EP1190438B1 (en) 2003-01-08

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