WO2001003298A1 - Oscillator circuit - Google Patents

Oscillator circuit Download PDF

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Publication number
WO2001003298A1
WO2001003298A1 PCT/EP2000/005635 EP0005635W WO0103298A1 WO 2001003298 A1 WO2001003298 A1 WO 2001003298A1 EP 0005635 W EP0005635 W EP 0005635W WO 0103298 A1 WO0103298 A1 WO 0103298A1
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WO
WIPO (PCT)
Prior art keywords
circuit
capacitors
capacitor array
voltage
current
Prior art date
Application number
PCT/EP2000/005635
Other languages
French (fr)
Inventor
Richard Goldman
Robin Wilson
Original Assignee
Telefonaktiebolaget Lm Ericsson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson filed Critical Telefonaktiebolaget Lm Ericsson
Priority to EP00942099A priority Critical patent/EP1196993B1/en
Priority to KR1020017016649A priority patent/KR20020019110A/en
Priority to AU56837/00A priority patent/AU5683700A/en
Priority to CA002377969A priority patent/CA2377969A1/en
Priority to DE60031408T priority patent/DE60031408D1/en
Priority to JP2001508596A priority patent/JP2003504910A/en
Publication of WO2001003298A1 publication Critical patent/WO2001003298A1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/011Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231Astable circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/354Astable circuits

Definitions

  • This invention relates to an oscillator circuit, for example for generating a clock signal in an integrated circuit .
  • Oscillator circuits are commonly used in integrated circuits to provide clock signals.
  • the frequency of the resulting clock signal depends on parameters of the oscillator circuit.
  • US-5,859,571 discloses a frequency trimmable oscillator, in which a current generator provides an output current, and also generates two threshold voltages.
  • the current is switched into a delay unit, which includes two arrays of capacitors, one for providing coarse trimming of the output frequency, and one for providing fine trimming.
  • the voltage on the capacitors is compared with the two threshold voltages, and the results of the comparisons are used to set and reset a flip-flop, with the time taken for each such cycle being the period of the output clock signal, such that the frequency is dependent on the value of the trimmed capacitance and is hence adjustable as desired.
  • this circuit requires two arrays of capacitors.
  • each capacitor has an associated parasitic capacitance.
  • an oscillator circuit includes a current generator producing a current which is trimmable by means of a resistor array, and thus includes only a single capacitor array.
  • an oscillator circuit includes a current generator which supplies current to input terminals of capacitors in a trimmable capacitor array.
  • FIG. 1 is a block diagram of an oscillator circuit in accordance with the invention.
  • Figure 2 is a schematic circuit diagram of a first sub-circuit forming part of the circuit of Figure 1.
  • Figure 3 is a schematic circuit diagram of a second sub-circuit forming part of the circuit of Figure 1.
  • Figure 4 is a schematic circuit diagram of a third sub-circuit forming part of the circuit of Figure 1.
  • Figure 5 is a timing diagram for explaining the operation of the circuit of Figure 1. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • FIG. 1 shows an oscillator circuit in accordance with aspects of the present invention.
  • the oscillator circuit of Figure 1 includes a control circuit 2, which includes a current source 4.
  • the current source 4 generates a current of magnitude Iset, which can be forced to flow out of or into the current source 4.
  • the current source 4 further generates first and second threshold voltages Vu, VI, which are supplied as inputs to respective comparators 6, 8.
  • the other inputs to these comparators 6, 8 are each supplied with a voltage of magnitude Vramp .
  • the outputs of the comparators 6, 8 are connected to the Set and Reset terminals respectively of a flip-flop 10, and the output of the flip-flop 10 is fed back to the current source 4, and is also fed to a circuit output 12 is an output clock signal .
  • a variable resistance circuit 14, including a resistor array 16, is connected to the current source 4, to alter the magnitude Iset of the current output therefrom.
  • An operational amplifier 18 has its non-inverting input terminal 20 connected to a fixed reference voltage Vref, which may also be provided by the control circuit 2 if desired.
  • the inverting input terminal 22 of the operational amplifier 20 is connected to an output of the current source 4.
  • the output terminal 24 of the operational amplifier 18 provides an amplifier output voltage Vramp which, as mentioned above, is supplied to the control circuit 2 as an input to each of the comparators 6, 8.
  • the operational amplifier 18 is generally conventional, and will not be described further herein.
  • a capacitor array 26 is connected between the operational amplifier output terminal 24 and inverting input terminal 22, and thus forms a feedback loop around the amplifier.
  • the voltage at the operational amplifier non-inverting input 20 is held constant relative to the supply voltage, the voltage at the operational amplifier inverting input 22 is also held relatively constant .
  • the capacitor array includes a fixed capacitance (not shown in Figure 1) and a plurality of capacitors, which can be switched into or out of the circuit by means of a multiple bit digital signal.
  • a multiple bit digital signal In a preferred embodiment, there are nine such capacitors, but Figure 1 shows only two capacitors CO, Cl, for clarity.
  • Each capacitor CO, Cl, ... has a first terminal connected to the amplifier inverting input terminal 22 through a first respective switch 28.0, 28.1, ..., or is connected to ground through a second respective switch 30.0, 30.1, ....
  • the switches are controlled by control bits B0, Bl, ..., such that, when a control bit is high, the respective first switch is closed, and, when a control bit is low, the respective second switch is closed.
  • each capacitor CO, Cl, ... in the array 26 has an associated parasitic capacitance. Specifically, as shown in Figure 1, there is a parasitic capacitance 32.0, 32.1, ... between the first capacitor terminal and the substrate, and a parasitic capacitance 34.0, 34.1, ... between the second capacitor terminal and substrate.
  • FIG. 2 is a schematic circuit diagram of the control circuit 2 of Figure 1.
  • the control circuit includes a voltage divider 202 which provides the reference voltage Vref to the non- inverting input terminal of the operational amplifier 18.
  • the control circuit also includes a current source 204, which has connections for the variable resistor array 16, and is controlled by the inverted circuit output voltage to produce the current output Iset .
  • the first threshold voltage Vu is the gate voltage of PMOS transistors 206, 208
  • the lower threshold voltage VI is the gate voltage of MOS transistors 210, 212.
  • the control circuit 2 also includes a sub-unit 214 with comparators and a flip-flop, producing the inverted circuit output voltage .
  • FIG 3 is a schematic circuit diagram of the variable resistor array 14 of Figure 1.
  • the resistor array 14 includes four resistors 302, 304, 306, 308, and four CMOS switches 310, 312, 314, 316, which are of generally known type .
  • the switches are connected in series with a fifth resistor 322 between terminals 318, 320, which are themselves connected to the current source 4.
  • the switches 310, 312, 314, 316 are controlled by the binary signals DO, Dl, D2 , D3 respectively. When the respective binary value is low, the switch is closed, and when the respective binary value is high, the switch is open and the corresponding resistor is switched into the circuit.
  • the resistor 302 has a value of 21k ⁇
  • the resistors can advantageously be formed from blocks of matched resistors of value 21k ⁇ .
  • the resistance value of the resistor array 14 can be varied between 315k ⁇ , if the switches are all closed, and 630k ⁇ , if the switches are all open.
  • FIG 4 is a schematic circuit diagram of the variable capacitor array 26 of Figure 1.
  • the capacitor array 26 includes nine capacitors 501, ..., 509, each connected in series with a respective switch 510, ..., 518 between terminals 519, 520 in the feedback loop of the operational amplifier 18. Also connected in parallel with the nine capacitors 501, ..., 509 is a capacitor 521.
  • Each of the switches 510, ..., 518 is of the type shown in Figure 1, and is controlled by a respective binary digit B0, ...,B8. When the respective binary value is low, the corresponding capacitor is switched into the circuit, and when the corresponding binary value is high, the switch is open and the corresponding capacitor is switched out of the circui .
  • the capacitor 510 has a value of 0.152pF
  • capacitor 511 has a value of 2x0.152pF
  • capacitor 512 has a value of 4x0.152pF
  • capacitor 513 has a value of 8x0.152pF
  • capacitor 514 has a value of 16x0.152pF
  • capacitor 515 has a value of 32x0.152pF
  • capacitor 516 has a value of 64x0.152pF
  • capacitor 517 has a value of 128x0.152pF
  • capacitor 518 has a value of 256x0.152pF
  • capacitor 521 has a value of 305.5pF.
  • These capacitors can advantageously be formed from blocks of matched capacitors of value 0.152pF, or 8x0.152pF, or 64x0.152pF.
  • the capacitance value of the capacitor array 26 can be varied between 305.5pF, if all of the binary values B0-B9 are high and the corresponding capacitors are all switched out of the circuit, and 305.5pF + 511x0.152pF, if all of the binary values are low and the corresponding capacitors are all switched into the circuit.
  • Integrated Circuit capacitors can have good matching, which allows a highly linear relationship between the value of the binary word B0-B9 and the trimmed capacitance value .
  • the current source 4 produces a current Iset which is a function of the positive supply voltage, and is inversely proportional to the coarse trimmed resistance value of the resistor array 16.
  • the current source 4 can act as a source or sink, and the direction of the current depends on the sign of the signal Vo at output 12 which is fed back to the current source.
  • this signal When this signal is high, current flows into the current source 4 from the capacitor array 26, as shown by the arrow in Figure 1.
  • this signal is low, current flows from the current source 4 into the capacitor array 26.
  • the current Iset by flowing through the capacitor array 26, causes the output voltage Vramp of the operational amplifier 18 to increase or decrease linearly.
  • the threshold voltages VI, Vu are set by the current source 4, and they are affected by changes in the supply voltage in the same way as the current Iset.
  • the frequency of oscillation Fosc is the inverse of the period of one cycle.
  • the period of one cycle is twice the time ⁇ t taken for the operational amplifier output voltage Vramp to increase from VI to Vu, or fall from Vu to VI.
  • the upper and lower thresholds Vu, VI, and the current Iset might be related to the supply voltage Vdd and resistance Rset of the resistor array by equations such as :
  • Vu Vdd - Vxl
  • V ⁇ Vx2
  • Iset (Vdd - Vxl - Vx2) I Rset where Vxl and Vx2 are unknown voltages . This gives :
  • the frequency of oscillation is controlled by the trimmed values of resistance and capacitance, but is independent of fluctuations in the supply voltage Vdd.
  • the capacitors C0-C8 have parasitic capacitances associated therewith.
  • the circuit of the present invention minimizes any problems caused thereby.
  • the operational amplifier 18 has a high gain, and the non-inverting input terminal is held at a constant voltage.
  • the operational amplifier acts to keep the voltages at its two input terminals at the same level, and the voltage at the inverting input is kept generally constant. As a result, the voltages across the parasitic capacitances 32.0, 32.1 etc.
  • the oscillator frequency Fosc has an accurate and linear relationship to the total value of the intended capacitance Ct .

Abstract

An oscillator circuit includes a current generator (4) which supplies current to input terminals of capacitors (C0, C1) in a trimmable capacitor array. The input terminals of the capacitors are held at a relatively constant voltage, and thus all of the current from the current generator passes through the desired capacitors of the capacitor array, thus minimizing the effetct of parasitic capacitance.

Description

OSCILLATOR CIRCUIT TECHNICAL FIELD
This invention relates to an oscillator circuit, for example for generating a clock signal in an integrated circuit .
BACKGROUND OF THE INVENTION
Oscillator circuits are commonly used in integrated circuits to provide clock signals. The frequency of the resulting clock signal depends on parameters of the oscillator circuit. In an integrated circuit, it is typically not possible to manufacture the oscillator circuit components with sufficient precision to provide a clock frequency with a desired accuracy. Therefore, it is known to manufacture an oscillator circuit whose frequency is trimmable. That is, the frequency is adjustable, after manufacture, by means of an input signal, for example a multi-bit digital signal. Thus, the frequency can be brought accurately to the desired value.
US-5,859,571 discloses a frequency trimmable oscillator, in which a current generator provides an output current, and also generates two threshold voltages. The current is switched into a delay unit, which includes two arrays of capacitors, one for providing coarse trimming of the output frequency, and one for providing fine trimming. The voltage on the capacitors is compared with the two threshold voltages, and the results of the comparisons are used to set and reset a flip-flop, with the time taken for each such cycle being the period of the output clock signal, such that the frequency is dependent on the value of the trimmed capacitance and is hence adjustable as desired. However, as mentioned above, this circuit requires two arrays of capacitors. Moreover, each capacitor has an associated parasitic capacitance. It is an inherent feature of integrated circuit capacitors that the value of the parasitic capacitance is not as well controlled as the value of the intended capacitance. Therefore, while the output frequency of the oscillator should desirably vary linearly with the intended trimmed capacitance value, in practice this can only be achieved to a limited extent . SUMMARY OF THE INVENTION In accordance with a preferred aspect of the invention, an oscillator circuit includes a current generator producing a current which is trimmable by means of a resistor array, and thus includes only a single capacitor array. In accordance with a further preferred aspect of the invention, an oscillator circuit includes a current generator which supplies current to input terminals of capacitors in a trimmable capacitor array. The input terminals of Mie capacitors are held at a relatively constant voltage, and thus all of the current from the current generator passes through the desired capacitors of the capacitor array, thus minimizing the effect of parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an oscillator circuit in accordance with the invention.
Figure 2 is a schematic circuit diagram of a first sub-circuit forming part of the circuit of Figure 1. Figure 3 is a schematic circuit diagram of a second sub-circuit forming part of the circuit of Figure 1.
Figure 4 is a schematic circuit diagram of a third sub-circuit forming part of the circuit of Figure 1. Figure 5 is a timing diagram for explaining the operation of the circuit of Figure 1. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Figure 1 shows an oscillator circuit in accordance with aspects of the present invention. The oscillator circuit of Figure 1 includes a control circuit 2, which includes a current source 4. The current source 4 generates a current of magnitude Iset, which can be forced to flow out of or into the current source 4. The current source 4 further generates first and second threshold voltages Vu, VI, which are supplied as inputs to respective comparators 6, 8. The other inputs to these comparators 6, 8 are each supplied with a voltage of magnitude Vramp . The outputs of the comparators 6, 8 are connected to the Set and Reset terminals respectively of a flip-flop 10, and the output of the flip-flop 10 is fed back to the current source 4, and is also fed to a circuit output 12 is an output clock signal .
A variable resistance circuit 14, including a resistor array 16, is connected to the current source 4, to alter the magnitude Iset of the current output therefrom.
An operational amplifier 18 has its non-inverting input terminal 20 connected to a fixed reference voltage Vref, which may also be provided by the control circuit 2 if desired. The inverting input terminal 22 of the operational amplifier 20 is connected to an output of the current source 4. The output terminal 24 of the operational amplifier 18 provides an amplifier output voltage Vramp which, as mentioned above, is supplied to the control circuit 2 as an input to each of the comparators 6, 8. The operational amplifier 18 is generally conventional, and will not be described further herein.
A capacitor array 26 is connected between the operational amplifier output terminal 24 and inverting input terminal 22, and thus forms a feedback loop around the amplifier.
Since the voltage at the operational amplifier non-inverting input 20 is held constant relative to the supply voltage, the voltage at the operational amplifier inverting input 22 is also held relatively constant .
The capacitor array includes a fixed capacitance (not shown in Figure 1) and a plurality of capacitors, which can be switched into or out of the circuit by means of a multiple bit digital signal. In a preferred embodiment, there are nine such capacitors, but Figure 1 shows only two capacitors CO, Cl, for clarity. Each capacitor CO, Cl, ... has a first terminal connected to the amplifier inverting input terminal 22 through a first respective switch 28.0, 28.1, ..., or is connected to ground through a second respective switch 30.0, 30.1, .... The switches are controlled by control bits B0, Bl, ..., such that, when a control bit is high, the respective first switch is closed, and, when a control bit is low, the respective second switch is closed. Each capacitor CO, Cl, ... further has a second terminal connected to the operational amplifier output terminal 24. It is relevant that each capacitor CO, Cl, ... in the array 26 has an associated parasitic capacitance. Specifically, as shown in Figure 1, there is a parasitic capacitance 32.0, 32.1, ... between the first capacitor terminal and the substrate, and a parasitic capacitance 34.0, 34.1, ... between the second capacitor terminal and substrate.
Figure 2 is a schematic circuit diagram of the control circuit 2 of Figure 1. The control circuit includes a voltage divider 202 which provides the reference voltage Vref to the non- inverting input terminal of the operational amplifier 18. The control circuit also includes a current source 204, which has connections for the variable resistor array 16, and is controlled by the inverted circuit output voltage to produce the current output Iset . The first threshold voltage Vu is the gate voltage of PMOS transistors 206, 208, and the lower threshold voltage VI is the gate voltage of MOS transistors 210, 212. The control circuit 2 also includes a sub-unit 214 with comparators and a flip-flop, producing the inverted circuit output voltage .
Figure 3 is a schematic circuit diagram of the variable resistor array 14 of Figure 1. The resistor array 14 includes four resistors 302, 304, 306, 308, and four CMOS switches 310, 312, 314, 316, which are of generally known type . The switches are connected in series with a fifth resistor 322 between terminals 318, 320, which are themselves connected to the current source 4. The switches 310, 312, 314, 316 are controlled by the binary signals DO, Dl, D2 , D3 respectively. When the respective binary value is low, the switch is closed, and when the respective binary value is high, the switch is open and the corresponding resistor is switched into the circuit. In the preferred embodiment, the resistor 302 has a value of 21kΩ, resistor 304 has a value of 2x21 = 42kΩ, resistor 306 has a value of 4x21 = 84kΩ, resistor 308 has a value of 8x21 = 168kΩ, and resistor 322 has a value of 15x21 = 315kΩ. The resistors can advantageously be formed from blocks of matched resistors of value 21kΩ. Thus, by switching the resistors 302, 304, 306, 308 into or out of the circuit by means of the control bits DO-3, the resistance value of the resistor array 14 can be varied between 315kΩ, if the switches are all closed, and 630kΩ, if the switches are all open.
Figure 4 is a schematic circuit diagram of the variable capacitor array 26 of Figure 1. The capacitor array 26 includes nine capacitors 501, ..., 509, each connected in series with a respective switch 510, ..., 518 between terminals 519, 520 in the feedback loop of the operational amplifier 18. Also connected in parallel with the nine capacitors 501, ..., 509 is a capacitor 521. Each of the switches 510, ..., 518 is of the type shown in Figure 1, and is controlled by a respective binary digit B0, ...,B8. When the respective binary value is low, the corresponding capacitor is switched into the circuit, and when the corresponding binary value is high, the switch is open and the corresponding capacitor is switched out of the circui .
In the preferred embodiment, the capacitor 510 has a value of 0.152pF, capacitor 511 has a value of 2x0.152pF, capacitor 512 has a value of 4x0.152pF, capacitor 513 has a value of 8x0.152pF, capacitor 514 has a value of 16x0.152pF, capacitor 515 has a value of 32x0.152pF, capacitor 516 has a value of 64x0.152pF, capacitor 517 has a value of 128x0.152pF, and capacitor 518 has a value of 256x0.152pF, while capacitor 521 has a value of 305.5pF. These capacitors can advantageously be formed from blocks of matched capacitors of value 0.152pF, or 8x0.152pF, or 64x0.152pF.
Thus, by switching the capacitors 510, ..., 518 into or out of the circuit by means of the control bits B0 -8, the capacitance value of the capacitor array 26 can be varied between 305.5pF, if all of the binary values B0-B9 are high and the corresponding capacitors are all switched out of the circuit, and 305.5pF + 511x0.152pF, if all of the binary values are low and the corresponding capacitors are all switched into the circuit. Integrated Circuit capacitors can have good matching, which allows a highly linear relationship between the value of the binary word B0-B9 and the trimmed capacitance value .
Thus, in operation of the circuit of Figures 1-4, the current source 4 produces a current Iset which is a function of the positive supply voltage, and is inversely proportional to the coarse trimmed resistance value of the resistor array 16. The current source 4 can act as a source or sink, and the direction of the current depends on the sign of the signal Vo at output 12 which is fed back to the current source. When this signal is high, current flows into the current source 4 from the capacitor array 26, as shown by the arrow in Figure 1. When this signal is low, current flows from the current source 4 into the capacitor array 26.
The current Iset, by flowing through the capacitor array 26, causes the output voltage Vramp of the operational amplifier 18 to increase or decrease linearly.
Thus, as shown in Figure 5, when Vo is low, Vramp falls until it reaches the lower threshold VI, at which time the comparator 8 sends a pulse to the Reset input of the flip-flop 10. The output Vo then goes high, and Vramp begins to rise. Vramp continues to rise until it reaches the upper threshold Vu, at which time the comparator 6 sends a pulse to the Set input of the flip-flop 10. Thus, the circuit produces an oscillating output Vo, as shown in Figure 6.
As mentioned above, the threshold voltages VI, Vu are set by the current source 4, and they are affected by changes in the supply voltage in the same way as the current Iset. The frequency of oscillation Fosc is the inverse of the period of one cycle. The period of one cycle is twice the time Δt taken for the operational amplifier output voltage Vramp to increase from VI to Vu, or fall from Vu to VI. Thus, if (Vu - VI) = ΔV, and the total selected capacitance of the array 26 is Ct , then :
1 Iset Fosc =
2 At CtΛV
Typically, the upper and lower thresholds Vu, VI, and the current Iset might be related to the supply voltage Vdd and resistance Rset of the resistor array by equations such as :
Vu = Vdd - Vxl
VΪ = Vx2
Iset = (Vdd - Vxl - Vx2) I Rset where Vxl and Vx2 are unknown voltages . This gives :
Vdd - Vx\ - Vx2 Fosc =
Ct. Rset (Vdd - Vxl - Vxl) Ct. Rset
Thus, the frequency of oscillation is controlled by the trimmed values of resistance and capacitance, but is independent of fluctuations in the supply voltage Vdd. As mentioned previously, the capacitors C0-C8 have parasitic capacitances associated therewith. However, the circuit of the present invention minimizes any problems caused thereby. Specifically, referring to Figure 1, the operational amplifier 18 has a high gain, and the non-inverting input terminal is held at a constant voltage. Thus, the operational amplifier acts to keep the voltages at its two input terminals at the same level, and the voltage at the inverting input is kept generally constant. As a result, the voltages across the parasitic capacitances 32.0, 32.1 etc. stay generally constant, and all of the current Iset passes through the relevant capacitor CO, Cl etc, rather than through the parasitic capacitance. While current does pass through the parasitic capacitances 34.0, 34.1 etc, this is derived from the operational amplifier 18, rather than from the current Iset .
As a result, the oscillator frequency Fosc has an accurate and linear relationship to the total value of the intended capacitance Ct . There is thus described an oscillator circuit which can be used in an integrated circuit and produces a output frequency which can be accurately controlled.

Claims

1. An oscillator circuit, comprising: a current supply circuit, for generating a reference current ; a capacitor array, comprising a plurality of capacitors and switches for switching the capacitors into and out of the circuit to control a total trimming capacitance value; and a timing circuit, connected to the capacitor array to receive a voltage across the capacitor array as an input thereto ; wherein the reference current is supplied to the capacitor array at respective first nodes of the plurality of capacitors to charge or discharge the capacitors switched into the circuit, and the timing circuit produces an output signal with a period which depends on the time taken for the voltage across the capacitor array to reach one or more threshold values; further comprising: an operational amplifier, having a first input terminal connected to a reference voltage, a second input terminal connected to the respective first nodes of the capacitors in the capacitor array, and an output terminal connected between the capacitor array and the timing circuit, such that the capacitor array forms a feedback loop around the operational amplifier, and such that the respective first nodes of the capacitors are held at a relatively constant voltage.
2. An oscillator circuit as claimed in claim 1, further comprising a resistor array, comprising a plurality of resistors and switches for switching the resistors into and out of the circuit to control a total trimming resistance value, the current source generating the reference current as a function of the trimming resistance value.
3. An oscillator circuit as claimed in claim 2, wherein the resistor array provides coarse trimming, and the capacitor array provides fine trimming.
4. An oscillator circuit as claimed in claim 1, wherein the reference current , and the or each voltage threshold value, are provided from a circuit supply voltage, such that any variations therein produce substantially no overall effect on the period of the output signal.
PCT/EP2000/005635 1999-07-01 2000-06-19 Oscillator circuit WO2001003298A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP00942099A EP1196993B1 (en) 1999-07-01 2000-06-19 Oscillator circuit
KR1020017016649A KR20020019110A (en) 1999-07-01 2000-06-19 Oscillator circuit
AU56837/00A AU5683700A (en) 1999-07-01 2000-06-19 Oscillator circuit
CA002377969A CA2377969A1 (en) 1999-07-01 2000-06-19 Oscillator circuit
DE60031408T DE60031408D1 (en) 1999-07-01 2000-06-19 OSCILLATOR CIRCUIT
JP2001508596A JP2003504910A (en) 1999-07-01 2000-06-19 Oscillation circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9915421.3 1999-07-01
GB9915421A GB2351619A (en) 1999-07-01 1999-07-01 A frequency trimmable oscillator with insensitivity to power supply variations and parasitic capacitance

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WO2001003298A1 true WO2001003298A1 (en) 2001-01-11

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EP (1) EP1196993B1 (en)
JP (1) JP2003504910A (en)
KR (1) KR20020019110A (en)
CN (1) CN1214525C (en)
AT (1) ATE343248T1 (en)
AU (1) AU5683700A (en)
CA (1) CA2377969A1 (en)
DE (1) DE60031408D1 (en)
GB (1) GB2351619A (en)
TW (1) TW478253B (en)
WO (1) WO2001003298A1 (en)

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US6326859B1 (en) 2001-12-04
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