WO2001005089A3 - Security chip architecture and implementations for cryptography acceleration - Google Patents

Security chip architecture and implementations for cryptography acceleration Download PDF

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Publication number
WO2001005089A3
WO2001005089A3 PCT/US2000/018545 US0018545W WO0105089A3 WO 2001005089 A3 WO2001005089 A3 WO 2001005089A3 US 0018545 W US0018545 W US 0018545W WO 0105089 A3 WO0105089 A3 WO 0105089A3
Authority
WO
WIPO (PCT)
Prior art keywords
cells
architecture
packets
processing
cryptography
Prior art date
Application number
PCT/US2000/018545
Other languages
French (fr)
Other versions
WO2001005089A2 (en
Inventor
Suresh Krishna
Christopher Owen
Original Assignee
Broadcom Corp
Suresh Krishna
Christopher Owen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp, Suresh Krishna, Christopher Owen filed Critical Broadcom Corp
Priority to EP00959143A priority Critical patent/EP1192783B1/en
Priority to DE60008109T priority patent/DE60008109T2/en
Priority to AT00959143T priority patent/ATE259130T1/en
Priority to AU70514/00A priority patent/AU7051400A/en
Publication of WO2001005089A2 publication Critical patent/WO2001005089A2/en
Publication of WO2001005089A3 publication Critical patent/WO2001005089A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
    • H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
    • H04L63/0485—Networking architectures for enhanced packet encryption processing, e.g. offloading of IPsec packet processing or efficient security association look-up
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/16—Implementing security features at a particular protocol layer
    • H04L63/164—Implementing security features at a particular protocol layer at the network layer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12—Protocol engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/12—Applying verification of the received information
    • H04L63/123—Applying verification of the received information received data contents, e.g. message integrity

Abstract

An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables 'cell-based' processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed-size 'cells'. The fixed-sized cells are then processed and reassembled into packets. The cell-based packet processing architecture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet data or control parameters.
PCT/US2000/018545 1999-07-08 2000-07-07 Security chip architecture and implementations for cryptography acceleration WO2001005089A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP00959143A EP1192783B1 (en) 1999-07-08 2000-07-07 Security chip architecture and implementations for cryptography acceleration
DE60008109T DE60008109T2 (en) 1999-07-08 2000-07-07 SECURITY CHIP ARCHITECTURE AND VERSIONS FOR CRYPTOGRAPHY SPEEDING
AT00959143T ATE259130T1 (en) 1999-07-08 2000-07-07 SECURITY CHIP ARCHITECTURE AND CRYPTOGRAPHY ACCELERATION DESIGNS
AU70514/00A AU7051400A (en) 1999-07-08 2000-07-07 Security chip architecture and implementations for cryptography acceleration

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US14287099P 1999-07-08 1999-07-08
US60/142,870 1999-07-08
US15901299P 1999-10-12 1999-10-12
US60/159,012 1999-10-12
US09/510,486 US6477646B1 (en) 1999-07-08 2000-02-23 Security chip architecture and implementations for cryptography acceleration
US09/510,486 2000-02-23

Publications (2)

Publication Number Publication Date
WO2001005089A2 WO2001005089A2 (en) 2001-01-18
WO2001005089A3 true WO2001005089A3 (en) 2001-09-27

Family

ID=27385867

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/018545 WO2001005089A2 (en) 1999-07-08 2000-07-07 Security chip architecture and implementations for cryptography acceleration

Country Status (6)

Country Link
US (3) US6477646B1 (en)
EP (1) EP1192783B1 (en)
AT (1) ATE259130T1 (en)
AU (1) AU7051400A (en)
DE (1) DE60008109T2 (en)
WO (1) WO2001005089A2 (en)

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Also Published As

Publication number Publication date
EP1192783B1 (en) 2004-02-04
US20060021022A1 (en) 2006-01-26
WO2001005089A2 (en) 2001-01-18
US6477646B1 (en) 2002-11-05
US20020199101A1 (en) 2002-12-26
ATE259130T1 (en) 2004-02-15
DE60008109T2 (en) 2004-07-08
AU7051400A (en) 2001-01-30
DE60008109D1 (en) 2004-03-11
EP1192783A2 (en) 2002-04-03
US7124296B2 (en) 2006-10-17
US6971006B2 (en) 2005-11-29

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