WO2001006552A1 - Conductivity reduction method for doped compound semiconductors - Google Patents

Conductivity reduction method for doped compound semiconductors Download PDF

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Publication number
WO2001006552A1
WO2001006552A1 PCT/US2000/017143 US0017143W WO0106552A1 WO 2001006552 A1 WO2001006552 A1 WO 2001006552A1 US 0017143 W US0017143 W US 0017143W WO 0106552 A1 WO0106552 A1 WO 0106552A1
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Prior art keywords
semiconductor
region
layer
group iii
group
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PCT/US2000/017143
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French (fr)
Inventor
Daniel P. Docter
Kursad Kiziloglu
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Hrl Laboratories, Llc
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Priority to AU57573/00A priority Critical patent/AU5757300A/en
Publication of WO2001006552A1 publication Critical patent/WO2001006552A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2258—Diffusion into or out of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T436/00—Chemistry: analytical and immunological testing
    • Y10T436/25—Chemistry: analytical and immunological testing including sample preparation

Definitions

  • the present invention relates to a method of reducing the conductivity (or charge) of a doped semiconductor.
  • the method may be conveniently used in a number of applications.
  • the method may be used to effectively perform the channel or gate recess etches commonly used in Metal Semiconductor Field Effect Transistor (MESFET) devices and High Electron Mobility Transistor (HEMT) devices, including Pseudomorphic High Electron Mobility transistor (PHEMT) devices.
  • the method may also be used to reduce the extrinsic base-collector capacitance in a semiconductor device As such the present invention also relates to devices manufactured according to this method.
  • Figure 1A depicts a substrate 10 having a buffer layer 11 disposed thereon which in turn has a channel layer 12 disposed thereon. On the channel layer is disposed a Schottky layer 13 and a contact layer 14 is formed on top of the Schottky layer.
  • Each of these layers are conventional epitaxial layers formed by methods known in the prior art. Additionally, these layers are generally formed of semiconductor materials from groups III and V of the Periodic Table of Elements and their alloys.
  • GaAs Gallium Arsenide
  • Indium Phosphide InP
  • AlGaAs Aluminum Gallium Arsenide
  • Indium Gallium Arsenide InGaAs
  • Indium Aluminum Arsenide InAlAs
  • metal source and drain contacts 15 and 16 are formed on contact layer 14 (see Figure 1C) .
  • This can be done by patterning a layer of photoresist 17, covering the patterned photoresist with metal 18 and, thereafter, lifting off the photoresist and the layer of metal disposed on top thereof in order to arrive at the structure shown in Figure 1C.
  • Those skilled in the art will realize, of course, that there are other ways of forming the source contact 15 and drain contact 16 shown in Figure 1C.
  • HEMT, PHEMT and MESFET devices are subjected to a second etch. If a second etch is used, the structure of Figure IE is covered with a photoresist which is patterned to form a region in the exposed portion 20 of Schottky layer 13 as shown in Figure IF.
  • the Schottky layer is subjected to a controlled etch which is called a channel recess etch. This particular etch is one of the most critical steps in the manufacture of prior art HEMT and PHEMT devices.
  • the most common process used for the gate recess etch previously described with reference to Figures ID and IE and the channel recess etch previously described with reference to Figure IF is typically a wet chemical etch which removes device material to the desired depth in the gate area of the device.
  • the channel etch is not monitored by depth, but rather by measuring the saturation current flowing from the source contact 15 to the drain contact 16 of exemplary HEMT devices being manufactured in a wafer.
  • many devices are normally manufactured at the same time on a common semiconductor wafer and the saturation current is measured only for a few exemplary devices being formed on the wafer. Presumably, the devices which are measured are representative of all the devices being manufactured on the wafer.
  • the exemplary devices may or may not be truly representative of all of the devices.
  • etching away the conductive material the conductivity in the channel decreases and therefore the saturation current decreases.
  • the measurement of the saturation current and the etch processing do not occur at the same time and therefore usually several cycles of etch processing and measuring are alternatingly utilized until the desired saturation current level is reached.
  • a gate structure 23 is formed and the patterned photoresist 22 is removed. If the
  • Schottky layer 13 includes Aluminum in the alloy thereof, which is commonly the case, a passivation layer 24 is conventionally applied. It is undesirable to expose Aluminum containing compounds to atmosphere since Aluminum is very reactive and subject to oxidation. The passivation layer 24 helps protect against such oxidation.
  • the present invention provides a method of reducing the conductivity of a layer of a group III-V semiconductor doped with a group IV semiconductor, the group III, IV and V semiconductors each having an atomic number with the atomic number of the group IV semiconductor being larger than the atomic numbers of each of the group III and group V semiconductors.
  • the method comprising the steps of forming a region of Si0 2 on the group III-V semiconductor layer; and annealing at least the semiconductor layer and the region of Si0 2 at a temperature sufficiently high to cause atoms of the group IV semiconductor to leach from the semiconductor layer into the region of Si0 2 -
  • the region of SiO z is optionally removed after the annealing step is performed.
  • the present invention provides a method of forming a gate region of a semiconductor device such as a PHEMT or a HEMT or a MESFET device.
  • the method includes the steps of (i) forming an layer of semiconductor layer doped with Sn; (ii) forming an region of Si0 2 on the semiconductor layer, the region of Si0 2 corresponding to the gate region to be formed; (iii) annealing at least the semiconductor layer and the region of Si0 2 at a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of Si0 2 and to thereby form a region in said semiconductor layer having a reduced concentration of Sn dopant, the annealing step occurring at a temperature sufficiently low and for a period of time sufficiently short to inhibit significant intermixing between the region of Si0 2 and the semiconductor layer; (iv) optionally removing the region of Si0 2 after the annealing step is performed; and (v) forming a gate electrode on said semiconductor layer.
  • the present invention provides a method of reducing base-collector capacitance of a semiconductor device having layer of a group III-v semiconductor which is doped with a group IV semiconductor.
  • the method includes the steps of: forming a region of Si0 2 on the group III-V semiconductor layer; annealing at least the semiconductor layer and the region of Si0 2 at a temperature sufficiently high to cause atoms of the group IV semiconductor to leach from at least a region of the group III-V semiconductor layer into the region of Si0 2 ; removing the region of
  • FIGS 1A through 1G depict the steps in manufacturing a prior art HEMT device
  • Figures 2A-2E depict the steps which may be used to define the channel (i.e., control the saturation current between the source and drain) without the need to expose any semiconductor compound which includes Aluminum to atmosphere and without the need to employ a passivation layer;
  • Figure 3A shows the resulting structure after a partial physical etch of the contact layer and a gate has been added
  • Figure 3B shows the resulting structure a gate has been added (without physically etching the contact layer) ;
  • Figure 4 depicts a semiconductor structure used for testing purposes ,-
  • Figure 5 shows room temperature photoluminescence data from as- grown and Si0 2 encapsulated, annealed samples of the structure shown in Figure 4;
  • Figure 6 shows X-ray data from as-grown and Si0 2 encapsulated, annealed samples of the structure shown in Figure 4;
  • Figure 7A and 7B provide SIMS data from as-grown and Si0 2 encapsulated, annealed samples of the structure shown in Figure 4;
  • Figures 8A - 8E depict the steps which may be used to manufacture a HBT device having reduced base-collector capacitance
  • Figures 9A - 9E depict the steps which may be used to manufacture an ultra-low power, enhancement mode HEMT device with a reduced charge cap over the device channel.
  • the invention is first described below with reference to the manufacture of a HEMT device in which an etch step is eliminated.
  • the present invention may be used during the manufacture of other devices, including, for example, PHEMT, MESFET and/or HBT devices, and to gain this and/or other advantages, such as layer charge reduction.
  • Other applications for the present invention are discussed after presenting certain experimental results which have been obtained.
  • a HEMT device made in accordance with the present invention starts out with a layered structure such as that shown in Figure 1A. Indeed, the process steps described with reference to Figures 1A - IC, may be utilized to arrive at the structure shown in Figure IC. Thereafter, instead of subjecting the contact layer to gate etch, which exposes the Aluminum bearing Schottky layer, a layer of Si0 2 is deposited over the structure shown in Figure IC so as to arrive at the structure shown in Figure 2A.
  • a layer of photoresist is then deposited on the layer of Si0 2 and the layer of photoresist is patterned using known photolithographic techniques, to leave an island of photoresist 31, as shown in Figure 2B.
  • the Si0 2 is then etched using the patterned layer (or island) of photoresist 31 as a mask.
  • the patterned layer would typically include many islands 31 i.e, one for each device being manufactured.
  • the masked portions of the layer of photoresist 31 are then removed to expose islands of Si0 2 disposed over a region in contact layer 14, as can be seen in Figure 2C.
  • contact layer 14 preferably comprises a layer of Gallium Arsenide doped with Tin (Sn) .
  • the structure shown in Figure 2C is then subjected to an anneal. It has been discovered that the SiO z tends to leach the Sn dopant atoms out of the contact layer 14 during an anneal. This tends to reduce the resistivity of the contact layer in the region 32 thereof immediately below the patterned SiO z 30 (see Fig. 2D), which basically has the same effect as etching the contact layer 14 (which is a standard procedure for removing the effective charge in the channel or gate area) .
  • This anneal occurs at a relatively low temperature (approximately 600°C) and the anneal time is relatively short (approximately 10 minutes or less) .
  • the remaining portion of the Si0 2 layer 30 is then preferably removed as shown in Figure 2E to produce a contact layer 14 which continues to cover the Aluminum containing Schottky layer 13 fully, but the contact layer 14 has an area 32 of reduced conductivity below region 20 which will become the gate area.
  • the contact layer 14 will be etched in a manner analogous to that discussed with reference to Figure IG (the main difference being that the contact layer 14 is being etched as opposed to the Schottky layer 13) .
  • the structure shown in Figure 3A will be arrived at after adding a gate 23.
  • the contact layer 14 need not be physically etched and the device will assume the structure shown in Figure 3B af er a gate 23 has been added.
  • using the patterned Si0 2 layer 30 to leach the Sn dopant from the underlying contact layer 14 permits an etch step to be eliminated and (ii) allows the contact layer to remain in place over the Schottky layer 13 thereby protecting Al, which is likely to exist in that layer, from the atmosphere.
  • Si0 2 to leach the Sn from the contact layer 14 might be referred to as an "etchless" etch when used in this fashion.
  • the Si0 2 layer after being used to leach the Sn dopant from the underlying semiconductor layer may be removed, as described above, or some practicing the present invention may prefer to retain at least a portion of the Si02 layer in place in the resulting semiconductor device.
  • the retained Si02 could be used, for example, as a passivation layer or insulating layer in the device being manufactured.
  • Tin (Sn) was used as the dopant in the contact layer 14.
  • the layers are defined with the same reference numbers as used in the preceding figures. However the layers are shown in greater detail in that some layers have spacer layers between them or are themselves made up of multiple layers.
  • Figure 4 shows the semiconductor materials (S) used and the dopants (D) used, if any. Undoped layers are marked “ud” .
  • the semiconductor structure shown by Figure 4 was cleaved into several test samples: (i) with Si0 2 deposition, (ii) with SiN deposition, and (iii) as grown for material characterization.
  • the layer of Si0 2 30 ( Figure 2A) was 1000 A thick for the Si0 2 encapsulated samples.
  • the samples of the semiconductor structure with Si0 2 , SiN, and no dielectric encapsulation were put through a metal organic vapor plasma etch (MOVPE) regrowth cycle (i.e. with no regrowth, but simply an anneal step which is preferably carried out without breaking vacuum) .
  • MOVPE metal organic vapor plasma etch
  • anneal In one regrowth cycle (anneal), the samples were left exposed and in a second cycle a proximity cap was used by covering the samples with a GaAs wafer. After the anneals. Hall, photoluminescence (PL) , X-ray, and SIMS tests were performed on the samples . Hall results are set forth in Table I for the various samples. The Hall data shows that the resistivity p of the semiconductor of the Si0 2 encapsulated samples increases greatly while the samples encapsulated with SiN or having no dielectric show very little change. The Hall data shows that the reason for the increased resistivity is a significant decrease in free charge n s . The increase in mobility ⁇ demonstrates that the decrease in free charge comes from the contact layer 14 and not the channel layer 12.
  • the Hall measurement measures total sample conductivity, and using that determines the total free charge and weighted average mobility. For the samples, there was conductivity in both the contact layer 14 and the channel layer 12.
  • the contact layer 14 has low mobility, due to Sn impurity atoms that scatter electrons, and the channel layer 12 has high mobility, due to no impurities and the addition of In.
  • the conductivity for each layer is proportional to the mobility*free charge product for that layer. So, if the charge in the contact layer (low mobility) decreases, its weighted contribution to the mobility decreases and the measured Hall mobility increases . Thus the charge depletion/removal must be occurring in the contact layer.
  • other aspects of the involved processing such as exposure to the BOE etch used to remove the dielectrics after anneals
  • the room temperature PL data are shown in Figure 5 for the as- grown sample and a Si0 2 encapsulated sample after anneal.
  • the peak wavelength and the overall lines shape are nearly identical.
  • the PL results verify that no intermixing associated with the InGaAs channel layer has occurred, and that the channel charge and charge distribution remains unchanged.
  • Figure 6 shows X-ray data, again for the as-grown and Si0 2 encapsulated and annealed samples.
  • the X-ray lineshapes are also nearly identical, and verify that the measured Al composition of the Schottky layer 13 is the same for both samples.
  • the X-ray data provide more evidence that no intermixing is occurring in these samples.
  • Figures 7A and 7B provide a comparison of SIMS data for an as- grown sample and a sample that was Si0 2 encapsulated and subsequently annealed. In particular, attention should be paid to the Sn depth profile.
  • the SIMS data show that, for the Si0 2 encapsulated sample, the Sn has been drawn to the Si0 2 /epilayer interface, where based on the Hall data it is inactive as a donor atom. In all likelihood, group III vacancies are "injected" at the Si0 2 /epilayer interface to promote and foster Sn exchange and diffusion. The large size of the Sn atom and relatively weak bonds with the group V atoms probably make the Sn atoms more susceptible to exchange and diffusion interactions. The SIMS data also show that there is no observable difference in the Al and In profiles which gives further evidence that there is no intermixing occurring in the samples.
  • the dopant is a group IV semiconductor having a larger size than the normal constituents of the group III-V semiconductors.
  • the group TV dopant should have an atomic number greater than the atomic numbers of either group III or group V semiconductors.
  • Figure IG shows a PHEMT structure with a typical gate and channel recess etch.
  • Figures 3A and 3B shows a PHEMT structure that is made by the etchless channel recess "etch" process which utilizes the aforementioned selective encapsulation with Si0 2 and subsequent annealing.
  • the technique can be used to manufacture a Heterojunction Bipolar Transistor (HBT) device having a reduced base-collector capacitance (C ⁇ ) .
  • the C ⁇ is reduced by selectively removing electric charge underneath the device's external base contact by previously annealing Si0 2 capped Sn-doped layers to deplete or remove Sn as a donor.
  • Figure 8A depicts a semi-insulating InP substrate 100 upon which an InP layer 110, which will act as a subcollector, has been grown.
  • the layer 110 is preferably about 4000 A thick and is doped with Sn at a concentration preferably in the range of about 1*10 19 to about 3*10 19 .
  • Si0 2 is deposited and patterned as shown in Figure 8B to form Si0 2 layer 120.
  • a subsequent anneal is performed, preferably at about 600°C for approximately 15 minutes, which leaches Sn atoms out of the InP layer 110 underlying Si0 2 layer 120. Sn atoms are not leached out of an adjacent location 111 in InP layer 110 which will become the subcollector. While most of layer 110 is shown as having been leached in Figure 8C, the particular area from which the Sn atoms should be leached is the region of layer 110 underneath the yet to be formed base contact 145 (see Figure 8E) . Since Sn is not leached from those portions of the InP layer 110 which are not covered by Si0 2 layer 120, in the region which will serve as the subcollector 111, the carrier concentration provided by the Sn doping remains undiminished.
  • InP layer 110 the remainder of the HBT device is grown using conventional HBT manufacturing technology.
  • a collector 130, base 140 and emitter 150 layers are grown as shown in Figure 8D and patterned as shown in Figure 8E.
  • Metal contacts are formed for the collector contact 115, a base contact 145 and an emitter contact 155.
  • group III-V semiconductors than InP may be used for layer 110 by some skilled in the art to form the subcollector.
  • GalnAs or another group III-V semiconductor may be substituted for InP in some applications.
  • Sn is the preferred dopant due to its relatively large size, some may choose to use other dopants.
  • Figure 9A shows several layers grown on a substrate 200, including a device channel layer 210, a GalnAs cap layer 220 which is doped with Sn atoms and an Si0 2 layer 230, the layers having been patterned to define the desired gate dimension and then etched down and into the channel layer 210 to yield the structure shown in Figure 9A.
  • source and drain ohmic contacts 240 are selectively regrown as shown in Figure 9B.
  • the anneal at preferably about 600°C, during the regrowth cycle also leaches Sn atoms out of the GalnAs cap 220 thereby reducing its charge (and hence its conductivity) and thereby setting the threshold voltage of the HEMT device being manufactured.
  • the reduction of charge in GalnAs cap 220 is represented by the X's depicted in the GalnAs cap 220 of Figures 9B - 9E.
  • the Si0 2 layer 230 which actually appears more as a column since it is now higher than it is wide, is reduced in size by a blanket etch, preferably a Reactive Ion Etch (RIE) , so that it is then spaced from the source and drain contacts 240 as can be seen in Figure 9C.
  • Polymide 250 is then spun and the resulting structure is planarized by etching the polymide back, leaving a tip 235 of the column 230 of Si0 2 exposed.
  • the Si0 2 230 is removed to define a gate contact via 256 and the polymide is patterned to define vias 255 for source and drain contacts, as shown in Figure 9D.
  • a metal gate contact 260 is formed in the gate via 256 and metal source and drain contacts 261 are formed in the vias 255.
  • the removal of the Si0 2 column yields a self-aligned via 256 which is easily metalized to form the gate contact 260, which of course is also self-aligned.
  • the lithography needed to form the source and drain vias 255 is not particularly critical and the gate, source and drains contacts 260, 261 can all be conveniently formed at the same time since no alloying is needed for the ohmic contacts formed thereby.
  • the semiconductor may be InP, InGaAs, GaAs or some other group III-V semiconductor, while the dopant should have a relatively larger-sized atom. Sn is the preferred dopant.

Abstract

Disclosed is a method of reducing the conductivity/charge of a layer of group III-V semiconductor doped with Sn. The method includes the steps of: forming a region of SiO2 (30) on the semiconductor layer (14), annealing at least the semiconductor layer and the region of SiO2 at a temperature sufficiently high to cause atoms of the Sn dopant to diffuse from the semiconductor layer into the region of SiO2; thereby forming a region (32) with reduced Sn concentration and removing the region of SiO2 after the annealing step is performed. The method can be used, for example, during the manufacture of HEMT, PHEMT,MESFET, and HBT devices.

Description

CONDUCTIVITY REDUCTION METHOD FOR DOPED COMPOUND SEMICONDUCTORS
Field of the Invention
The present invention relates to a method of reducing the conductivity (or charge) of a doped semiconductor. The method may be conveniently used in a number of applications. For example, the method may be used to effectively perform the channel or gate recess etches commonly used in Metal Semiconductor Field Effect Transistor (MESFET) devices and High Electron Mobility Transistor (HEMT) devices, including Pseudomorphic High Electron Mobility transistor (PHEMT) devices. The method may also be used to reduce the extrinsic base-collector capacitance in a semiconductor device As such the present invention also relates to devices manufactured according to this method.
Description of the Prior Art
A prior art HEMT device will now be described with reference to Figures 1A-1G. Figure 1A depicts a substrate 10 having a buffer layer 11 disposed thereon which in turn has a channel layer 12 disposed thereon. On the channel layer is disposed a Schottky layer 13 and a contact layer 14 is formed on top of the Schottky layer. Each of these layers are conventional epitaxial layers formed by methods known in the prior art. Additionally, these layers are generally formed of semiconductor materials from groups III and V of the Periodic Table of Elements and their alloys.
Semiconductor materials such as Gallium Arsenide (GaAs) , Indium Phosphide (InP) , and Aluminum Gallium Arsenide (AlGaAs) , Indium Gallium Arsenide (InGaAs) , Indium Aluminum Arsenide (InAlAs) are typically used in such devices. Since the alloys which are used and their level of dopings are known in the prior art, they are not described further here.
In order to form a field effect device in the structure shown in Figure 1A, metal source and drain contacts 15 and 16 are formed on contact layer 14 (see Figure 1C) . This can be done by patterning a layer of photoresist 17, covering the patterned photoresist with metal 18 and, thereafter, lifting off the photoresist and the layer of metal disposed on top thereof in order to arrive at the structure shown in Figure 1C. Those skilled in the art will realize, of course, that there are other ways of forming the source contact 15 and drain contact 16 shown in Figure 1C.
Thereafter, another layer of photoresist 19 is applied and patterned as shown in Figure ID to expose an area 20 between the source contact 15 and the drain contact 16. The device is then etched with an etchant suitable to remove the exposed contact layer in area 20. This etch is called a gate recess etch. After the photoresist layer 19 is removed the structure shown in Figure IE results.
Sometimes HEMT, PHEMT and MESFET devices are subjected to a second etch. If a second etch is used, the structure of Figure IE is covered with a photoresist which is patterned to form a region in the exposed portion 20 of Schottky layer 13 as shown in Figure IF. The Schottky layer is subjected to a controlled etch which is called a channel recess etch. This particular etch is one of the most critical steps in the manufacture of prior art HEMT and PHEMT devices. The most common process used for the gate recess etch previously described with reference to Figures ID and IE and the channel recess etch previously described with reference to Figure IF is typically a wet chemical etch which removes device material to the desired depth in the gate area of the device. Typically, the channel etch is not monitored by depth, but rather by measuring the saturation current flowing from the source contact 15 to the drain contact 16 of exemplary HEMT devices being manufactured in a wafer. In manufacturing these devices, many devices are normally manufactured at the same time on a common semiconductor wafer and the saturation current is measured only for a few exemplary devices being formed on the wafer. Presumably, the devices which are measured are representative of all the devices being manufactured on the wafer. Of course, the exemplary devices may or may not be truly representative of all of the devices. In any event, as a channel recess etch proceeds, etching away the conductive material, the conductivity in the channel decreases and therefore the saturation current decreases. Typically, the measurement of the saturation current and the etch processing do not occur at the same time and therefore usually several cycles of etch processing and measuring are alternatingly utilized until the desired saturation current level is reached. After the channel recess etch has been completed, a gate structure 23 is formed and the patterned photoresist 22 is removed. If the
Schottky layer 13 includes Aluminum in the alloy thereof, which is commonly the case, a passivation layer 24 is conventionally applied. It is undesirable to expose Aluminum containing compounds to atmosphere since Aluminum is very reactive and subject to oxidation. The passivation layer 24 helps protect against such oxidation.
It is an object of the present invention to provide a method of manufacturing HEMT-type devices having desired saturation current levels but without exposing Aluminum containing compounds of the Schottky layer 13 to atmosphere.
It is another object of the present invention to provide a method of manufacturing HEMT-type devices having desired saturation current levels but without requiring use of a passivation layer to cover Aluminum containing compounds on the gate area.
Brief Description of the Invention
In one aspect the present invention provides a method of reducing the conductivity of a layer of a group III-V semiconductor doped with a group IV semiconductor, the group III, IV and V semiconductors each having an atomic number with the atomic number of the group IV semiconductor being larger than the atomic numbers of each of the group III and group V semiconductors. The method comprising the steps of forming a region of Si02 on the group III-V semiconductor layer; and annealing at least the semiconductor layer and the region of Si02 at a temperature sufficiently high to cause atoms of the group IV semiconductor to leach from the semiconductor layer into the region of Si02 - The region of SiOz is optionally removed after the annealing step is performed.
In another aspect, the present invention provides a method of forming a gate region of a semiconductor device such as a PHEMT or a HEMT or a MESFET device. The method includes the steps of (i) forming an layer of semiconductor layer doped with Sn; (ii) forming an region of Si02 on the semiconductor layer, the region of Si02 corresponding to the gate region to be formed; (iii) annealing at least the semiconductor layer and the region of Si02 at a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of Si02 and to thereby form a region in said semiconductor layer having a reduced concentration of Sn dopant, the annealing step occurring at a temperature sufficiently low and for a period of time sufficiently short to inhibit significant intermixing between the region of Si02 and the semiconductor layer; (iv) optionally removing the region of Si02 after the annealing step is performed; and (v) forming a gate electrode on said semiconductor layer.
In yet another aspect the present invention provides a method of reducing base-collector capacitance of a semiconductor device having layer of a group III-v semiconductor which is doped with a group IV semiconductor. The method includes the steps of: forming a region of Si02 on the group III-V semiconductor layer; annealing at least the semiconductor layer and the region of Si02 at a temperature sufficiently high to cause atoms of the group IV semiconductor to leach from at least a region of the group III-V semiconductor layer into the region of Si02; removing the region of
Si02 after the annealing step is performed; and forming a semiconductor layer defining a base region on the region of the group III-V semiconductor layer from which the IV semiconductor was leached.
Brief Description of the Drawings
Figures 1A through 1G depict the steps in manufacturing a prior art HEMT device; and
Figures 2A-2E depict the steps which may be used to define the channel (i.e., control the saturation current between the source and drain) without the need to expose any semiconductor compound which includes Aluminum to atmosphere and without the need to employ a passivation layer;
Figure 3A shows the resulting structure after a partial physical etch of the contact layer and a gate has been added; Figure 3B shows the resulting structure a gate has been added (without physically etching the contact layer) ;
Figure 4 depicts a semiconductor structure used for testing purposes ,-
Figure 5 shows room temperature photoluminescence data from as- grown and Si02 encapsulated, annealed samples of the structure shown in Figure 4;
Figure 6 shows X-ray data from as-grown and Si02 encapsulated, annealed samples of the structure shown in Figure 4;
Figure 7A and 7B provide SIMS data from as-grown and Si02 encapsulated, annealed samples of the structure shown in Figure 4;
Figures 8A - 8E depict the steps which may be used to manufacture a HBT device having reduced base-collector capacitance; and
Figures 9A - 9E depict the steps which may be used to manufacture an ultra-low power, enhancement mode HEMT device with a reduced charge cap over the device channel.
Detailed Description of the Invention
The invention is first described below with reference to the manufacture of a HEMT device in which an etch step is eliminated. However, the present invention may be used during the manufacture of other devices, including, for example, PHEMT, MESFET and/or HBT devices, and to gain this and/or other advantages, such as layer charge reduction. Other applications for the present invention are discussed after presenting certain experimental results which have been obtained.
An Improved HEMT device
A HEMT device made in accordance with the present invention starts out with a layered structure such as that shown in Figure 1A. Indeed, the process steps described with reference to Figures 1A - IC, may be utilized to arrive at the structure shown in Figure IC. Thereafter, instead of subjecting the contact layer to gate etch, which exposes the Aluminum bearing Schottky layer, a layer of Si02 is deposited over the structure shown in Figure IC so as to arrive at the structure shown in Figure 2A.
A layer of photoresist is then deposited on the layer of Si02 and the layer of photoresist is patterned using known photolithographic techniques, to leave an island of photoresist 31, as shown in Figure 2B. The Si02 is then etched using the patterned layer (or island) of photoresist 31 as a mask. The patterned layer would typically include many islands 31 i.e, one for each device being manufactured. The masked portions of the layer of photoresist 31 are then removed to expose islands of Si02 disposed over a region in contact layer 14, as can be seen in Figure 2C. In this embodiment, contact layer 14 preferably comprises a layer of Gallium Arsenide doped with Tin (Sn) .
The structure shown in Figure 2C is then subjected to an anneal. It has been discovered that the SiOz tends to leach the Sn dopant atoms out of the contact layer 14 during an anneal. This tends to reduce the resistivity of the contact layer in the region 32 thereof immediately below the patterned SiOz 30 (see Fig. 2D), which basically has the same effect as etching the contact layer 14 (which is a standard procedure for removing the effective charge in the channel or gate area) . This anneal occurs at a relatively low temperature (approximately 600°C) and the anneal time is relatively short (approximately 10 minutes or less) .
The remaining portion of the Si02 layer 30 is then preferably removed as shown in Figure 2E to produce a contact layer 14 which continues to cover the Aluminum containing Schottky layer 13 fully, but the contact layer 14 has an area 32 of reduced conductivity below region 20 which will become the gate area.
If the MESFET, HEMT or PHEMT device is to be of a type similar to the doubly etched device discussed with reference to Figures 1A - IG, then the contact layer 14 will be etched in a manner analogous to that discussed with reference to Figure IG (the main difference being that the contact layer 14 is being etched as opposed to the Schottky layer 13) . The structure shown in Figure 3A will be arrived at after adding a gate 23.
If the MESFET, HEMT or PHEMT device is analogous to a single etch device, then the contact layer 14 need not be physically etched and the device will assume the structure shown in Figure 3B af er a gate 23 has been added.
In any case, using the patterned Si02 layer 30 to leach the Sn dopant from the underlying contact layer 14 (i) permits an etch step to be eliminated and (ii) allows the contact layer to remain in place over the Schottky layer 13 thereby protecting Al, which is likely to exist in that layer, from the atmosphere. Thus using Si02 to leach the Sn from the contact layer 14 might be referred to as an "etchless" etch when used in this fashion.
The Si02 layer, after being used to leach the Sn dopant from the underlying semiconductor layer may be removed, as described above, or some practicing the present invention may prefer to retain at least a portion of the Si02 layer in place in the resulting semiconductor device. The retained Si02 could be used, for example, as a passivation layer or insulating layer in the device being manufactured.
Experimental Results
A semiconductor structure was experimentally grown, as is shown in Figure 4. Tin (Sn) was used as the dopant in the contact layer 14. The layers are defined with the same reference numbers as used in the preceding figures. However the layers are shown in greater detail in that some layers have spacer layers between them or are themselves made up of multiple layers. Figure 4 shows the semiconductor materials (S) used and the dopants (D) used, if any. Undoped layers are marked "ud" .
After growth the semiconductor structure shown by Figure 4 was cleaved into several test samples: (i) with Si02 deposition, (ii) with SiN deposition, and (iii) as grown for material characterization. The layer of Si02 30 (Figure 2A) was 1000 A thick for the Si02 encapsulated samples. The samples of the semiconductor structure with Si02, SiN, and no dielectric encapsulation were put through a metal organic vapor plasma etch (MOVPE) regrowth cycle (i.e. with no regrowth, but simply an anneal step which is preferably carried out without breaking vacuum) . The cycle was 10 minutes at 600°C. In one regrowth cycle (anneal), the samples were left exposed and in a second cycle a proximity cap was used by covering the samples with a GaAs wafer. After the anneals. Hall, photoluminescence (PL) , X-ray, and SIMS tests were performed on the samples . Hall results are set forth in Table I for the various samples. The Hall data shows that the resistivity p of the semiconductor of the Si02 encapsulated samples increases greatly while the samples encapsulated with SiN or having no dielectric show very little change. The Hall data shows that the reason for the increased resistivity is a significant decrease in free charge ns. The increase in mobility μ demonstrates that the decrease in free charge comes from the contact layer 14 and not the channel layer 12. The Hall measurement measures total sample conductivity, and using that determines the total free charge and weighted average mobility. For the samples, there was conductivity in both the contact layer 14 and the channel layer 12. The contact layer 14 has low mobility, due to Sn impurity atoms that scatter electrons, and the channel layer 12 has high mobility, due to no impurities and the addition of In. The conductivity for each layer is proportional to the mobility*free charge product for that layer. So, if the charge in the contact layer (low mobility) decreases, its weighted contribution to the mobility decreases and the measured Hall mobility increases . Thus the charge depletion/removal must be occurring in the contact layer. In addition to the encapsulation and anneal experiments, it was determined that other aspects of the involved processing (such as exposure to the BOE etch used to remove the dielectrics after anneals) had negligible effect on the Hall data for the samples.
Table I - Hall Data for the experiment:
Figure imgf000012_0001
The room temperature PL data are shown in Figure 5 for the as- grown sample and a Si02 encapsulated sample after anneal. The peak wavelength and the overall lines shape are nearly identical. The PL results verify that no intermixing associated with the InGaAs channel layer has occurred, and that the channel charge and charge distribution remains unchanged. These data support the Hall findings which indicate the charge loss occurs in the contact layer.
Figure 6 shows X-ray data, again for the as-grown and Si02 encapsulated and annealed samples. The X-ray lineshapes are also nearly identical, and verify that the measured Al composition of the Schottky layer 13 is the same for both samples. The X-ray data provide more evidence that no intermixing is occurring in these samples. Figures 7A and 7B provide a comparison of SIMS data for an as- grown sample and a sample that was Si02 encapsulated and subsequently annealed. In particular, attention should be paid to the Sn depth profile. The SIMS data show that, for the Si02 encapsulated sample, the Sn has been drawn to the Si02/epilayer interface, where based on the Hall data it is inactive as a donor atom. In all likelihood, group III vacancies are "injected" at the Si02/epilayer interface to promote and foster Sn exchange and diffusion. The large size of the Sn atom and relatively weak bonds with the group V atoms probably make the Sn atoms more susceptible to exchange and diffusion interactions. The SIMS data also show that there is no observable difference in the Al and In profiles which gives further evidence that there is no intermixing occurring in the samples.
It is believed that this technique may well work with other group III-V semiconductors where the dopant is a group IV semiconductor having a larger size than the normal constituents of the group III-V semiconductors. As such, the group TV dopant should have an atomic number greater than the atomic numbers of either group III or group V semiconductors.
A brief discussion concerning intermixing at this point is very useful. Impurity induced intermixing and impurity free intermixing using Si02 encapsulant are well known in the prior art. The present invention is fundamentally different. The primary difference stems from the fact that the aim of intermixing, as performed by other researchers, is to selectively intermix different epilayers by displacing constituent atoms using Si02 encapsulation and subsequent annealing. As such, the anneal temperatures are necessarily very high (typically the effects become noticeable at 850°C) and anneal times can be very long (more than 25 hours) . In contrast, the present invention alters the Fermi potential without intentionally causing intermixing or other possibly deleterious effects on the lattice. As such, the anneal temperatures are comparatively quite' low (approximately 600°C) and anneal times are comparatively quite short (approximately 10 min or less) .
Use of the "etchless" etch technique in making other semicon uri-nr devices
This technique performs the function of a gate recess etch in HEMTs and/or PHEMTs and/or MESFETs . Figure IG shows a PHEMT structure with a typical gate and channel recess etch. As mentioned above, there are several drawbacks to the standard technique for recess etching, including non-uniformity, non- planarity, and exposure of Al containing compounds to atmosphere. Figures 3A and 3B shows a PHEMT structure that is made by the etchless channel recess "etch" process which utilizes the aforementioned selective encapsulation with Si02 and subsequent annealing. As Figure 3B shows, the process is planar or, if a double "etch" is utilized and the structure of Figure 3A is obtained, then the process is very close to being planar. In either case the process does not expose the AlGaAs Schottky layer to air, which allows the dielectric passivation step used in the prior art to be eliminated.
Other applications for the described technique to reduce or control the charge of a semiconductor layer
The technique can be used to manufacture a Heterojunction Bipolar Transistor (HBT) device having a reduced base-collector capacitance (C^) . The C^ is reduced by selectively removing electric charge underneath the device's external base contact by previously annealing Si02 capped Sn-doped layers to deplete or remove Sn as a donor. Figure 8A depicts a semi-insulating InP substrate 100 upon which an InP layer 110, which will act as a subcollector, has been grown. The layer 110 is preferably about 4000 A thick and is doped with Sn at a concentration preferably in the range of about 1*1019 to about 3*1019. Then Si02 is deposited and patterned as shown in Figure 8B to form Si02 layer 120. A subsequent anneal is performed, preferably at about 600°C for approximately 15 minutes, which leaches Sn atoms out of the InP layer 110 underlying Si02 layer 120. Sn atoms are not leached out of an adjacent location 111 in InP layer 110 which will become the subcollector. While most of layer 110 is shown as having been leached in Figure 8C, the particular area from which the Sn atoms should be leached is the region of layer 110 underneath the yet to be formed base contact 145 (see Figure 8E) . Since Sn is not leached from those portions of the InP layer 110 which are not covered by Si02 layer 120, in the region which will serve as the subcollector 111, the carrier concentration provided by the Sn doping remains undiminished.
After removing the Sn atoms from the Si02-covered portions of the
InP layer 110, the remainder of the HBT device is grown using conventional HBT manufacturing technology. Thus a collector 130, base 140 and emitter 150 layers are grown as shown in Figure 8D and patterned as shown in Figure 8E. Metal contacts are formed for the collector contact 115, a base contact 145 and an emitter contact 155.
Other group III-V semiconductors than InP may be used for layer 110 by some skilled in the art to form the subcollector. For example, GalnAs or another group III-V semiconductor may be substituted for InP in some applications. And while Sn is the preferred dopant due to its relatively large size, some may choose to use other dopants.
The described technique can also be used in the manufacture of ultra-low power, enhancement mode HEMT devices. Figure 9A shows several layers grown on a substrate 200, including a device channel layer 210, a GalnAs cap layer 220 which is doped with Sn atoms and an Si02 layer 230, the layers having been patterned to define the desired gate dimension and then etched down and into the channel layer 210 to yield the structure shown in Figure 9A.
Using the remaining Si0 as a self-aligning mask, source and drain ohmic contacts 240 are selectively regrown as shown in Figure 9B. Conveniently, the anneal, at preferably about 600°C, during the regrowth cycle also leaches Sn atoms out of the GalnAs cap 220 thereby reducing its charge (and hence its conductivity) and thereby setting the threshold voltage of the HEMT device being manufactured. The reduction of charge in GalnAs cap 220 is represented by the X's depicted in the GalnAs cap 220 of Figures 9B - 9E.
The Si02 layer 230, which actually appears more as a column since it is now higher than it is wide, is reduced in size by a blanket etch, preferably a Reactive Ion Etch (RIE) , so that it is then spaced from the source and drain contacts 240 as can be seen in Figure 9C. Polymide 250 is then spun and the resulting structure is planarized by etching the polymide back, leaving a tip 235 of the column 230 of Si02 exposed. Next the Si02 230 is removed to define a gate contact via 256 and the polymide is patterned to define vias 255 for source and drain contacts, as shown in Figure 9D. A metal gate contact 260 is formed in the gate via 256 and metal source and drain contacts 261 are formed in the vias 255. The removal of the Si02 column yields a self-aligned via 256 which is easily metalized to form the gate contact 260, which of course is also self-aligned. The lithography needed to form the source and drain vias 255 is not particularly critical and the gate, source and drains contacts 260, 261 can all be conveniently formed at the same time since no alloying is needed for the ohmic contacts formed thereby.
As should now be apparent to a person skilled in the art, there are likely many more applications for which reduction of conductivity/charge in a semiconductor layer using the present invention will prove to be very useful. The semiconductor may be InP, InGaAs, GaAs or some other group III-V semiconductor, while the dopant should have a relatively larger-sized atom. Sn is the preferred dopant.
Having described the invention with respect to a preferred embodiment of the invention, modification will now suggest itself to those skilled in the. As such, the invention is not to be limited to the disclosed embodiments, unless required by the appended claims.

Claims

What is claimed is:
1. A method of reducing the conductivity of a layer of semiconductor doped with Tin (Sn) comprising the steps of:
(a) forming a region of Si02 on said semiconductor layer; and
(b) annealing at least the semiconductor layer and the region of Si02 at a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of Si02.
2. The method of claim 1 wherein the annealing step occurs at a temperature sufficiently low and for a period of time sufficiently short to inhibit significant intermixing between the region of Si02 and the semiconductor layer.
3. The method of claim 1 wherein the region of Si02 is smaller in area than is the semiconductor layer so that after the annealing steps a region is defined in said Si02 layer having a reduced concentration of Sn dopant compared to other portions of said semiconductor layer.
4. The method of claim 3 wherein the annealing step occurs at a temperature of approximately 600°C.
5. The method of claim 4 wherein the anneal time of the annealing step is approximately 10 minutes.
6. The method of claim 1 wherein the semiconductor layer is a selected one of Indium Phosphide (InP) , Gallium Arsenide (GaAs) and Indium Gallium Arsenide (InGaAs) .
7. The method of claim 1 wherein the annealing step occurs at a temperature of approximately 600°C.
8. The method of claim 1 further including removing the region of Si02 after the annealing step is performed.
9. The method of claim 7 wherein the anneal time of the annealing step is approximately 10 minutes.
10. A method of reducing the conductivity of a layer of a group III-V semiconductor doped with a group IV semiconductor, the group III, IV and V semiconductors each having an atomic number with the atomic number of the group IV semiconductor being larger than the atomic numbers of each of the group III and group V semiconductors, said method comprising the steps of:
(a) forming a region of Si02 on said group III-V semiconductor layer; and
(b) annealing at least the semiconductor layer and the region of SiOz at a temperature sufficiently high to cause atoms of the group IV semiconductor to leach from the semiconductor layer into the region of Si02.
11. The method of claim 10 further including removing the region of Si02 after the annealing step is performed.
12. The method of claim 11 wherein the group III-V semiconductor is selected from semiconductor materials including Indium Phosphide (InP), Gallium Arsenide (GaAs) and Indium Gallium Arsenide (InGaAs) and the group IV semiconductor is Tin (Sn) .
13.. The method of claim 10 wherein the group III-V semiconductor is selected from semiconductor materials including Indium Phosphide (InP) , Gallium Arsenide (GaAs) and Indium Gallium Arsenide (InGaAs) and the group IV semiconductor is Tin (Sn) -
14. A method of forming a gate region of a semiconductor device comprising the steps of:
(a) forming a layer of semiconductor doped with Sn,-
(b) forming a region of Si02 on said semiconductor layer, the region of Si02 corresponding to said gate region;
(c) annealing at least the semiconductor layer and the region of Si02 at a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of Si02 and to thereby form a region in said Si02 layer having a reduced concentration of Sn dopant, the annealing step occurring at a temperature sufficiently low and for a period of time sufficiently short to inhibit significant intermixing between the region of Si02 and the semiconductor layer;
(d) removing the region of Si02 after the annealing step is performed; and
(e) forming a gate electrode on said semiconductor layer.
15. The method of claim 14 wherein the annealing step occurs at a temperature of approximately 600°C.
16. The method of claim 15 wherein the anneal time of the annealing step is approximately 10 minutes.
17. The method of claim 14 further including the step of etching a channel in the region in said Si02 layer having the reduced concentration of Sn dopant.
18. A method of reducing base-collector capacitance of a semiconductor device having a layer of a group III-V semiconductor which is doped with a group IV semiconductor, said method comprising the steps of: (a) forming a region of SiOz on said group III-V semiconductor layer;
(b) annealing at least the semiconductor layer and the region of Si02 at a temperature sufficiently high to cause atoms of the group IV semiconductor to leach from at least a region of the group III-V semiconductor layer into the region of Si02;
(c) removing the region of Si02 after the annealing step is performed; and
(d) forming semiconductor layers defining a collector region and defining a base region over the region of the group III-V semiconductor layer from which the IV semiconductor was leached.
19. The method of claim 18 wherein the group III-V semiconductor is selected from semiconductor materials including Indium Phosphide (InP) , Gallium Arsenide (GaAs) and Indium Gallium Arsenide (InGaAs) and the group IV semiconductor is Tin (Sn) .
20. A method of making a HEMT device comprising the steps of:
(a) forming a device channel on a substrate;
(b) forming a cap layer of a group III-V semiconductor which is doped with a group IV semiconductor over said device channel; (c) forming a region of Si0 on said group III-V semiconductor cap layer;
(d) annealing the semiconductor cap layer and the region of Si02 formed thereon at a temperature sufficiently high to cause atoms of the group IV semiconductor to leach from at least a region of the group III-V semiconductor cap layer into the region of Si02;
(e) forming self-aligned, regrowth contacts adjacent said semiconductor cap layer and adjacent the region of Si02;
(f) partially etching the region of Si02 after the regrowth contacts are formed;
(g) forming and patterning an insulating layer over the regrowth contacts and over exposed portions of the group III-V semiconductor cap layer;
(h) removing the partially etched region of Si02 after forming the insulating layer; and
(i) forming metal contacts for the group III-V semiconductor cap layer and for the regrowth contacts.
21. The method of claim 20 wherein the group III-V semiconductor is Indium Phosphide (InP) or Indium Gallium Arsenide (InGaAs) or Gallium Arsenide (GaAs) and the group IV semiconductor is Tin (Sn) .
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