WO2001006692A3 - Integrated ethernet switch - Google Patents

Integrated ethernet switch Download PDF

Info

Publication number
WO2001006692A3
WO2001006692A3 PCT/US2000/008637 US0008637W WO0106692A3 WO 2001006692 A3 WO2001006692 A3 WO 2001006692A3 US 0008637 W US0008637 W US 0008637W WO 0106692 A3 WO0106692 A3 WO 0106692A3
Authority
WO
WIPO (PCT)
Prior art keywords
switch
phy
communication protocol
mac
drives
Prior art date
Application number
PCT/US2000/008637
Other languages
French (fr)
Other versions
WO2001006692A2 (en
Inventor
Yi-Hsien Hao
Scott Mcdaniel
John K Lenell
Andrew M Naylor
Original Assignee
Broadcom Corp
Hao Yi Hsien
Scott Mcdaniel
John K Lenell
Andrew M Naylor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp, Hao Yi Hsien, Scott Mcdaniel, John K Lenell, Andrew M Naylor filed Critical Broadcom Corp
Priority to EP00921565A priority Critical patent/EP1166505B1/en
Priority to DE60027712T priority patent/DE60027712T2/en
Priority to AU41864/00A priority patent/AU4186400A/en
Publication of WO2001006692A2 publication Critical patent/WO2001006692A2/en
Publication of WO2001006692A3 publication Critical patent/WO2001006692A3/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/35Switches specially adapted for specific applications
    • H04L49/351Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Packet switching elements characterised by the switching fabric construction
    • H04L49/103Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding in a switch fabric
    • H04L49/253Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254Centralised controller, i.e. arbitration or scheduling
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/45Arrangements for providing or supporting expansion

Abstract

A network switch having PHY integrated with the switch. The switch also integrates MAC with PHY. The PHY, MAC, and switch are integrated onto a single VLSI component. The network switch implements an IEEE Standard 802.3 communication protocol which may include autonegotiation, flow control, and duplexing. The communication protocol can include a 10Base-T communication protocol and a 100Base-T communication protocol. The switch includes an Address Resolution Table using associative memory. A free buffer pool, Transmit Descriptor Table, a Packet Storage Table, and combinations thereof also may reside with the Address Resolution Table in a shared memory block. Each PHY/MAC pair in the switch employs only a single Link Partner Capability Register. The switch uses a common system clock which is driven by a single clock source. The PLL that drives the PHY also drives the switch functions through a first clock generator. A second clock generator is used to drive devices external to the switch, such as memory.
PCT/US2000/008637 1999-03-31 2000-03-31 Integrated ethernet switch WO2001006692A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00921565A EP1166505B1 (en) 1999-03-31 2000-03-31 Integrated ethernet switch
DE60027712T DE60027712T2 (en) 1999-03-31 2000-03-31 INTEGRATED ETHERNET AGENCY
AU41864/00A AU4186400A (en) 1999-03-31 2000-05-31 Integrated ethernet switch

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12714799P 1999-03-31 1999-03-31
US60/127,147 1999-03-31
US09/492,265 2000-01-27
US09/492,265 US7899052B1 (en) 1999-01-27 2000-01-27 Memory structure for resolving addresses in a packet-based network switch

Publications (2)

Publication Number Publication Date
WO2001006692A2 WO2001006692A2 (en) 2001-01-25
WO2001006692A3 true WO2001006692A3 (en) 2001-06-07

Family

ID=26825382

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2000/008677 WO2000059176A2 (en) 1999-03-31 2000-03-31 Apparatus for ethernet phy/mac communication
PCT/US2000/008637 WO2001006692A2 (en) 1999-03-31 2000-03-31 Integrated ethernet switch

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2000/008677 WO2000059176A2 (en) 1999-03-31 2000-03-31 Apparatus for ethernet phy/mac communication

Country Status (6)

Country Link
US (1) US7899052B1 (en)
EP (2) EP1166506B1 (en)
AT (2) ATE313188T1 (en)
AU (2) AU4187100A (en)
DE (2) DE60027712T2 (en)
WO (2) WO2000059176A2 (en)

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Also Published As

Publication number Publication date
WO2000059176A3 (en) 2001-01-04
EP1166505A2 (en) 2002-01-02
WO2000059176A2 (en) 2000-10-05
EP1166506A2 (en) 2002-01-02
EP1166506B1 (en) 2005-12-14
EP1166505B1 (en) 2006-05-03
WO2001006692A2 (en) 2001-01-25
US7899052B1 (en) 2011-03-01
ATE325485T1 (en) 2006-06-15
ATE313188T1 (en) 2005-12-15
DE60024794T2 (en) 2006-09-14
AU4187100A (en) 2000-10-16
DE60027712D1 (en) 2006-06-08
DE60024794D1 (en) 2006-01-19
DE60027712T2 (en) 2007-05-03
AU4186400A (en) 2001-02-05

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