WO2001008159A2 - Method of forming memory capacitor contact openings - Google Patents

Method of forming memory capacitor contact openings Download PDF

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Publication number
WO2001008159A2
WO2001008159A2 PCT/US2000/040472 US0040472W WO0108159A2 WO 2001008159 A2 WO2001008159 A2 WO 2001008159A2 US 0040472 W US0040472 W US 0040472W WO 0108159 A2 WO0108159 A2 WO 0108159A2
Authority
WO
WIPO (PCT)
Prior art keywords
forming
over
insulative material
bit line
conductive
Prior art date
Application number
PCT/US2000/040472
Other languages
French (fr)
Other versions
WO2001008159A3 (en
Inventor
Luan C. Tran
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to DE10084848T priority Critical patent/DE10084848T1/en
Priority to AU73879/00A priority patent/AU7387900A/en
Priority to DE60026860T priority patent/DE60026860T2/en
Priority to JP2001512582A priority patent/JP2003529915A/en
Priority to EP00962009A priority patent/EP1277209B1/en
Publication of WO2001008159A2 publication Critical patent/WO2001008159A2/en
Publication of WO2001008159A3 publication Critical patent/WO2001008159A3/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/24—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
    • H01L21/108—Provision of discrete insulating layers, i.e. non-genetic barrier layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Definitions

  • This invention relates to methods of forming conductive capacitor plugs, to methods of forming capacitor contact openings, and to methods of forming memory arrays.
  • Semiconductor processing involves a number of processing steps in which individual layers are masked and etched to form semiconductor components.
  • Mask alignment is important as even small misalignments can cause device failure.
  • proper alignment is extremely critical to achieve proper fabrication.
  • design rules are more relaxed allowing for a larger margin for alignment errors.
  • One way in which design rules can be relaxed is to provide processing sequences which enable so-called self aligned etches, such as to encapsulated word lines in the fabrication of memory circuitry.
  • there is a goal to reduce or minimize the number of steps in a particular processing flow. Minimizing the processing steps reduces the risk of a processing error affecting the finished device, and reduces cost.
  • This invention arose out of needs associated with improving the manner in which semiconductor memory arrays, and in particular capacitor-over-bit line memory arrays, are fabricated.
  • a conductive capacitor plug is formed to extend from proximate a substrate node location to a location elevationaUy above all conductive material of an adjacent bit line.
  • a capacitor contact opening is etched through a first insulative material received over a bit line and a word line substantially selective relative to a second insulative material covering portions of the bit line and the word line. The opening is etched to a substrate location proximate the word line in a self-aligning manner relative to both the bit line and the word line.
  • capacitor contact openings are formed to elevationaUy below the bit lines after the bit lines are formed.
  • capacitor-over-bit line memory arrays are formed.
  • Fig. 1 is a top plan view of the semiconductor wafer fragment in process in accordance with one embodiment of the invention.
  • Fig. 2 is a view of the Fig. 1 wafer fragment at a different processing step.
  • Fig. 3 is a view which is taken along line 3-3 in Fig. 2.
  • Fig. 4 is a view of the Fig. 3 wafer fragment at a different processing step.
  • Fig. 5 is a view of the Fig. 4 wafer fragment at a different processing step.
  • Fig. 6 is a view of the Fig. 5 wafer fragment at a different processing step.
  • Fig. 7 is a view of the Fig. 6 wafer fragment at a different processing step.
  • Fig. 8 is a view of the Fig. 2 wafer fragment at a different processing step.
  • Fig. 9 is a view which is taken along line 9-9 in Fig. 8.
  • Fig. 10 is a view of the Fig. 9 wafer fragment at a different processing step.
  • Fig. 1 1 is a view of the Fig. 10 wafer fragment at a different processing step.
  • Fig. 12 is a view of the Fig. 11 wafer fragment at a different processing step.
  • Fig. 13 is a view of the Fig. 12 wafer fragment at a different processing step.
  • Fig. 14 is a view which is taken along line 14-14 in Fig. 8 and somewhat reduced in dimension.
  • Fig. 15 is a view of the Fig. 14 wafer fragment at a different processing step.
  • Fig. 16 is a view of the Fig. 15 wafer fragment at a different processing step.
  • Fig. 17 is a view of a semiconductor wafer fragment in process, in accordance with another embodiment of the invention.
  • the Fig. 17 view coincides to processing which can occur after the view depicted in Fig. 12.
  • a semiconductor wafer fragment 20 in process in accordance with one embodiment of the invention includes a semiconductive substrate 22.
  • semiconductive substrate is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
  • substrate refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
  • Substrate 22 includes a plurality of active areas 24 and a plurality of isolation regions 26. Isolation regions 26 can be formed through various techniques including shallow trench isolation.
  • a plurality of conductive lines 28 are formed over substrate 22 and constitute word lines of a memory array which is to be formed.
  • Each of word lines 28 includes a gate oxide layer 30, a conductive polysilicon layer 32, and an overlying silicide layer 34.
  • Insulative coverings are formed over individual word lines 28 and include side wall spacers 36 and an insulative cap 38. The insulative coverings preferably encapsulate the word lines.
  • Exemplary insulative materials include oxide formed through decomposition of TEOS, or nitride/oxynitride materials.
  • Diffusion regions 40 are provided and formed intermediate word lines 28 and define substrate node locations with which electrical communication is desired.
  • the illustrated diffusion regions include lightly doped drain (LDD) regions (not specifically designated).
  • a first layer 42 is formed over substrate 22 and between conductive lines 28 and comprises a first insulative material which is different from the insulative material covering or encapsulating word lines 28.
  • An exemplary material is borophosphosilicate glass (BPSG) which can be subsequently reflowed and planarized as by conventional techniques to provide a generally planar uppermost surface 44.
  • a first masking layer 46 is formed over the substrate and defines a plurality of bit line plug mask openings 48.
  • An exemplary material is photoresist.
  • material of first layer 42 is etched through bit line plug mask openings 48 and individual substrate diffusion regions 40 between selected word lines 28 are preferably exposed. Such etching forms bit plug openings 50 intermediate the selected word lines.
  • conductive material 52 is formed over and in electrical communication with the individual substrate diffusion regions 40 beneath bit plug openings 50 (Fig. 5).
  • An exemplary material is conductively doped polysilicon which can be deposited, and portions subsequently removed, to isolate the conductive material within the bit plug openings and form individual plugs 54.
  • Plugs 54 can be formed by chemical mechanical polishing conductive material 52 or through various etch back techniques.
  • bit lines 56 are formed and in electrical communication with respective individual conductive bit line plugs 54.
  • Bit lines 56 are formed over insulative material 42 and the illustrated word lines 28.
  • Bit lines 56 include a polysilicon layer 58 and a silicide or other conductive layer 60 (i.e., tungsten).
  • An insulative covering 62 is formed over conductive material of the bit lines and can comprise a suitable oxide, such as one formed through decomposition of TEOS, or nitride/oxynitride materials.
  • the various bit line layers are preferably blanket deposited over the substrate and subsequently photomasked and etched to provide the illustrated bit lines (Fig. 8).
  • the bit line plug and the bit line can comprise a common material deposited during the same processing step.
  • layers 52 and 58 could comprise the same material which is deposited thick enough to form both the conductive plug and some or all of bit lines 56.
  • a view is shown which is taken along line 9-9 in Fig. 8 and cuts across three individual bit line plugs 54 and their associated bit lines 56.
  • a layer of insulative material is formed over substrate
  • insulative material 64 include oxide formed through decomposition of TEOS, or nitride/oxynitride materials.
  • the insulative material which is utilized to encapsulate the word lines (Fig. 3) is the same material which is utilized to encapsulate the bit lines. Referring to Fig.
  • a second layer 66 is formed over the word lines and bit lines 56, and preferably comprises the first insulative material which was formed over word lines 28, e.g. BPSG. Such layer is preferably reflowed and planarized.
  • Layers 42, 66 constitute a plurality of separately-formed layers of first insulative material which, in the preferred embodiment, comprise two layers.
  • a second patterned masking layer 68 is formed over second layer 66 and defines a plurality of opening patterns 70 over various substrate diffusion regions 40. Openings 70 are formed on opposite sides of individual word lines between which individual bit line plugs are formed.
  • a preferred alternative to forming individual openings 70 over the illustrated diffusion regions is to form a so-called stripe opening which can be opened up over a plurality of the diffusion regions, where of the stripe opening intersects with the bit line spacers.
  • An exemplary stripe opening is illustrated in Fig. 8 inside dashed line 72 (Fig. 8).
  • capacitor contact openings 74 are etched through first and second layers of insulative material 42, 66 respectively.
  • capacitor contact openings 74 are etched to elevationaUy below bit lines 56, down to proximate individual word lines of the memory array. In a preferred embodiment, the etching exposes individual diffusion regions 40.
  • some portions of second layer 66 remain over the individual bit lines.
  • the above-mentioned stripe opening 72 (Fig. 8) is formed, all of first insulative material 66 over the individual bit lines would ideally be removed.
  • the material which is used to encapsulate both the bit lines and the word lines is selected to comprise the same material, or, a material selective to which layers 42, 66 can be etched. Accordingly, etch chemistries can be selected to etch material of both layers 42, 66 substantially selectively relative to the material encapsulating both the word lines and the bit lines.
  • capacitor contact openings 74 can be formed in a self-aligning manner to be generally self-aligned to both the bit lines and the word lines. Aspects of the invention also include non-capacitor-over-bit line memory array fabrication processes, and selective etching of contact openings which might not be capacitor contact openings.
  • conductive material 76 is formed within individual contact openings 74 and in electrical communication with individual respective diffusion regions 40.
  • An exemplary material is conductively doped polysilicon which can be subsequently etched back or chemical mechanical polished to form individual capacitor plugs 78.
  • conductive material 76 extends from proximate diffusion regions 40 to respective elevations which are at least laterally proximate (including higher) individual conductive portions of the bit lines. In a preferred embodiment, conductive material 76 extends to locations which are elevationaUy higher than any conductive portion of any bit line.
  • Individual conductive capacitor plugs 78 include individual surfaces 80 proximate which each plug terminates. Surfaces 80 are disposed at elevations above conductive portions of the bit lines.
  • an insulative layer 82 e.g. BPSG, is formed over the substrate and subsequently patterned and etched to form individual capacitor containers 84 (Fig. 16).
  • Storage capacitors are then formed by depositing a storage node layer 86, a cell dielectric layer 88, and a cell plate layer 90. Accordingly, such constitutes a portion of a capacitor-over-bit line memory array.
  • the above methods can facilitate formation of memory circuitry over other techniques wherein the capacitor plugs are formed prior to formation of the bit lines. Such other techniques can present alignment problems insofar capacitor container-to-bit line, and capacitor container-to-word line, alignments are concerned.
  • aspects of the present invention can permit the capacitor plugs to be formed to be generally self-aligned to both the word lines and the bit lines, while preserving the mask count necessary to form the subject memory arrays.
  • Other aspects of the present invention can ease alignment constraints imposed on capacitor container alignment by removing requirements that the containers be etched to be self-aligned to other structures including the bit lines.
  • storage capacitors can be formed directly within contact openings 74 (see Fig. 12) such that capacitor plugs 78 (Fig. 13) are not necessary.
  • a layer 66a is formed over the substrate and subsequently patterned and etched, along with layer 42 as described above, to form capacitor containers 84a.
  • storage capacitors are formed by depositing a storage node layer 86a, a cell dielectric layer 88a, and a cell plate layer 90a. Accordingly, such constitutes forming conductive material at least partially within individual contact openings 74.
  • plugging material 76 of Figs. 13 and 14 might be etched partially inward to provide more room, and thereby more capacitance, for the capacitor being formed.
  • some or all of the insulative material laterally outside of the capacitor container might be etched away in advance of forming the capacitor dielectric layer to provide more surface area and thereby more capacitance.
  • Memory cells of the invention can be fabricated to occupy 6F 2 , 8F 2 or other areas, with 6F 2 being preferred.

Abstract

Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays are described. In one embodiment, a conductive capacitor plug (76) is formed to extend from proximate a substrate node location to a location elevationally above all conductive material of an adjacent bit line (56). The capacitor contact opening is etched through a first insulative material received over a bit line and a word line substantially selective relative to a second insulative material covering portions of the bit line and the word line. The opening is etched to a substrate location proximate the word line in a self-aligning manner relative to both the bit line and the word line. In a preferred embodiment, capacitor-over-bit line memory arrays are formed.

Description

DESCRIPTION
METHODS OF FORMING CONDUCTIVE CAPACITOR PLUGS, METHODS OF
FORMING CAPACITOR CONTACT OPENINGS, AND METHODS OF
FORMING MEMORY ARRAYS
Technical Field
This invention relates to methods of forming conductive capacitor plugs, to methods of forming capacitor contact openings, and to methods of forming memory arrays.
Background Art
Semiconductor processing involves a number of processing steps in which individual layers are masked and etched to form semiconductor components. Mask alignment is important as even small misalignments can cause device failure. For certain photomasking steps, proper alignment is extremely critical to achieve proper fabrication. In others, design rules are more relaxed allowing for a larger margin for alignment errors. One way in which design rules can be relaxed is to provide processing sequences which enable so-called self aligned etches, such as to encapsulated word lines in the fabrication of memory circuitry. Further, there is a goal to reduce or minimize the number of steps in a particular processing flow. Minimizing the processing steps reduces the risk of a processing error affecting the finished device, and reduces cost.
This invention arose out of needs associated with improving the manner in which semiconductor memory arrays, and in particular capacitor-over-bit line memory arrays, are fabricated.
Disclosure of the Invention
Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays are described. In one embodiment, a conductive capacitor plug is formed to extend from proximate a substrate node location to a location elevationaUy above all conductive material of an adjacent bit line. In another embodiment, a capacitor contact opening is etched through a first insulative material received over a bit line and a word line substantially selective relative to a second insulative material covering portions of the bit line and the word line. The opening is etched to a substrate location proximate the word line in a self-aligning manner relative to both the bit line and the word line. In another embodiment, capacitor contact openings are formed to elevationaUy below the bit lines after the bit lines are formed. In a preferred embodiment, capacitor-over-bit line memory arrays are formed.
Brief Description of the Drawings Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
Fig. 1 is a top plan view of the semiconductor wafer fragment in process in accordance with one embodiment of the invention.
Fig. 2 is a view of the Fig. 1 wafer fragment at a different processing step.
Fig. 3 is a view which is taken along line 3-3 in Fig. 2. Fig. 4 is a view of the Fig. 3 wafer fragment at a different processing step.
Fig. 5 is a view of the Fig. 4 wafer fragment at a different processing step.
Fig. 6 is a view of the Fig. 5 wafer fragment at a different processing step.
Fig. 7 is a view of the Fig. 6 wafer fragment at a different processing step. Fig. 8 is a view of the Fig. 2 wafer fragment at a different processing step.
Fig. 9 is a view which is taken along line 9-9 in Fig. 8. Fig. 10 is a view of the Fig. 9 wafer fragment at a different processing step. Fig. 1 1 is a view of the Fig. 10 wafer fragment at a different processing step. Fig. 12 is a view of the Fig. 11 wafer fragment at a different processing step.
Fig. 13 is a view of the Fig. 12 wafer fragment at a different processing step. Fig. 14 is a view which is taken along line 14-14 in Fig. 8 and somewhat reduced in dimension.
Fig. 15 is a view of the Fig. 14 wafer fragment at a different processing step.
Fig. 16 is a view of the Fig. 15 wafer fragment at a different processing step.
Fig. 17 is a view of a semiconductor wafer fragment in process, in accordance with another embodiment of the invention. The Fig. 17 view coincides to processing which can occur after the view depicted in Fig. 12.
Best Modes for Carrying Out the Invention and Disclosure of Invention
Referring to Fig. 1, a semiconductor wafer fragment 20 in process in accordance with one embodiment of the invention includes a semiconductive substrate 22. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Substrate 22 includes a plurality of active areas 24 and a plurality of isolation regions 26. Isolation regions 26 can be formed through various techniques including shallow trench isolation.
Referring to Figs. 2 and 3. a plurality of conductive lines 28 are formed over substrate 22 and constitute word lines of a memory array which is to be formed. Each of word lines 28 includes a gate oxide layer 30, a conductive polysilicon layer 32, and an overlying silicide layer 34. Insulative coverings are formed over individual word lines 28 and include side wall spacers 36 and an insulative cap 38. The insulative coverings preferably encapsulate the word lines. Exemplary insulative materials include oxide formed through decomposition of TEOS, or nitride/oxynitride materials. Diffusion regions 40 are provided and formed intermediate word lines 28 and define substrate node locations with which electrical communication is desired. The illustrated diffusion regions include lightly doped drain (LDD) regions (not specifically designated).
Referring to Fig. 4, a first layer 42 is formed over substrate 22 and between conductive lines 28 and comprises a first insulative material which is different from the insulative material covering or encapsulating word lines 28. An exemplary material is borophosphosilicate glass (BPSG) which can be subsequently reflowed and planarized as by conventional techniques to provide a generally planar uppermost surface 44. A first masking layer 46 is formed over the substrate and defines a plurality of bit line plug mask openings 48. An exemplary material is photoresist. Referring to Fig. 5, material of first layer 42 is etched through bit line plug mask openings 48 and individual substrate diffusion regions 40 between selected word lines 28 are preferably exposed. Such etching forms bit plug openings 50 intermediate the selected word lines.
Referring to Fig. 6, conductive material 52 is formed over and in electrical communication with the individual substrate diffusion regions 40 beneath bit plug openings 50 (Fig. 5). An exemplary material is conductively doped polysilicon which can be deposited, and portions subsequently removed, to isolate the conductive material within the bit plug openings and form individual plugs 54. Plugs 54 can be formed by chemical mechanical polishing conductive material 52 or through various etch back techniques.
Referring to Figs. 7 and 8, individual bit lines 56 are formed and in electrical communication with respective individual conductive bit line plugs 54. Bit lines 56 are formed over insulative material 42 and the illustrated word lines 28. Bit lines 56 include a polysilicon layer 58 and a silicide or other conductive layer 60 (i.e., tungsten). An insulative covering 62 is formed over conductive material of the bit lines and can comprise a suitable oxide, such as one formed through decomposition of TEOS, or nitride/oxynitride materials. The various bit line layers are preferably blanket deposited over the substrate and subsequently photomasked and etched to provide the illustrated bit lines (Fig. 8). Alternately, the bit line plug and the bit line can comprise a common material deposited during the same processing step. For example, layers 52 and 58 could comprise the same material which is deposited thick enough to form both the conductive plug and some or all of bit lines 56.
Referring to Fig. 9, a view is shown which is taken along line 9-9 in Fig. 8 and cuts across three individual bit line plugs 54 and their associated bit lines 56. Referring to Fig. 10, a layer of insulative material is formed over substrate
22 and etched to provide insulative coverings in the form of sidewall spacers 64. Sidewall spacers 64 together with insulative coverings 62 serve to encapsulate the individual bit lines. It will be appreciated, however, that the insulative material which ultimately becomes sidewall spacers 64 need not be etched to form the sidewall spacers at this time. Exemplary materials for insulative material 64 include oxide formed through decomposition of TEOS, or nitride/oxynitride materials. In a preferred embodiment, the insulative material which is utilized to encapsulate the word lines (Fig. 3) is the same material which is utilized to encapsulate the bit lines. Referring to Fig. 11 , a second layer 66 is formed over the word lines and bit lines 56, and preferably comprises the first insulative material which was formed over word lines 28, e.g. BPSG. Such layer is preferably reflowed and planarized. Layers 42, 66 constitute a plurality of separately-formed layers of first insulative material which, in the preferred embodiment, comprise two layers. Referring to Fig. 12, a second patterned masking layer 68 is formed over second layer 66 and defines a plurality of opening patterns 70 over various substrate diffusion regions 40. Openings 70 are formed on opposite sides of individual word lines between which individual bit line plugs are formed. A preferred alternative to forming individual openings 70 over the illustrated diffusion regions is to form a so-called stripe opening which can be opened up over a plurality of the diffusion regions, where of the stripe opening intersects with the bit line spacers. An exemplary stripe opening is illustrated in Fig. 8 inside dashed line 72 (Fig. 8).
Whether individual openings 70 are formed in second masking layer 68 or stripe opening 72 is formed, capacitor contact openings 74 are etched through first and second layers of insulative material 42, 66 respectively. In the illustrated example, capacitor contact openings 74 are etched to elevationaUy below bit lines 56, down to proximate individual word lines of the memory array. In a preferred embodiment, the etching exposes individual diffusion regions 40. In this example, and because individual openings 70 are formed in second masking layer 68, some portions of second layer 66 remain over the individual bit lines. Where, however, the above-mentioned stripe opening 72 (Fig. 8) is formed, all of first insulative material 66 over the individual bit lines would ideally be removed.
In a preferred embodiment, the material which is used to encapsulate both the bit lines and the word lines is selected to comprise the same material, or, a material selective to which layers 42, 66 can be etched. Accordingly, etch chemistries can be selected to etch material of both layers 42, 66 substantially selectively relative to the material encapsulating both the word lines and the bit lines. Hence, capacitor contact openings 74 can be formed in a self-aligning manner to be generally self-aligned to both the bit lines and the word lines. Aspects of the invention also include non-capacitor-over-bit line memory array fabrication processes, and selective etching of contact openings which might not be capacitor contact openings.
Referring to Figs. 13 and 14, conductive material 76 is formed within individual contact openings 74 and in electrical communication with individual respective diffusion regions 40. An exemplary material is conductively doped polysilicon which can be subsequently etched back or chemical mechanical polished to form individual capacitor plugs 78. In the illustrated example, conductive material 76 extends from proximate diffusion regions 40 to respective elevations which are at least laterally proximate (including higher) individual conductive portions of the bit lines. In a preferred embodiment, conductive material 76 extends to locations which are elevationaUy higher than any conductive portion of any bit line. Individual conductive capacitor plugs 78 include individual surfaces 80 proximate which each plug terminates. Surfaces 80 are disposed at elevations above conductive portions of the bit lines.
Referring to Figs. 15 and 16, an insulative layer 82, e.g. BPSG, is formed over the substrate and subsequently patterned and etched to form individual capacitor containers 84 (Fig. 16). Storage capacitors are then formed by depositing a storage node layer 86, a cell dielectric layer 88, and a cell plate layer 90. Accordingly, such constitutes a portion of a capacitor-over-bit line memory array. In but one aspect, the above methods can facilitate formation of memory circuitry over other techniques wherein the capacitor plugs are formed prior to formation of the bit lines. Such other techniques can present alignment problems insofar capacitor container-to-bit line, and capacitor container-to-word line, alignments are concerned. Aspects of the present invention can permit the capacitor plugs to be formed to be generally self-aligned to both the word lines and the bit lines, while preserving the mask count necessary to form the subject memory arrays. Other aspects of the present invention can ease alignment constraints imposed on capacitor container alignment by removing requirements that the containers be etched to be self-aligned to other structures including the bit lines.
Referring to Fig. 17, and in accordance with an alternate embodiment of the present invention, storage capacitors can be formed directly within contact openings 74 (see Fig. 12) such that capacitor plugs 78 (Fig. 13) are not necessary. Like numbers from the above-described embodiment have been utilized where appropriate, with differences being indicated with the suffix "a". A layer 66a is formed over the substrate and subsequently patterned and etched, along with layer 42 as described above, to form capacitor containers 84a. Subsequently, storage capacitors are formed by depositing a storage node layer 86a, a cell dielectric layer 88a, and a cell plate layer 90a. Accordingly, such constitutes forming conductive material at least partially within individual contact openings 74. The above storage capacitor constructions are for illustrative purposes only. Accordingly, other constructions are possible. For example, and by way of example only, plugging material 76 of Figs. 13 and 14 might be etched partially inward to provide more room, and thereby more capacitance, for the capacitor being formed. Further and by way of example only, some or all of the insulative material laterally outside of the capacitor container might be etched away in advance of forming the capacitor dielectric layer to provide more surface area and thereby more capacitance. Memory cells of the invention can be fabricated to occupy 6F2, 8F2 or other areas, with 6F2 being preferred.

Claims

1. In a capacitor-over-bit line memory array, a method of forming a conductive capacitor plug comprising extending conductive material from proximate a substrate node location to a location elevationaUy above all conductive material of an adjacent bit line.
2. The method of claim 1, wherein the extending comprises etching a contact opening through insulative material after forming said bit line and forming conductive material within the contact opening.
3. The method of claim 2, wherein the forming of the conductive material comprises forming a storage capacitor at least partially within the contact opening.
4. The method of claim 1, wherein the extending comprises etching a contact opening through two separately-formed insulative material layers, at least a portion of the contact opening being generally self-aligned to said bit line, and forming conductive material within the contact opening.
5. The method of claim 1, wherein the array comprises a word line elevationaUy below the bit line, and the extending comprises etching a contact opening through insulative material and generally self-aligned to both said bit line and said word line.
6. The method of claim 5, wherein the insulative material comprises two or more separately-formed insulative material layers.
7. The method of claim 1, wherein the extending comprises: forming a patterned masking layer over the substrate and defining an opening pattern over said substrate node location; etching insulative material through the opening pattern sufficient to form a contact opening after forming said bit line; and forming conductive material within the contact opening.
8. The method of claim 7, wherein said opening pattern is formed over a plurality of substrate node locations over which individual capacitors are to be formed.
9. The method of claim 1, wherein said substrate node location comprises a diffusion region, and the extending comprises: etching a contact opening through insulative material to substantially expose a portion of the diffusion region after forming said bit line; and forming conductive material within the contact opening and in electrical communication with the diffusion region.
10. The method of claim 9, wherein said insulative material comprises two separately-formed layers of insulative material.
11. In a capacitor-over-bit line memory array, a method of forming a capacitor contact opening comprising etching an opening through a first insulative material received over a bit line and a word line substantially selective relative to second insulative material covering the bit line and the word line to a substrate location proximate the word line in a self-aligning manner relative to both the bit line and the word line.
12. The method of claim 1 1, wherein the first insulative material comprises separately-formed layers of insulative material.
13. The method of claim 1 1, wherein the first insulative material comprises two separately-formed layers of insulative material.
14. The method of claim 11, wherein the second insulative material separately encapsulates the bit line and the word line.
15. The method of claim 11, wherein the substrate location comprises a diffusion region, and the etching comprises outwardly exposing the diffusion region.
16. The method of claim 11, wherein the etching comprises removing all of the first insulative material from over the bit line.
17. The method of claim 11, wherein the etching comprises forming a patterned masking layer over the first insulative material defining an opening pattern, and etching the opening through the opening pattern.
18. The method of claim 1 1 further comprising forming conductive material within the opening, the conductive material extending to an elevation laterally proximate conductive portions of the bit line.
19. The method of claim 11 further comprising forming conductive material within the opening, the conductive material extending to a location elevationaUy higher than any conductive portion of the bit line.
20. In a capacitor-over-bit line memory array, etching an array of capacitor contact openings to elevationaUy below the bit lines after forming the bit lines.
21. The method of claim 20, wherein the etching comprises etching openings down to proximate individual substrate diffusion regions.
22. The method of claim 20, wherein the etching comprises etching openings down to proximate individual word lines of the array.
23. The method of claim 22, wherein the etching comprises exposing individual substrate diffusion regions intermediate the word lines.
24. The method of claim 20, wherein etching comprises selectively etching through first insulative material relative to second insulative material covering portions of the bit lines.
25. The method of claim 20, wherein the etching comprises selectively etching through first insulative material relative to second insulative material covering portions of the bit lines and word lines of the array.
26. The method of claim 25, wherein the first insulative material comprises a plurality of separately formed layers of first insulative material.
27. The method of claim 20 further comprising forming conductive material within the contact openings, the conductive material extending to at least laterally proximate conductive portions of the bit lines.
28. The method of claim 20 further comprising forming conductive material within the contact openings, the conductive material extending elevationaUy higher than any conductive portions of the bit lines.
29. A method of forming a capacitor-over-bit line memory array comprising: forming a plurality of word lines over a substrate, the word lines having insulating material thereover; forming a plurality of bit lines over the word lines, the bit lines having insulating material thereover; forming insulative material over the word lines and the bit lines, the insulative material being etchably different from the insulating material over the word lines and the insulating material over the bit lines; and selectively etching capacitor contact openings through the insulative material relative to the insulating material over the bit lines and the insulating material over the word lines, the openings being self-aligned to both bit lines and word lines and extending to proximate the substrate.
30. The method of claim 29, wherein the forming of the insulative material comprises forming a plurality of layers of insulative over at least one of the word lines and bit lines.
31. The method of claim 29, wherein forming of the insulative material comprises forming one layer of insulative material over the word lines, and after the forming of the bit lines, forming another layer of insulative material over the bit lines.
32. The method of claim 31 further comprising forming a patterned masking layer over the insulative material defining a mask opening, the mask opening being received over a plurality of substrate locations over which the capacitor contact openings are to be etched, and the etching of the capacitor contact openings comprises etching said contact openings through said mask opening.
33. The method of claim 29 further comprising forming conductive material within the contact openings, the conductive material being formed to extend from proximate individual substrate diffusion regions to at least locations which are elevationaUy coincident with conductive material of the individual bit lines.
34. The method of claim 29 further comprising forming conductive material within the contact openings, the conductive material being formed to extend from proximate individual substrate diffusion regions to locations elevationaUy higher than any conductive material of any of the bit lines.
35. A method of forming a capacitor-over-bit line memory array comprising: forming a plurality of word lines over a substrate; forming a plurality of bit lines over the word lines; forming insulative material over the word lines and the bit lines; and after forming the bit lines, etching an opening through the insulative material and outwardly exposing a diffusion region received within the substrate proximate a word line.
36. The method of claim 35, wherein the forming of the insulative material comprises forming two separate layers of insulative material over the substrate, and the etching of the opening comprises etching the two layers selectively relative to insulative coverings formed over portions of both the bit lines and the word lines.
37. The method of claim 35 further comprising forming conductive material within the opening, the conductive material extending from proximate the diffusion region to a location elevationaUy higher than any conductive material of the bit lines.
38. A method of forming a memory array comprising in sequence: forming a plurality of conductive lines over a substrate; forming a conductive bit line plug intermediate a pair of the conductive lines; forming a bit line in electrical communication with the conductive bit line plug; forming a conductive capacitor plug proximate one of the pair of conductive lines, which capacitor plug extends away from the substrate and terminates above conductive portions of the bit line; and forming a capacitor over and in electrical communication with the capacitor plug.
39. The method of claim 38, wherein the memory array is a capacitor-over-bit line memory array.
40. The method of claim 38, wherein the bit line plug and bit line comprise at least one common material.
41. The method of claim 38, wherein the bit line plug and bit line comprise at least one common material, said common material being deposited in a common processing step.
42. The method of claim 38, wherein the forming of the capacitor plug comprises forming said surface elevationaUy higher than any conductive portion of the bit line.
43. The method of claim 38 further comprising prior to the forming of the conductive bit line plug, forming first insulative material over the conductive lines, and wherein the forming of the conductive capacitor plug comprises substantially selectively etching an opening into the first insulative material relative to second insulative material over the conductive lines.
44. The method of claim 38 further comprising prior to the forming of the conductive capacitor plug, forming first insulative material over the bit line, and wherein the forming of the conductive capacitor plug comprises substantially selectively etching an opening into the first insulative material relative to second insulative material over the bit line.
45. The method of claim 38 further comprising: prior to the forming of the conductive bit line plug, forming a first layer of first insulative material over the conductive lines; and prior to the forming of the conductive capacitor plug, forming a second layer of first insulative material over the bit line, wherein the forming of the conductive capacitor plug comprises substantially selectively etching an opening into the first insulative material relative to second insulative material over the conductive lines and bit line.
46. The method of claim 45, wherein the etching comprises exposing a substrate diffusion region proximate the conductive lines.
47. A method of forming a memory array comprising: forming a plurality of word lines over a substrate, the word lines being encapsulated with a first insulative material; forming a second layer of a second insulative material over the word lines, the second insulative material having a generally planar uppermost surface; patterning the layer of second insulative material to define a bit line plug opening exposing a first substrate diffusion region between two of the word lines; forming conductive material over at least a portion of said second insulative material and in electrical communication with the first substrate diffusion region; removing some of the conductive material over the substrate diffusion region to form a bit line plug in said opening; forming a bit line over the second insulative material and in electrical communication with the bit line plug, the bit line being encapsulated with a third insulative material; forming a layer of a fourth insulative material over the bit line; patterning the layer of fourth insulative material to define an opening over a second substrate diffusion region, said second substrate diffusion region being on an opposite side of one of two word lines between which the bit line plug was formed to form an opening which is generally self-aligned to both the word lines and the bit line; and forming conductive material within said self-aligned opening and extending to a location higher than the bit line.
48. A method of forming a memory array comprising: forming a plurality of word lines over a substrate, the word lines having insulating material thereover; forming a plurality of bit lines over the word lines, the bit lines having insulating material thereover; forming insulative material over the word lines and the bit lines, the insulative material being etchably different from the insulating material over the word lines and the insulating material over the bit lines; and selectively etching contact openings through the insulative material relative to the insulating material over the bit lines and the insulating material over the word lines, the openings being self-aligned to both bit lines and word lines and extending to proximate the substrate.
PCT/US2000/040472 1999-07-22 2000-07-24 Method of forming memory capacitor contact openings WO2001008159A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE10084848T DE10084848T1 (en) 1999-07-22 2000-07-24 Method of forming memory capacitor contact openings
AU73879/00A AU7387900A (en) 1999-07-22 2000-07-24 Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays
DE60026860T DE60026860T2 (en) 1999-07-22 2000-07-24 METHOD FOR PRODUCING STORAGE CAPACITOR CONTACT OPENINGS
JP2001512582A JP2003529915A (en) 1999-07-22 2000-07-24 Method of forming conductive capacitor plug, method of forming capacitor contact opening, and method of forming memory array
EP00962009A EP1277209B1 (en) 1999-07-22 2000-07-24 Method of forming memory capacitor contact openings

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US09/359,956 1999-07-22
US09/359,956 US6589876B1 (en) 1999-07-22 1999-07-22 Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays

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EP1662562A3 (en) 2006-06-28
EP1662563B1 (en) 2008-02-20
EP1662561B1 (en) 2009-06-03
JP2003529915A (en) 2003-10-07
DE60038135D1 (en) 2008-04-03
EP1662561A3 (en) 2006-06-28
US6964910B2 (en) 2005-11-15
US20050213369A1 (en) 2005-09-29
US7449390B2 (en) 2008-11-11
EP1277209A2 (en) 2003-01-22
KR20020085866A (en) 2002-11-16
DE10084848T1 (en) 2002-08-29
EP1662563A2 (en) 2006-05-31
ATE387010T1 (en) 2008-03-15
WO2001008159A3 (en) 2002-11-07
DE60026860D1 (en) 2006-05-11
KR100473910B1 (en) 2005-03-10
EP1277209B1 (en) 2006-03-22
EP1662561A2 (en) 2006-05-31
AU7387900A (en) 2001-02-13
EP1662563A3 (en) 2006-06-28
EP1662562A2 (en) 2006-05-31
US20040097085A1 (en) 2004-05-20
DE60026860T2 (en) 2007-03-15
ATE321337T1 (en) 2006-04-15
ATE433197T1 (en) 2009-06-15
US6589876B1 (en) 2003-07-08
DE60038135T2 (en) 2009-02-12

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