WO2001013426A1 - Method of producing copper features on semiconductor wafers - Google Patents
Method of producing copper features on semiconductor wafers Download PDFInfo
- Publication number
- WO2001013426A1 WO2001013426A1 PCT/IB2000/001115 IB0001115W WO0113426A1 WO 2001013426 A1 WO2001013426 A1 WO 2001013426A1 IB 0001115 W IB0001115 W IB 0001115W WO 0113426 A1 WO0113426 A1 WO 0113426A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- copper
- depositing
- substrate
- depressions
- carried out
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical Vapour Deposition (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00948212A EP1203406A1 (en) | 1999-08-18 | 2000-08-11 | Method of producing copper features on semiconductor wafers |
JP2001517426A JP2003507888A (en) | 1999-08-18 | 2000-08-11 | Method for producing copper features on semiconductor wafers |
KR1020027002079A KR20020020969A (en) | 1999-08-18 | 2000-08-11 | Method of producing copper features on semiconductor wafers |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US37695499A | 1999-08-18 | 1999-08-18 | |
US09/376,954 | 1999-08-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001013426A1 true WO2001013426A1 (en) | 2001-02-22 |
Family
ID=23487177
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2000/001115 WO2001013426A1 (en) | 1999-08-18 | 2000-08-11 | Method of producing copper features on semiconductor wafers |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1203406A1 (en) |
JP (1) | JP2003507888A (en) |
KR (1) | KR20020020969A (en) |
TW (1) | TW457678B (en) |
WO (1) | WO2001013426A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7777059B2 (en) | 2003-12-18 | 2010-08-17 | Basf Se | Copper(I) formate complexes |
US8357613B2 (en) | 2009-02-12 | 2013-01-22 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices and semiconductor devices including a contact plug processed by rapid thermal annealing |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3727277B2 (en) | 2002-02-26 | 2005-12-14 | Necエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
TWI680535B (en) | 2016-06-14 | 2019-12-21 | 美商應用材料股份有限公司 | Oxidative volumetric expansion of metals and metal containing compounds |
TWI719262B (en) | 2016-11-03 | 2021-02-21 | 美商應用材料股份有限公司 | Deposition and treatment of films for patterning |
EP3539154A4 (en) | 2016-11-08 | 2020-06-03 | Applied Materials, Inc. | Geometric control of bottom-up pillars for patterning applications |
TW201839897A (en) | 2017-02-22 | 2018-11-01 | 美商應用材料股份有限公司 | Critical dimension control for self-aligned contact patterning |
WO2018200212A1 (en) * | 2017-04-25 | 2018-11-01 | Applied Materials, Inc. | Selective deposition of tungsten for simplified process flow of tungsten oxide pillar formation |
US10840186B2 (en) | 2017-06-10 | 2020-11-17 | Applied Materials, Inc. | Methods of forming self-aligned vias and air gaps |
TWI719316B (en) * | 2017-06-12 | 2021-02-21 | 美商應用材料股份有限公司 | Seamless tungsten fill by tungsten oxidation-reduction |
TW201906035A (en) | 2017-06-24 | 2019-02-01 | 美商微材料有限責任公司 | Method of producing fully self-aligned vias and contacts |
WO2019046402A1 (en) | 2017-08-31 | 2019-03-07 | Micromaterials Llc | Methods of producing self-aligned grown via |
US10510602B2 (en) | 2017-08-31 | 2019-12-17 | Mirocmaterials LLC | Methods of producing self-aligned vias |
WO2019050735A1 (en) | 2017-09-06 | 2019-03-14 | Micromaterials Llc | Methods of producing self-aligned vias |
CN110034017A (en) | 2017-12-07 | 2019-07-19 | 微材料有限责任公司 | Method for making metal and barrier layer-liner controllably be recessed |
EP3499557A1 (en) | 2017-12-15 | 2019-06-19 | Micromaterials LLC | Selectively etched self-aligned via processes |
TW201939628A (en) | 2018-03-02 | 2019-10-01 | 美商微材料有限責任公司 | Methods for removing metal oxides |
US10790191B2 (en) | 2018-05-08 | 2020-09-29 | Micromaterials Llc | Selective removal process to create high aspect ratio fully self-aligned via |
TW202011547A (en) | 2018-05-16 | 2020-03-16 | 美商微材料有限責任公司 | A method for creating a fully self-aligned via |
US10699953B2 (en) | 2018-06-08 | 2020-06-30 | Micromaterials Llc | Method for creating a fully self-aligned via |
US11164938B2 (en) | 2019-03-26 | 2021-11-02 | Micromaterials Llc | DRAM capacitor module |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5424246A (en) * | 1992-07-31 | 1995-06-13 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor metal wiring layer by reduction of metal oxide |
US5728626A (en) * | 1993-07-26 | 1998-03-17 | At&T Global Information Solutions Company | Spin-on conductor process for integrated circuits |
EP0984488A2 (en) * | 1998-08-31 | 2000-03-08 | Nec Corporation | Multilayer copper interconnect structure with copper oxide portions and manufacturing method thereof |
-
2000
- 2000-08-11 JP JP2001517426A patent/JP2003507888A/en active Pending
- 2000-08-11 WO PCT/IB2000/001115 patent/WO2001013426A1/en not_active Application Discontinuation
- 2000-08-11 EP EP00948212A patent/EP1203406A1/en not_active Withdrawn
- 2000-08-11 KR KR1020027002079A patent/KR20020020969A/en not_active Application Discontinuation
- 2000-08-17 TW TW89116673A patent/TW457678B/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5424246A (en) * | 1992-07-31 | 1995-06-13 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor metal wiring layer by reduction of metal oxide |
US5728626A (en) * | 1993-07-26 | 1998-03-17 | At&T Global Information Solutions Company | Spin-on conductor process for integrated circuits |
EP0984488A2 (en) * | 1998-08-31 | 2000-03-08 | Nec Corporation | Multilayer copper interconnect structure with copper oxide portions and manufacturing method thereof |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7777059B2 (en) | 2003-12-18 | 2010-08-17 | Basf Se | Copper(I) formate complexes |
US8357613B2 (en) | 2009-02-12 | 2013-01-22 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices and semiconductor devices including a contact plug processed by rapid thermal annealing |
KR101534678B1 (en) * | 2009-02-12 | 2015-07-08 | 삼성전자주식회사 | Mothod for manufacturing semiconductor device by annealing rapidly tungsten contact plug under oxygen atmosphere and reducing the RTO pulg under hydrogen atmosphere |
Also Published As
Publication number | Publication date |
---|---|
TW457678B (en) | 2001-10-01 |
JP2003507888A (en) | 2003-02-25 |
EP1203406A1 (en) | 2002-05-08 |
KR20020020969A (en) | 2002-03-16 |
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