WO2001016782A3 - Parallel processor architecture - Google Patents

Parallel processor architecture Download PDF

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Publication number
WO2001016782A3
WO2001016782A3 PCT/US2000/022322 US0022322W WO0116782A3 WO 2001016782 A3 WO2001016782 A3 WO 2001016782A3 US 0022322 W US0022322 W US 0022322W WO 0116782 A3 WO0116782 A3 WO 0116782A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
references
processor
parallel processor
processor architecture
Prior art date
Application number
PCT/US2000/022322
Other languages
French (fr)
Other versions
WO2001016782A9 (en
WO2001016782A2 (en
Inventor
Matthew J Adiletta
Gilbert Wolrich
William Wheeler
Original Assignee
Intel Corp
Matthew J Adiletta
Gilbert Wolrich
William Wheeler
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Matthew J Adiletta, Gilbert Wolrich, William Wheeler filed Critical Intel Corp
Priority to CA002391833A priority Critical patent/CA2391833C/en
Priority to AT00954073T priority patent/ATE253238T1/en
Priority to EP00954073A priority patent/EP1221105B1/en
Priority to DE60006270T priority patent/DE60006270T2/en
Priority to AU66419/00A priority patent/AU6641900A/en
Publication of WO2001016782A2 publication Critical patent/WO2001016782A2/en
Publication of WO2001016782A3 publication Critical patent/WO2001016782A3/en
Publication of WO2001016782A9 publication Critical patent/WO2001016782A9/en
Priority to HK03101706.0A priority patent/HK1049716B/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015One dimensional arrays, e.g. rings, linear arrays, buses
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G06F9/30127Register windows
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824Operand accessing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824Operand accessing
    • G06F9/3834Maintaining memory consistency
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Abstract

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write reference.
PCT/US2000/022322 1999-08-31 2000-08-15 Parallel processor architecture WO2001016782A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CA002391833A CA2391833C (en) 1999-08-31 2000-08-15 Parallel processor architecture
AT00954073T ATE253238T1 (en) 1999-08-31 2000-08-15 PARALLEL PROCESSOR ARCHITECTURE
EP00954073A EP1221105B1 (en) 1999-08-31 2000-08-15 Parallel processor architecture
DE60006270T DE60006270T2 (en) 1999-08-31 2000-08-15 PARALLEL PROCESSOR ARCHITECTURE
AU66419/00A AU6641900A (en) 1999-08-31 2000-08-15 Parallel processor architecture
HK03101706.0A HK1049716B (en) 1999-08-31 2003-03-10 Parallel processor architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/387,111 1999-08-31
US09/387,111 US6606704B1 (en) 1999-08-31 1999-08-31 Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode

Publications (3)

Publication Number Publication Date
WO2001016782A2 WO2001016782A2 (en) 2001-03-08
WO2001016782A3 true WO2001016782A3 (en) 2001-05-31
WO2001016782A9 WO2001016782A9 (en) 2002-06-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/022322 WO2001016782A2 (en) 1999-08-31 2000-08-15 Parallel processor architecture

Country Status (9)

Country Link
US (2) US6606704B1 (en)
EP (1) EP1221105B1 (en)
CN (1) CN1185592C (en)
AT (1) ATE253238T1 (en)
AU (1) AU6641900A (en)
CA (1) CA2391833C (en)
DE (1) DE60006270T2 (en)
HK (1) HK1049716B (en)
WO (1) WO2001016782A2 (en)

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