WO2001026137A3 - Three dimensional device integration method and integrated device - Google Patents

Three dimensional device integration method and integrated device Download PDF

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Publication number
WO2001026137A3
WO2001026137A3 PCT/US2000/021990 US0021990W WO0126137A3 WO 2001026137 A3 WO2001026137 A3 WO 2001026137A3 US 0021990 W US0021990 W US 0021990W WO 0126137 A3 WO0126137 A3 WO 0126137A3
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WIPO (PCT)
Prior art keywords
workpieces
integration method
devices
polished
bonded together
Prior art date
Application number
PCT/US2000/021990
Other languages
French (fr)
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WO2001026137A2 (en
Inventor
Paul M Enquist
Original Assignee
Res Triangle Inst
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Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23623022&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2001026137(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Res Triangle Inst filed Critical Res Triangle Inst
Priority to JP2001529006A priority Critical patent/JP2003524886A/en
Priority to KR1020117015047A priority patent/KR101329836B1/en
Priority to AU78253/00A priority patent/AU7825300A/en
Priority to EP00968318A priority patent/EP1245039A4/en
Publication of WO2001026137A2 publication Critical patent/WO2001026137A2/en
Publication of WO2001026137A3 publication Critical patent/WO2001026137A3/en

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Abstract

A device integration method and integrated device. The method includes the steps of polishing surfaces of first (10) and second (30) workpieces each to a surface roughness of about 5-10Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece (32) is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1-10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies.
PCT/US2000/021990 1999-10-01 2000-09-29 Three dimensional device integration method and integrated device WO2001026137A2 (en)

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JP2001529006A JP2003524886A (en) 1999-10-01 2000-09-29 Three-dimensional device integration method and integrated device
KR1020117015047A KR101329836B1 (en) 1999-10-01 2000-09-29 Method for integrating semiconductor devices
AU78253/00A AU7825300A (en) 1999-10-01 2000-09-29 Three dimensional device integration method and integrated device
EP00968318A EP1245039A4 (en) 1999-10-01 2000-09-29 Three dimensional device integration method and integrated device

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US09/410,054 US6984571B1 (en) 1999-10-01 1999-10-01 Three dimensional device integration method and integrated device

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US20020173120A1 (en) 2002-11-21
US9431368B2 (en) 2016-08-30
EP1245039A2 (en) 2002-10-02
TW471012B (en) 2002-01-01
JP2003524886A (en) 2003-08-19
US6984571B1 (en) 2006-01-10
KR20030036127A (en) 2003-05-09
US20080061419A1 (en) 2008-03-13
JP5744773B2 (en) 2015-07-08
US20150287692A1 (en) 2015-10-08
US20160190093A1 (en) 2016-06-30
KR101328367B1 (en) 2013-12-16
JP2012156514A (en) 2012-08-16
EP1245039A4 (en) 2007-06-27
US20080093747A1 (en) 2008-04-24
US20060292744A1 (en) 2006-12-28
US6905557B2 (en) 2005-06-14
US9564414B2 (en) 2017-02-07
KR101329836B1 (en) 2013-12-16
AU7825300A (en) 2001-05-10
US20170170132A1 (en) 2017-06-15
US7126212B2 (en) 2006-10-24
WO2001026137A2 (en) 2001-04-12
US10366962B2 (en) 2019-07-30
US20080061418A1 (en) 2008-03-13
US20020094661A1 (en) 2002-07-18
KR20110081359A (en) 2011-07-13

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