WO2001031705A1 - Methods for forming co-axial interconnect in a cmos process - Google Patents
Methods for forming co-axial interconnect in a cmos process Download PDFInfo
- Publication number
- WO2001031705A1 WO2001031705A1 PCT/US2000/022516 US0022516W WO0131705A1 WO 2001031705 A1 WO2001031705 A1 WO 2001031705A1 US 0022516 W US0022516 W US 0022516W WO 0131705 A1 WO0131705 A1 WO 0131705A1
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- WIPO (PCT)
- Prior art keywords
- layer
- forming
- metallization layer
- oxide layer
- over
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49123—Co-axial cable
Definitions
- the present invention relates to the manufacture of semiconductor devices. More particularly, the present invention relates to the integration of radio frequency (RF) features, RF devices, microwave features, and microwave devices into standard complementary metal oxide semiconductor (CMOS) chips.
- RF radio frequency
- CMOS complementary metal oxide semiconductor
- CMOS chips and RF chips In order to meet the demands, semiconductor devices employ CMOS chips and RF chips. Such devices include, for example, cellular phones that require both digital CMOS circuitry as well as RF circuitry to enable wireless communication.
- CMOS circuitry In order to integrate both digital CMOS and RF circuitry onto one chip, manufacturers have been forced to use co-axial interconnect lines to handle the RF signals.
- current high speed technology using CMOS circuitry suffers large losses of power.
- Today's devices are expected to handle high speed applications such as RF and microwave applications.
- standard digital CMOS interconnects will be expected to run at frequencies up to and greater than 1 GHz.
- Figures 1A and IB represent a cross-sectional view and a top view, respectively, of a prior art interconnect structure 12 having a suspended portion 14 over a silicon substrate 10.
- Interconnect structure 12 includes an inner conductor 20, an insulating dielectric coating 18 and an outer conductive layer that serves to encapsulate the insulating dielectric coating 18.
- Interconnect structure 12 also includes two contact posts 13 fabricated that have a larger dimension so as to support suspended portion 14.
- Circuit 50 requires that RF circuit 55 and the CMOS chip 52 be individually fabricated and integrated onto the printed circuit board (PCB) 51. This increases manufacturing costs and manufacturing time.
- Microwave and RF applications operate at high frequencies. The high frequencies require the use of co-axial lines or waveguides. When these lines are integrated with standard CMOS lines, a large loss of power occurs. In order to compensate for these losses, amplification circuitry may be necessary.
- the present invention fills these needs by providing an integrated circuit device which can integrate both standard CMOS circuitry and co-axial lines that are capable of handling RF signals, microwave signals and other high speed signals, and methods for making such a device. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.
- a method of forming a co-axial interconnect line in a dielectric layer is disclosed. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.
- a semiconductor device incorporating a co-axial interconnect line in another embodiment, includes a dielectric layer and a trench defined within the dielectric layer.
- a shield metallization layer is defined over the dielectric layer and along the trench.
- the semiconductor device also includes a center conductor contained within the shield metallization layer.
- An oxide layer surrounds the center conductor.
- a cap metallization layer is defined over the oxide layer and over the shield metallization layer, such that the cap metallization layer is in electrical contact with the shield metallization layer.
- the cap metallization layer and the shield metallization layer form an outer shield of a co-axial line and the center conductor forms the inner conductor of the co-axial line.
- a method for making a semiconductor device with co- axial interconnect lines in a CMOS chip for high speed applications includes forming a trench in a base dielectric layer and forming a shield metallization layer over the base dielectric layer and the trench. After the shield metallization layer is formed, a conformal oxide layer is deposited over the shield metallization layer such that the conformal oxide layer defines a region within the trench. Once the conformal oxide layer is deposited, a liner metallization layer is formed over the conformal oxide layer and over the region within the trench. Next, a conductive layer is disposed within the liner metallization layer to fill the region within the trench with conductive material.
- the conductive layer is disposed within the liner metallization layer
- the conductive layer is etched along with the liner layer to define an inner conductor within the region that is defined within the trench.
- an oxide layer is formed over the inner conductor that is defined by the liner layer and the conductive layer, whereby the oxide layer is configured to fill the region within the trench.
- the oxide layer and the conformal oxide layer are then planarized down to the shield metallization layer.
- a cap metallization layer is then formed over the shield metallization layer, the conformal oxide layer, and the oxide layer defined within the trench.
- a semiconductor application can now integrate co-axial features and standard CMOS features on a single chip, and the co-axial features can be integrated on any level of a chip's interconnect region. As such, designers are no longer required to design and fabricate separate chips having co-axial lines and CMOS chips to make a desired integrated circuit application.
- the present invention has the ability to handle high speed applications, such as RF, microwave applications and other applications operating at frequencies up to and greater than 1 GHz.
- Figure 1A depicts a cross-sectional view of a prior art interconnect structure.
- Figure IB represents a top view of the prior art interconnect structure.
- Figure 1C is a top view of a prior art implementation using a separate RF chip and CMOS chip.
- Figure 2 is a cross-sectional view of a semiconductor substrate with a dielectric layer placed above the semiconductor substrate.
- Figure 3 illustrates the formation of a trench which is used to form a co-axial interconnect line in accordance with one embodiment of the present invention.
- Figure 4 shows the deposition of a shield metallization layer in accordance with one embodiment of the present invention.
- Figure 5 illustrates the deposition of a conformal oxide layer.
- Figure 6 demonstrates the deposition of a liner metallization layer and the deposition of a tungsten metallization layer.
- Figure 7 depicts the formation of a center conductor in accordance with one embodiment of the present invention.
- Figure 8 illustrates the deposition of a gap fill oxide in accordance with one embodiment of the present invention.
- Figure 9 illustrates the gap fill oxide and the resultant oxide surrounding the center conductor in accordance with one embodiment of the present invention.
- Figure 10 shows a cap metallization layer formed over the shield metallization layer and the gap fill oxide in accordance with one embodiment of the present invention.
- Figure 11A shows the formation of an oversize via in the cap metallization layer.
- Figure 11B depicts a simplified three-dimensional view of a co-axial line defined in a dielectric in accordance with one embodiment of the present invention.
- Figure 12 shows the formation of vias to the center conductor and the cap metallization layer through an inter-metal oxide.
- Figure 13 illustrates the formation of a center conductor via and an outer conductor via in accordance with an embodiment of the present invention.
- Figure 14 illustrates the deposition of tungsten in the center conductor via and the outer conductor via.
- Figure 15 shows a semiconductor device with a co-axial interconnect line in a CMOS chip in accordance with one embodiment of the present invention.
- a semiconductor device with an integrated co-axial interconnect line in a dielectric layer is disclosed.
- numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be understood, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
- FIGS 1A - 1C were described with reference to the prior art.
- a cross-sectional view of a semiconductor substrate 100 is shown.
- a dielectric layer 102 is formed over the substrate 100, which typically has active transistor devices (not shown).
- the dielectric layer 102 is placed through a chemical mechanical polishing operation (CMP) in order to planarize a top surface of dielectric layer 102.
- CMP chemical mechanical polishing operation
- FIG 3 illustrates the formation of a trench 106, which will be used to form a coaxial interconnect line, in accordance with one embodiment of the present invention.
- a photoresist mask 104 is shown patterned over dielectric layer 102 which defines a region where the trench 106 is desired.
- a dielectric etch operation 108 is then performed to form the trench 106.
- the trench 106 is defined by a trench depth (TD) and a trench width (TW).
- the TW ranges from about 0.5 micron to about 100 microns, more preferably from about 1 micron to about 10 microns, and most preferably 1 micron.
- the depth of the TD is preferably between about 5,000 Angstroms and about 10,000 Angstroms, and more preferably about 7,000 Angstroms. In situations where wider trenches are desired, an additional mask should be used to protect the trench filled tungsten during the tungsten etchback operation.
- FIG. 4 shows a deposited shield metallization layer 110, in accordance with one embodiment of the present invention.
- the shield metallization layer 110 is preferably formed by depositing a layer of titanium nitride on the surface of dielectric layer 102 and along the walls of trench 106 as shown.
- the shield metallization layer 110 may also be any other suitable conductive material, such as titanium (Ti) or a combination of titanium and tungsten (Ti:W).
- the shield metallization layer 110 is preferably between about 100 Angstroms and about 1,000 Angstroms, and more preferably between about 200 Angstroms and about 500 Angstroms, and most preferably about 300 Angstroms.
- the shield metallization layer 110 will be used to define a outer shield of a co-axial line.
- the co-axial line can be used to transmit RF signals, microwave-type signals, and other high speed signals within a CMOS design.
- Figure 5 illustrates the deposition of a conformal oxide layer 112.
- the conformal oxide layer 112 is deposited over the shield metallization layer 110 and along the walls of the trench 106 using a plasma enhanced chemical vapor deposition (PECVD) technique.
- PECVD plasma enhanced chemical vapor deposition
- the conformal oxide layer 112 preferably has a thickness in the range of about 300 Angstroms to about 5,000 Angstroms and more preferably about 1,000 Angstroms.
- it is desired that the conformal nature of the PECVD or other suitable deposition technique leave a region within the trench 106. This region will then be used to define a center conductor, as will be described in greater detail with reference to Figure 7.
- Figure 6 demonstrates the deposition of a liner metallization layer 114 and a tungsten metallization layer 116.
- the liner metallization layer 114 is deposited over the conformal oxide layer 112 and along the walls of the trench 106 as shown.
- the liner metallization layer 114 is preferably deposited to a thickness ranging from about 100 Angstroms to about 500 Angstroms, and more preferably about 200 Angstroms.
- the liner metallization layer 114 is also preferably titanium nitride (TiN).
- TiW titanium tungsten
- W tungsten
- Ta tantalum
- the tungsten metallization layer 116 is subsequently deposited over the liner metallization layer 114, thus filling the trench 106.
- the tungsten metallization layer 116 is preferably deposited to a thickness of about 3,000 Angstroms to about 10,000 Angstroms, and more preferably to about 6,000 Angstroms. In general, the thickness of the deposited tungsten should be selected such that the region within the trench is substantially filled. In this embodiment, the tungsten metallization layer 116 is preferably tungsten, however, other suitable conductive materials may also be used, such as aluminum (Al) and copper (Cu).
- FIG. 7 depicts the formation of a center conductor 119 in accordance with one embodiment of the present invention.
- the center conductor 119 is preferably defined using a metallization etch operation 118.
- the metallization etch operation 118 removes the tungsten metallization layer 116 and the liner metallization layer 114 to a desired depth.
- the remaining tungsten metallization layer 116 and the liner metallization layer 114 define a core thickness (CT).
- the CT is configured to define a center conductor 119 of the co-axial line.
- the thickness of the CT is preferably between about 2,000 Angstroms and about 7,000 Angstroms, and more preferably is about 4,000 Angstroms.
- the shield metallization layer 110 defines part of the outer shield.
- Figure 8 illustrates a gap fill oxide 120 in accordance with one embodiment of the present invention.
- the gap fill oxide 120 is preferably deposited using a high density plasma chemical vapor deposition (HDP CVD) process over the center conductor 119 and the conformal oxide layer 112, thus filling the trench 106. After deposition is complete, the gap fill oxide 120 is planarized as shown in Figure 9 to form an oxide layer over the center conductor 119.
- HDP CVD high density plasma chemical vapor deposition
- Figure 9 illustrates the gap fill oxide 120 and the resultant oxide 112 surrounding the center conductor 119 after a planarization operation is complete.
- a CMP operation is performed which removes gap fill oxide 120 down to the shield metallization layer 110.
- a top surface of the gap fill oxide 120 is planar with a top surface of the shield metallization layer 110.
- Figure 10 shows a cap metallization layer 122 formed over the shield metallization layer 110 and the gap fill oxide 120 in accordance with one embodiment of the present invention.
- the cap metallization layer 122 is deposited over the shield metallization layer 110 such that the cap metallization layer 122 is in electrical contact with the shield metallization layer 110.
- the cap metallization layer 122 is deposited over portions of the conformal oxide layer 120, and the gap fill oxide 120.
- the cap metallization layer 122 is preferably titanium nitride. Nonetheless, other suitable conductive materials, such as titanium tungsten (TiW), tungsten (W) and tantalum (Ta) can also be used for the cap metallization layer 122.
- the shield metallization layer 122 is configured to complete the enclosure (e.g., the shield metallization layer 110 and cap metallization layer 122) that defines the co-axial line, which is well suited to handle high frequency signals.
- signals can include RF signals, and microwave signals.
- an oversize via in the cap metallization layer 122 is shown.
- a photoresist mask 124 is formed onto the cap metallization layer 122 using standard photoresist patterning and metal etching 126.
- the metal etching operation 126 should be configured to substantially remove the cap metallization layer 122 down to the gap fill oxide 120.
- Figure 11A shows the formation of an oversize via 122a in the cap metallization layer 122.
- the oversize via 122a is defined within the cap metallization layer 122 such that the oversize via 122a is located over the center conductor 119.
- the oversize via 122a will allow the formation a center conductor via, as will be shown in Figure 13.
- the center conductor via will define an electrical contact between the center conductor 119 and CMOS circuitry located throughout the semiconductor device.
- Figure 11A defines a cross- section A-A which will now be further described with reference to Figure 11B.
- Figure 11B depicts a simplified three-dimensional view of a co-axial line defined in a dielectric in accordance with one embodiment of the present invention.
- the co-axial line is defined by an outer shield and the center conductor 119.
- the outer shield is partially defined by the cap metallization layer 122 and the shield metallization layer 110.
- Figure 11B shows a via 121 defining a path to the center conductor 119.
- the via may be located anywhere along the co-axial line in order to integrate the center conductor 119 and the co-axial line with various CMOS lines located throughout a semiconductor device.
- Figure 12 shows the formation of vias to the center conductor 119 and the cap metallization layer 122 through inter-metal oxide 128.
- the inter-metal oxide layer 128 is deposited over cap metallization layer 122 and gap fill oxide 120 using standard deposition techniques. Once the deposition is complete, the inter-metal oxide layer 128 is then planarized to allow the spin coating of photoresist.
- the photoresist is patterned to define a photoresist mask 130 having a center conductor window 130a and an outer conductor window 130b.
- a dielectric etch operation 132 is then performed which etches away portions of inter-metal oxide 128 and gap fill oxide 120 as shown in Figure 13.
- Figure 13 illustrates the center conductor via 128a and outer conductor via 128b in accordance with an embodiment of the present invention.
- the dielectric etch operation 132 as described above, formed the vias 128a and 128b through the inter-metal oxide layer 128.
- tungsten is deposited in vias 128a and 128b as shown in Figure 14.
- Figure 14 illustrates the deposition of tungsten over the inter-metal oxide 128 and in the vias 128a and 128b.
- a tungsten fill layer 134 is deposited such that the vias 128a and 128b are adequately filled.
- tungsten etch back operation is performed to remove the tungsten fill layer 134 down to the inter-metal oxide layer 128.
- the tungsten fill layer 134 allows electrical contact for the center conductor 119 and the cap metallization layer 122. These electrical connections therefore enable integration of high frequency devices to other CMOS circuitry located throughout the semiconductor device.
- Figure 15 shows a partial view of a cross-section of a semiconductor device with a co-axial interconnect line.
- the co-axial interconnect line is capable of being integrated into a chip that can process digital CMOS operations as well as high speed applications.
- a CMOS metallization line 136b is in electrical contact with cap metallization layer 122 through outer conductor via 134b as shown.
- Another CMOS metallization line 136a is in electrical contact with the center conductor 119 through center conductor conductive via 134a.
- the center conductor 119 acts as an inner conductor for the co-axial line and cap metallization layer 122 serves as part of the outer shield for the same co-axial line.
- the co-axial line is capable of handling RF signals, microwave signals and other high speed signal applications. As shown in this particular embodiment, it is now possible to integrate co-axial lines capable of handling high speed applications such as RF signals and microwave signals with CMOS lines in a semiconductor device.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE60038786T DE60038786D1 (en) | 1999-10-28 | 2000-08-16 | METHOD FOR PRODUCING COAXIAL CONNECTING LINES IN A CMOS PROCESS |
JP2001534201A JP2003513450A (en) | 1999-10-28 | 2000-08-16 | Method of forming coaxial interconnect lines in a CMOS process |
EP00957505A EP1145312B1 (en) | 1999-10-28 | 2000-08-16 | Methods for forming co-axial interconnect lines in a cmos process |
KR1020017008215A KR20010093229A (en) | 1999-10-28 | 2000-08-16 | Methods for forming co-axial interconnect in a cmos process |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/429,540 US6569757B1 (en) | 1999-10-28 | 1999-10-28 | Methods for forming co-axial interconnect lines in a CMOS process for high speed applications |
US09/429,540 | 1999-10-28 |
Publications (1)
Publication Number | Publication Date |
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WO2001031705A1 true WO2001031705A1 (en) | 2001-05-03 |
Family
ID=23703698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/022516 WO2001031705A1 (en) | 1999-10-28 | 2000-08-16 | Methods for forming co-axial interconnect in a cmos process |
Country Status (7)
Country | Link |
---|---|
US (1) | US6569757B1 (en) |
EP (1) | EP1145312B1 (en) |
JP (1) | JP2003513450A (en) |
KR (1) | KR20010093229A (en) |
CN (1) | CN1333463C (en) |
DE (1) | DE60038786D1 (en) |
WO (1) | WO2001031705A1 (en) |
Cited By (2)
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JP2003152093A (en) * | 2001-07-23 | 2003-05-23 | Agere Systems Guardian Corp | Method and structure for dc and rf shielding of integrated circuit |
DE10215328A1 (en) * | 2001-12-28 | 2003-07-10 | Ihp Gmbh | Isolation method for semiconductor devices used in microelectronics comprises a first switch, a second switch and a screen consisting of metal screening element for screening impurity signals between the two switches |
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US6255852B1 (en) | 1999-02-09 | 2001-07-03 | Micron Technology, Inc. | Current mode signal interconnects and CMOS amplifier |
US7554829B2 (en) | 1999-07-30 | 2009-06-30 | Micron Technology, Inc. | Transmission lines for CMOS integrated circuits |
US6373740B1 (en) * | 1999-07-30 | 2002-04-16 | Micron Technology, Inc. | Transmission lines for CMOS integrated circuits |
US6975189B1 (en) * | 2000-11-02 | 2005-12-13 | Telasic Communications, Inc. | On-chip multilayer metal shielded transmission line |
US7101770B2 (en) * | 2002-01-30 | 2006-09-05 | Micron Technology, Inc. | Capacitive techniques to reduce noise in high speed interconnections |
JP2003264405A (en) * | 2002-03-08 | 2003-09-19 | Opnext Japan Inc | High frequency transmission line, electronic component using the same and electronic equipment |
US7235457B2 (en) * | 2002-03-13 | 2007-06-26 | Micron Technology, Inc. | High permeability layered films to reduce noise in high speed interconnects |
US6846738B2 (en) * | 2002-03-13 | 2005-01-25 | Micron Technology, Inc. | High permeability composite films to reduce noise in high speed interconnects |
US6900116B2 (en) * | 2002-03-13 | 2005-05-31 | Micron Technology Inc. | High permeability thin films and patterned thin films to reduce noise in high speed interconnections |
US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
DE10220653A1 (en) * | 2002-05-08 | 2003-11-27 | Infineon Technologies Ag | Integrated conductor arrangement |
KR100474853B1 (en) * | 2003-01-29 | 2005-03-10 | 삼성전자주식회사 | One-chipped direct conversion transceiver for reducing DC offset and method making the same |
US6970053B2 (en) * | 2003-05-22 | 2005-11-29 | Micron Technology, Inc. | Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US8168891B1 (en) * | 2007-10-26 | 2012-05-01 | Force10 Networks, Inc. | Differential trace profile for printed circuit boards |
TWI340002B (en) * | 2008-04-07 | 2011-04-01 | Unimicron Technology Corp | Circuit board and manufacturing method thereof |
US8279025B2 (en) * | 2008-12-09 | 2012-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Slow-wave coaxial transmission line having metal shield strips and dielectric strips with minimum dimensions |
US9349636B2 (en) | 2013-09-26 | 2016-05-24 | Intel Corporation | Interconnect wires including relatively low resistivity cores |
US10410939B2 (en) * | 2015-12-16 | 2019-09-10 | Intel Corporation | Package power delivery using plane and shaped vias |
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- 1999-10-28 US US09/429,540 patent/US6569757B1/en not_active Expired - Lifetime
-
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- 2000-08-16 WO PCT/US2000/022516 patent/WO2001031705A1/en active Application Filing
- 2000-08-16 CN CNB008043604A patent/CN1333463C/en not_active Expired - Fee Related
- 2000-08-16 JP JP2001534201A patent/JP2003513450A/en not_active Withdrawn
- 2000-08-16 EP EP00957505A patent/EP1145312B1/en not_active Expired - Lifetime
- 2000-08-16 KR KR1020017008215A patent/KR20010093229A/en not_active Application Discontinuation
- 2000-08-16 DE DE60038786T patent/DE60038786D1/en not_active Expired - Lifetime
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PATENT ABSTRACTS OF JAPAN vol. 010, no. 275 (E - 438) 18 September 1986 (1986-09-18) * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003152093A (en) * | 2001-07-23 | 2003-05-23 | Agere Systems Guardian Corp | Method and structure for dc and rf shielding of integrated circuit |
DE10215328A1 (en) * | 2001-12-28 | 2003-07-10 | Ihp Gmbh | Isolation method for semiconductor devices used in microelectronics comprises a first switch, a second switch and a screen consisting of metal screening element for screening impurity signals between the two switches |
Also Published As
Publication number | Publication date |
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DE60038786D1 (en) | 2008-06-19 |
US6569757B1 (en) | 2003-05-27 |
EP1145312A1 (en) | 2001-10-17 |
KR20010093229A (en) | 2001-10-27 |
CN1342330A (en) | 2002-03-27 |
EP1145312B1 (en) | 2008-05-07 |
JP2003513450A (en) | 2003-04-08 |
CN1333463C (en) | 2007-08-22 |
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