WO2001042936A3 - Transceiver with latency alignment circuitry - Google Patents
Transceiver with latency alignment circuitry Download PDFInfo
- Publication number
- WO2001042936A3 WO2001042936A3 PCT/US2000/041554 US0041554W WO0142936A3 WO 2001042936 A3 WO2001042936 A3 WO 2001042936A3 US 0041554 W US0041554 W US 0041554W WO 0142936 A3 WO0142936 A3 WO 0142936A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- transceiver
- controller
- channel
- data
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU26175/01A AU2617501A (en) | 1999-12-09 | 2000-10-24 | Transceiver with latency alignment circuitry |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/458,582 | 1999-12-09 | ||
US09/458,582 US6643752B1 (en) | 1999-12-09 | 1999-12-09 | Transceiver with latency alignment circuitry |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001042936A2 WO2001042936A2 (en) | 2001-06-14 |
WO2001042936A3 true WO2001042936A3 (en) | 2001-12-27 |
Family
ID=23821342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/041554 WO2001042936A2 (en) | 1999-12-09 | 2000-10-24 | Transceiver with latency alignment circuitry |
Country Status (3)
Country | Link |
---|---|
US (6) | US6643752B1 (en) |
AU (1) | AU2617501A (en) |
WO (1) | WO2001042936A2 (en) |
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- 2000-10-24 WO PCT/US2000/041554 patent/WO2001042936A2/en active Application Filing
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2003
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2005
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2006
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2007
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Also Published As
Publication number | Publication date |
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AU2617501A (en) | 2001-06-18 |
US7010658B2 (en) | 2006-03-07 |
US20050160247A1 (en) | 2005-07-21 |
US8086812B2 (en) | 2011-12-27 |
US20070118711A1 (en) | 2007-05-24 |
US6643752B1 (en) | 2003-11-04 |
US7065622B2 (en) | 2006-06-20 |
US20040128460A1 (en) | 2004-07-01 |
WO2001042936A2 (en) | 2001-06-14 |
US20050149685A1 (en) | 2005-07-07 |
US7124270B2 (en) | 2006-10-17 |
US20070011426A1 (en) | 2007-01-11 |
US8458426B2 (en) | 2013-06-04 |
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