WO2001048595A1 - Processing multiply-accumulate operations in a single cycle - Google Patents
Processing multiply-accumulate operations in a single cycle Download PDFInfo
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- WO2001048595A1 WO2001048595A1 PCT/US2000/032887 US0032887W WO0148595A1 WO 2001048595 A1 WO2001048595 A1 WO 2001048595A1 US 0032887 W US0032887 W US 0032887W WO 0148595 A1 WO0148595 A1 WO 0148595A1
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- adder
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- 238000012545 processing Methods 0.000 title description 10
- 239000013598 vector Substances 0.000 claims description 54
- 238000000034 method Methods 0.000 claims description 13
- 241000030538 Thecla Species 0.000 description 21
- 238000013461 design Methods 0.000 description 7
- 238000007792 addition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000000295 complement effect Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000035508 accumulation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
Definitions
- This invention relates to processor-based systems and, more particularly, to multiply- accumulate units.
- a multiply-accumulate unit is a unit designed to perform multiplication operations. In a processor-based system, for example, such operations may be plentiful.
- MACs may be implemented using a variety of logic. Because of the abundance of multiplication operations in some applications, the fastest performing MAC is generally preferred. The success of any MAC design may depend upon the power requirements, the available space which may be allocated to MAC circuitry, and the intended use for the MAC, among other considerations.
- a tradeoff between speed and cost makes the design of an optimally performing MAC difficult.
- the cost may come in the form of additional hardware, the chip space necessary to accommodate that hardware, or in the power needed to drive the hardware.
- DSP digital signal processing
- some critical operations may involve a series of multiplications and or accumulations. Accordingly, a high-throughput MAC is essential to achieving high performance.
- many DSP applications today require low power consumption, particularly in the portable electronics market.
- a method includes receiving a first set of operands in a first portion of a unit, performing a plurality of operations on the first set of operands to arrive at a first intermediate result and receiving a second set of operands in the first portion of the unit. Following these, a second plurality of operations is performed on the first intermediate result to arrive at a first final result while the first plurality of operations is performed on the second set of operands to arrive at a second intermediate result.
- Figure 1 is a block diagram of a multiply accumulate unit according to one embodiment of the invention.
- Figures 2A and 2B are flow diagrams of a multiply operation performed using the MAC of Figure 1 according to one embodiment of the invention
- Figure 3 is a chart of the performance time for 16-bit multiplication operations using the MAC of Figure 1 according to one embodiment of the invention
- Figures 4A - 4C are flow diagrams of an implicit multiply operation performed using the MAC of Figure 1 according to one embodiment of the invention.
- Figure 5 is a flow diagram of a multiply operation using packed data instructions performed using the MAC of Figure 1 according to one embodiment of the invention.
- a MAC typically includes a Booth encoder, also called a Booth recoder or Booth multiplier.
- a Booth encoder may reduce the number of stages used to perform the multiplication. The number of partial products that are added together thus may be reduced.
- the number of partial products may be reduced from sixteen to eight, a factor of two.
- Wallace trees are structures for performing multiple addition operations. Wallace trees typically include features, such as adders, to help perform the addition of multiple partial products.
- a Wallace tree may include a group of carry-save adders.
- the output carry is "saved" for the next operation, thus, the name.
- Wallace trees may organize carry-save adders or similar logic such that a number of input values typically produces two results, a sum value and a carry value.
- a four-stage Wallace tree may include four stages of 3-to-2 carry-save adders. The four-stage
- Wallace tree may receive nine input vectors, and produce a sum vector and a carry vector as its result.
- a carry look-ahead adder is one such logic device.
- the CLA may efficiently perform the addition of two multi-bit operands.
- the ability of the MAC to multiply 16-bit signed integers at a very fast rate is a paramount concern.
- the MAC could include additional circuitry. For example, each component of the MAC could be duplicated, such that multiple operations run simultaneously. Control logic to keep track of the parallel operations would be part of the MAC as well.
- the additional hardware may be costly, the available space may be limited, and additional power to support the new hardware may be used.
- Another MAC design may pipeline the operations, such that a new multiply operation may be processed while a prior operation is not yet completed by the MAC hardware, somewhere down the pipeline.
- Pipelining may involve a number of stages of the operation being performed, each stage operating independently from the others.
- Pipelining may thus utilize additional control logic and hardware, such as registers, for temporarily storing the state of the two, three, or more, independent operations being conducted simultaneously by the MAC hardware.
- additional control logic may add to development cost and diminish available board or chip space.
- a MAC which supports pipelining may run more slowly.
- a higher throughput MAC may be implemented using conventional architectural features, without excessively impacting the cost or power requirements of the hardware.
- a MAC design provides a single-cycle throughput for 16-bit multiplication operations by simultaneously operating two functional units of the
- a MAC 100 includes a Booth encoder 10, a multiplexer, or MUX, array
- the MAC 100 may receive two input values, a multiplicand,
- the input values A, B, and C may be 16-bit, 32-bit, or larger signed integer values, for example.
- the Booth encoder receives up to sixteen bits of the multiplier, B, at a time, and thus produces up to eight control signals 12a - 12h.
- the MUX array 14 receives the eight control signals 12a - 12h from the Booth encoder 10 as well as receiving the multiplicand, A.
- the MUX array 14 produces up to eight partial products,
- the Wallace tree 20 is a four-stage unit, including a plurality of carry-save adders (not shown).
- the Wallace tree 20 thus receives nine input signals and produces two output signals, a sum vector 22a and a carry vector 22b.
- the sum vector 22a and the carry vector 22b may subsequently be fed into the CLA 30, to be added together. Alternatively or simultaneously, the sum vector 22a and the carry vector 22b may be routed back to the MUX array 14, for further processing.
- the MAC 100 includes three banks of flip-flops 6a - 6c.
- the flip-flops 6 enable portions of the multiplicand A, the multiplier B, and the accumulate data C to be sent to the other logic of the MAC 100 for processing. For example, if a 32-bit multiplier, B[31 :0], is sent to the MAC 100 as part of a multiplication operation, the flip-flops 6b may toggle between two 16-bit portions, B [31 :16] or B[15:0], controlling which portion of the multiplier
- the MAC 100 also includes MUXs 8a - 8e.
- the MUXs 8 may control the receipt of a signal by a subsequent unit of the MAC 100.
- the MUXs 8a - 8c work in conjunction with the flip-flops 6a - 6c to control which portion of the multiplicand A, the multiplier B, or the accumulator C may be received by the MUX array 14, the Booth encoder
- the MUXs 8d control receipt of the sum vector 22a and the carry vector 22b by the CLA 30.
- the MUXs 8e enable the output value 34 from the
- the MAC 100 includes two banks of MUXs and flip-flops units 24a and 24b which receive the output signals 22a and 22b from the Wallace tree 20.
- the MUXs and flip-flops unit 24a is used to feed part of the sum vector 22a and the carry vector 22b back to the MUX array 14.
- the portion 26a fed back to the MUX array 14 depends upon the type of operation being performed. Such feedback is a feature common to multi-stage MAC operations, such as for performing a 32-bit multiplication.
- the MAC 100 includes a second MUXs and flip-flops unit 24b, to which the sum vector 22a and the carry vector 22b are also sent. Subsequently, these values may be sent to the CLA 30 via the MUXs 8d. In one embodiment of the invention, the sum vector 22a and the carry vector 22b are sent to both units 24a and 24b simultaneously.
- the MAC 100 includes architectural enhancements which may improve throughput for multiplication operations.
- the MAC 100 includes two registers, an accumulator A 32a and an accumulator B 32b.
- the accumulators 32 may receive the result vector 34 from the CLA 30.
- the result vector 34 is alternatively stored in the accumulators 32. For example, in a first operation, the result vector, which may be an intermediate result, is stored in the accumulator A 32a. In a subsequent operation, the subsequent result vector is stored in the accumulator B 32b.
- the accumulators 32 are each connected to the MUXs 8c, for submission to the Wallace tree 20.
- the configuration allows the values stored in either accumulator 32 to be submitted to the Wallace tree 20 as the accumulate data instead of receiving the accumulated data from a source (C) external to the MAC 100.
- the accumulators 32 may facilitate the throughput of operations performed in the MAC 100 in one embodiment of the invention.
- the MAC 100 may support implicit instructions such as an implicit multiply instruction.
- An implicit instruction is one where one or more intermediate results may be stored internally to the MAC, such as in a register. Including a register in the MAC circuitry may allow the MAC to avoid sending intermediate results to a storage location outside the MAC over an external bus, for example.
- a MAC which supports implicit operations may process instructions more quickly than a MAC with no such support.
- the MAC circuitry may provide multiple intermediate results before arriving at the final result.
- the conventional MAC design typically receives an intermediate result, an intermediate sum vector and an intermediate carry vector, from the Wallace tree and feeds the results back into the MUX array for subsequent processing. This scheme is repeated as necessary. Eventually, the sum vector and the carry vector produced by the Wallace tree represent the final result. These values are subsequently sent to the CLA, where they are added together and sent out of the MAC circuitry as the final result.
- the intermediate sum vector 22a and the intermediate carry vector 22b may be sent to the CLA 30 in each cycle, if desired.
- the CLA 30 may then add the intermediate sum vector 22a and the intermediate carry vector 22b, to produce an intermediate result 34, which may then be stored in one of the accumulators 32.
- Feedback logic in the MAC 100 design permits the intermediate result 34 to be fed from one of the accumulators 32 back into the Wallace tree 20, via the MUXs 8c, as accumulate data 18.
- the Wallace tree 20 includes an input line 18 for the accumulator C.
- the MUXs 8c permit the source of the accumulate data 18 to include the accumulators 32.
- the MAC 100 provides circuitry which allows simultaneous operation of both the Wallace tree 20 and the CLA 30.
- This circuitry includes early termination logic 50 and MAC control logic 52, in one embodiment of the invention.
- This circuitry may control the simultaneous processing of more than one multiplication operation or of more than one portion of a single multiplication operation by the MAC 100.
- a MAC may receive signed binary values as operands.
- a two's complement notation may be used.
- the most significant bit of the value may represent the sign: zero for positive values, one for negative values.
- the 16-bit operand FFClh may represent -63d and the operand 003Fh may represent +63d.
- 16-bit values may be represented as 32-bit values, for some applications.
- the sign bit (bit fifteen) may thus be "extended” or duplicated in the upper sixteen bits.
- the sign-extended operand FFFFFFClh may thus again represent -63d while the operand 0000003 Fh may represent +63d.
- the upper seventeen bits of both operands are identical, as the sign bit (bit fifteen) is extended. Likewise, for either value, the upper sixteen bits are not needed to perform a multiplication operation.
- the early termination logic 50 uses this feature of signed binary values to the advantage of the MAC 100.
- the early termination logic 50 receives a signal from the multiplier B.
- the early termination logic 50 may be invoked when the upper seventeen bits of a 32-bit multiplier B are identical. In such a case, the upper sixteen bits of the multiplier B are not used in the multiplication operation.
- the early termination logic 50 sends a signal to the MAC control logic 52.
- the MAC control logic 52 controls the flip-flops 6, the MUXs 8, and the MUXs and flip- flops 24, as well as the accumulators 32.
- the MAC control logic 52 thus may enable the next multiplicand A to be latched by the flip-flops 6a and the MUXs 8a, the next multiplier B to be latched by the flip-flops 6b and the MUXs 8b, or the next accumulate data C to be latched by the flip-flops 6c and the MUXs 8c.
- the MAC control logic 52 may control the routing of the intermediate sum vector 22a and the intermediate carry vector 22b, received from the Wallace tree 30.
- the MAC control logic 52 may enable the MUXs and flip-flops 24a, the MUXs and flip- flops 24b, and the MUXs 8d, as needed.
- the MAC control logic 52 further controls the accumulator A register 32a and the accumulator B register 32b, permitting the values contained therein to be routed back to the Wallace tree 20 as accumulate input 18. Finally, the MAC control logic 52 may control the MUXs 8e such that the final output vector 34 may be sign-extended, if desired, and produce the output value 40.
- the MAC control unit 52 may receive control signals from a source external to the MAC 100, such as an instruction decoder (not shown). The MAC control unit 52 may also submit control signals to another source external to the MAC 100. Depending upon the operation being performed, the MAC 100 may produce intermediate vector values.
- the Booth encoder 10 receives a 16-bit value from the multiplier, B. Accordingly, to multiply two 32- bit numbers, or a 16-bit multiplicand and a 32-bit multiplier, the Booth encoder 10 may receive the lower sixteen bits of the multiplier in a first cycle and then receive the upper sixteen bits of the multiplier in a second cycle.
- the other circuitry of the MAC 100 may receive data in both a first and a second cycle.
- the multiplication operation thus takes, at a minimum, two cycles to complete.
- the MAC 100 may achieve single-cycle throughput.
- the MAC 100 achieves single-cycle throughput in performing 16-bit multiplication operations.
- the Wallace tree 66 and the CLA 68 may simultaneously process all subsequent operands.
- the Wallace tree 66 may be processing data for cycle n, while, at the same time, the CLA 68 is processing data for cycle n-1.
- FIG. 2 A a flow diagram illustrates how the MAC 100 logic processes a multiply or multiply/accumulate operation.
- two 16-bit operands are sign-extended as 32-bit values.
- Such operands are common in DSP applications and may particularly illustrate performance of the early termination logic 50 in the MAC 100.
- the MAC 100 may perform multiply or multiply/accumulate operations on operands with other characteristics.
- a first cycle, cycle 0, begins (block 200).
- the lower sixteen bits of the multiplier B[15:0] are sent to the Booth encoder 10 (block 202).
- the MUX array 14 receives eight control signals 12 from the Booth encoder 10 as well as the multiplicand A[31 :0] (block 204).
- the MUX array 14 processes these signals such that the Wallace tree 20 receives eight partial product vectors 16 from the MUX array 14.
- the Wallace tree 20 receives accumulate data C[31 :0] (block 206). From this data, the Wallace tree 20 produces an intermediate sum vector (ISV) 22a and an intermediate carry vector (ICV) 22b (block 208).
- the intermediate sum vector 22a and the intermediate carry vector 22b are sent to the MUXs and flip-flops 24a and 24b (block 210).
- the early termination logic 50 may receive the 32-bit multiplier B[31 :0] (block 212). Because the operands are sign-extended 16-bit values, the upper seventeen bits of the multiplier B are identical. Accordingly, the early termination logic 50 sends a signal to the MAC control logic 52 (block 214). The MAC control logic 52 then sends a signal to latch the flip-flops 6a, 6b and 6c as well as the MUXs 8a, 8b and 8c (block 216). In this manner, the MAC control logic 52 enables the circuitry to latch the next MAC operands A, B and C.
- the second cycle, cycle one is a continuation of the operations of Figure 2A.
- the MAC control logic 52 sends a signal to the MUXs 8d to release the intermediate sum vector 22a and the intermediate carry vector 22b (block 232).
- the intermediate sum vector 22a and the intermediate carry vector 22b are sent to the CLA 30 (block 234).
- the CLA 30 adds the intermediate sum vector 22a and the intermediate carry vector 22b together (block 236).
- the result 40 is then sent out of the MAC 100 (block 238).
- cycle one is completed.
- FIG 3 the single-cycle throughput of 16-bit multiplication operations using the MAC 100 according to one embodiment of the invention may be demonstrated using a chart.
- a chart At the top of the chart, a numbered series of 16-bit multiplication operations performed by the MAC 100 is depicted.
- the cycle in which an operation was performed is specified.
- the chart tracks operations performed by the Wallace tree 20, indicated as "W”, and the CLA 30, indicated as "C” according to one embodiment of the invention.
- the Wallace tree 20 For the first 16-bit multiplication operation, the Wallace tree 20 is executed in cycle zero while the CLA 30 is executed in cycle one.
- the Wallace tree 20 For the second 16-bit multiplication operation, the Wallace tree 20 is executed in cycle one and the CLA 30 is executed in cycle two.
- the execution of the CLA 30 for the first multiplication operation occurs simultaneously with the execution of the Wallace tree 20 for the second 16-bit multiplication operation.
- the subsequent 16-bit multiplication operations proceed like the two already described.
- fifteen 16-bit multiplication operations At the end of the fifteenth cycle, fifteen 16-bit multiplication operations have been completed.
- the MAC 100 thus provides a single-cycle throughput.
- the accumulators 32 allow the MAC 100 to perform implicit multiply and multiply/accumulate operations.
- the MAC 100 may include a single accumulator.
- the accumulators 32 may be implicitly referenced by several implicit instructions. Those implicit multiply/accumulate instructions reference the accumulators 32 instead of a register-specified accumulator.
- MAR or MRA may be received by the MAC control logic 52 in order for the accumulators 32 to be read from or written to, respectively.
- Figure 4A a flow diagram illustrates the implicit multiply/accumulate operation in which early termination is invoked. Recall that, in order for early termination to be invoked, the other seventeen bits of the multiplier B are all zeros or all ones.
- cycle zero begins (block 300)
- the multiplier B[15:0] is sent to the Booth encoder 10 (block 302).
- the MUX array 14 then receives eight control signals 12 from the Booth encoder 10 as well as the multiplicand A[31 :0] (block 304).
- the Wallace tree 20 receives eight partial product vectors from the MUX array 14. Additionally, the Wallace tree 20 receives an accumulate value from either accumulator A 32a or accumulator B 32b (block 306). The Wallace tree 20 subsequently produces an intermediate sum vector 22a and an intermediate carry vector 22b (block 308).
- the carry look-ahead adder 30 is a 40-bit CLA, which may perform 16-bit DSP operations.
- the accumulator A register 32a and the accumulator B register 32b are 40-bit registers.
- the entire 32-bit multiplier B is sent to the early termination logic (ETL) 50 (block 312). Because the upper seventeen bits of the multiplier B are identical, the early termination logic 50 sends a signal to the MAC control logic 52 (block 312).
- the MAC control logic 52 then sends a signal to latch the flip-flops 6a, 6b, and 6c as well as the MUXs 8a, 8b, and 8c (block 316). This indicates that the Wallace tree 20 will be available to accept the next implicit multiply/accumulate instruction in the next cycle (block 316).
- cycle 1 begins (block 330).
- the MAC control logic 52 sends a signal to the MUXs 8d to release the intermediate sum vector 22a and the intermediate carry vector
- the MAC 100 may receive implicit instructions which reference the accumulators. These instructions may be received from the MAC control logic 52, which ultimately controls the accumulator A 32a and the accumulator B 32b.
- the MAC control logic 52 may receive an implicit instruction for reading the accumulator A 32a (block 350).
- the values stored in the accumulator A 32a and the accumulator B 32b are sent to the CLA 30 (block 352).
- the CLA 30 then adds the values 36a and 36b together (block 354).
- the CLA 30 then sends the result 40 as output data (block 356).
- the result 40 may then be sent to a register file external to the MAC 100.
- a multiply with implicit accumulate operation uses packed data instructions.
- the MAC 100 may receive four different packed data instructions. These four packed data instructions operate on sixteen bits or half of two 32-bit operands. For example, one instruction may operate on the lower sixteen bits of both the multiplier B and the multiplicand A. Another may operate on the upper sixteen bits of the multiplicand A and the lower sixteen bits of the multiplier B. Ultimately, each packed- data instruction thus performs a 16-bit multiply operation on two 16-bit operands.
- a 32-bit multiplicand A[31 :0] and a 32-bit multiplier B[31 :0] are sent to the MAC 100 (block 402).
- the MAC control logic 52 also receives a packed-data instruction (block 404).
- Sixteen bits of the multiplicand A are extended to 32 bits. For example, if the packed- data instruction is operating on the lower sixteen bits of the multiplicand A, then the upper sixteen bits of the multiplicand A are replaced with the contents of the 16th bit of the multiplicand A. In essence, the sign is extended from the 16th to the 32nd bit. Likewise, if the packed-data instruction is operating on the upper sixteen bits of the multiplicand A, then the upper sixteen bits are shifted to the lower 16 bits and the upper sixteen bits are filled with the value of the sign bit. Sixteen bits of the multiplier B are sent to the Booth encoder 10 (block 408).
- the MAC 100 is simultaneously determining whether the early termination logic 50 will be invoked. That is, the multiplier B[31 :0] is sent to the early termination logic 50 (block 420). Because the upper seventeen bits of the multiplier B are identical, the early termination logic 50 sends a signal to the MAC control logic 52 (block 422). The MAC control logic 52 then sends a signal to latch the flip-flops 6a, 6b, and 6c as well as the MUXs 8a, 8b and 8c (block 424). This allows a new MAC instruction to be processed in the next cycle (block 426).
- a multiply-accumulate unit may provide single-cycle throughput for certain operations.
- the MAC avoids using redundant hardware, which may consume additional power, and includes no pipelining circuitry, which may run more slowly. Instead, the Wallace tree and the carry look-ahead adder which are part of the MAC may simultaneously operate. Where such simultaneous operations occur, a higher throughput may be possible.
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2001549181A JP3869269B2 (en) | 1999-12-23 | 2000-12-04 | Handling multiply accumulate operations in a single cycle |
AU20594/01A AU2059401A (en) | 1999-12-23 | 2000-12-04 | Processing multiply-accumulate operations in a single cycle |
GB0208937A GB2371657B (en) | 1999-12-23 | 2000-12-04 | Processing multiply-accumulate operations in a single cycle |
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US09/470,836 US6611856B1 (en) | 1999-12-23 | 1999-12-23 | Processing multiply-accumulate operations in a single cycle |
US09/470,836 | 1999-12-23 |
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WO2001048595A1 true WO2001048595A1 (en) | 2001-07-05 |
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PCT/US2000/032887 WO2001048595A1 (en) | 1999-12-23 | 2000-12-04 | Processing multiply-accumulate operations in a single cycle |
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US (2) | US6611856B1 (en) |
JP (1) | JP3869269B2 (en) |
KR (1) | KR100470299B1 (en) |
CN (1) | CN1230735C (en) |
AU (1) | AU2059401A (en) |
GB (1) | GB2371657B (en) |
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WO (1) | WO2001048595A1 (en) |
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Also Published As
Publication number | Publication date |
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GB0208937D0 (en) | 2002-05-29 |
JP2003518690A (en) | 2003-06-10 |
GB2371657A (en) | 2002-07-31 |
US6611856B1 (en) | 2003-08-26 |
CN1230735C (en) | 2005-12-07 |
JP3869269B2 (en) | 2007-01-17 |
GB2371657B (en) | 2004-09-15 |
KR20030011063A (en) | 2003-02-06 |
CN1402843A (en) | 2003-03-12 |
AU2059401A (en) | 2001-07-09 |
US20030172101A1 (en) | 2003-09-11 |
KR100470299B1 (en) | 2005-02-05 |
TW588281B (en) | 2004-05-21 |
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