WO2001050679A3 - Method and apparatus for gigabit packet assignment for multithreaded packet processing - Google Patents

Method and apparatus for gigabit packet assignment for multithreaded packet processing Download PDF

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Publication number
WO2001050679A3
WO2001050679A3 PCT/US2000/033405 US0033405W WO0150679A3 WO 2001050679 A3 WO2001050679 A3 WO 2001050679A3 US 0033405 W US0033405 W US 0033405W WO 0150679 A3 WO0150679 A3 WO 0150679A3
Authority
WO
WIPO (PCT)
Prior art keywords
packet
segment
assigned
threads
program
Prior art date
Application number
PCT/US2000/033405
Other languages
French (fr)
Other versions
WO2001050679A2 (en
Inventor
Gilbert Wolrich
Debra Bernstein
Matthew J Adiletta
Donald F Hooper
Original Assignee
Intel Corp
Gilbert Wolrich
Debra Bernstein
Matthew J Adiletta
Donald F Hooper
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Gilbert Wolrich, Debra Bernstein, Matthew J Adiletta, Donald F Hooper filed Critical Intel Corp
Priority to AU20786/01A priority Critical patent/AU2078601A/en
Priority to EP00984108.1A priority patent/EP1245097B1/en
Publication of WO2001050679A2 publication Critical patent/WO2001050679A2/en
Publication of WO2001050679A3 publication Critical patent/WO2001050679A3/en
Priority to HK02108425.6A priority patent/HK1047006A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/102—Packet switching elements characterised by the switching fabric construction using shared medium, e.g. bus or ring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H04L49/352—Gigabit ethernet switching [GBPS]

Abstract

A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads - one for header segment processing and the other for handling payload segment(s) - or a different program thread for segment of data in a packet. Dedicated inputs for ready status and sequence numbers provide assistance needed for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.
PCT/US2000/033405 1999-12-29 2000-12-07 Method and apparatus for gigabit packet assignment for multithreaded packet processing WO2001050679A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU20786/01A AU2078601A (en) 1999-12-29 2000-12-07 Method and apparatus for gigabit packet assignment for multithreaded packet processing
EP00984108.1A EP1245097B1 (en) 1999-12-29 2000-12-07 Method and article for packet scheduling for multithreaded packet processing
HK02108425.6A HK1047006A1 (en) 1999-12-29 2002-11-21 Method and article for packet scheduling for multithreaded packet processing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/474,650 US6661794B1 (en) 1999-12-29 1999-12-29 Method and apparatus for gigabit packet assignment for multithreaded packet processing
US09/474,650 1999-12-29

Publications (2)

Publication Number Publication Date
WO2001050679A2 WO2001050679A2 (en) 2001-07-12
WO2001050679A3 true WO2001050679A3 (en) 2002-01-17

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/033405 WO2001050679A2 (en) 1999-12-29 2000-12-07 Method and apparatus for gigabit packet assignment for multithreaded packet processing

Country Status (7)

Country Link
US (3) US6661794B1 (en)
EP (1) EP1245097B1 (en)
CN (1) CN1191698C (en)
AU (1) AU2078601A (en)
HK (1) HK1047006A1 (en)
TW (1) TW538609B (en)
WO (1) WO2001050679A2 (en)

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