WO2001053933A3 - Dram embedded coprocessor - Google Patents

Dram embedded coprocessor Download PDF

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Publication number
WO2001053933A3
WO2001053933A3 PCT/US2001/001594 US0101594W WO0153933A3 WO 2001053933 A3 WO2001053933 A3 WO 2001053933A3 US 0101594 W US0101594 W US 0101594W WO 0153933 A3 WO0153933 A3 WO 0153933A3
Authority
WO
WIPO (PCT)
Prior art keywords
dram
embedded
processor
cpu core
vliw
Prior art date
Application number
PCT/US2001/001594
Other languages
French (fr)
Other versions
WO2001053933A2 (en
Inventor
Eric M Dowling
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to AU2001229574A priority Critical patent/AU2001229574A1/en
Publication of WO2001053933A2 publication Critical patent/WO2001053933A2/en
Publication of WO2001053933A3 publication Critical patent/WO2001053933A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor

Abstract

A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks. In different embodiments, standard software can be accelerated either with or without the express knowledge of the processor.
PCT/US2001/001594 2000-01-19 2001-01-17 Dram embedded coprocessor WO2001053933A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001229574A AU2001229574A1 (en) 2000-01-19 2001-01-17 Split embedded dram processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/487,639 2000-01-19
US09/487,639 US6226738B1 (en) 1997-08-01 2000-01-19 Split embedded DRAM processor

Publications (2)

Publication Number Publication Date
WO2001053933A2 WO2001053933A2 (en) 2001-07-26
WO2001053933A3 true WO2001053933A3 (en) 2002-03-21

Family

ID=23936550

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/001594 WO2001053933A2 (en) 2000-01-19 2001-01-17 Dram embedded coprocessor

Country Status (3)

Country Link
US (1) US6226738B1 (en)
AU (1) AU2001229574A1 (en)
WO (1) WO2001053933A2 (en)

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Publication number Publication date
US6226738B1 (en) 2001-05-01
AU2001229574A1 (en) 2001-07-31
WO2001053933A2 (en) 2001-07-26

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