WO2001065757A3 - An atm switch - Google Patents

An atm switch Download PDF

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Publication number
WO2001065757A3
WO2001065757A3 PCT/IN2000/000048 IN0000048W WO0165757A3 WO 2001065757 A3 WO2001065757 A3 WO 2001065757A3 IN 0000048 W IN0000048 W IN 0000048W WO 0165757 A3 WO0165757 A3 WO 0165757A3
Authority
WO
WIPO (PCT)
Prior art keywords
cell
input
queue
shared
buffer
Prior art date
Application number
PCT/IN2000/000048
Other languages
French (fr)
Other versions
WO2001065757A2 (en
Inventor
Muthusamy Kamaraj
Mariamma Joselin
Kalyanaraman Pattabhiraman
Satish Manohar Kulkarni
Philip Jain
Jayant Bhatnagar
Pradeep Kumar Bhatnagar
Kailash Narain Gupta
Adde Palli Gopinat Dixit
Original Assignee
Centre For Development Of Telematics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to IL15150900A priority Critical patent/IL151509A0/en
Application filed by Centre For Development Of Telematics filed Critical Centre For Development Of Telematics
Priority to AU58442/00A priority patent/AU5844200A/en
Publication of WO2001065757A2 publication Critical patent/WO2001065757A2/en
Publication of WO2001065757A3 publication Critical patent/WO2001065757A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/108—ATM switching elements using shared central buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H04L49/309—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/45—Arrangements for providing or supporting expansion
    • H04L49/455—Provisions for supporting expansion in ATM switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/60—Software-defined switches
    • H04L49/606—Hybrid ATM switches, e.g. ATM&STM, ATM&Frame Relay or ATM&IP
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651—Priority, marking, classes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

An ATM switch having a plurality of input-ports and a plurality of output ports allowing a plurality of priority levels, which is highly modular allowing expansion of the number of cell buffers in a shared buffer pool (4), thus efficiently handling bursty traffic of one-to-one and one-to-many destination ports, using the bit slicing concept to reduce the operating speed of the switch, and decrease the cell buffer size requirement per slice along with reducing the number of shared queue memories per slice, aiding cost effective and efficient, very large scale integration (VLSI) implementation. It also allows configurability of input link speeds, taking care of the order of cell delivery to the output ports. The switch on receiving the input cell, searches for a free buffer in the shared pool, then routes the cell into this buffer and indexes the pointer into an output queue called the queue management module (5) which uses a shared pool of queue memories. The buffers are then read out in the order of priority and sequence of arrival at the input, by this queue management module. It provides initialization, control, and status monitoring features too, through a processor interface module (7).
PCT/IN2000/000048 2000-02-29 2000-04-27 An atm switch WO2001065757A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IL15150900A IL151509A0 (en) 2000-02-29 2000-03-27 An atm switch
AU58442/00A AU5844200A (en) 2000-02-29 2000-04-27 An atm switch

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
IN176/DEL/2000 2000-02-29
IN176DE2000 2000-02-29
US09/519,072 US6501757B1 (en) 2000-02-29 2000-03-06 ATM switch

Publications (2)

Publication Number Publication Date
WO2001065757A2 WO2001065757A2 (en) 2001-09-07
WO2001065757A3 true WO2001065757A3 (en) 2009-09-03

Family

ID=26324878

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IN2000/000048 WO2001065757A2 (en) 2000-02-29 2000-04-27 An atm switch

Country Status (4)

Country Link
US (1) US6501757B1 (en)
AU (1) AU5844200A (en)
IL (1) IL151509A0 (en)
WO (1) WO2001065757A2 (en)

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US6717951B2 (en) * 1999-12-29 2004-04-06 Intel Corporation Method and apparatus for determining priority of network packets
FI108691B (en) * 2000-02-01 2002-02-28 Nokia Corp Autoconfiguration of the control connections in a switchboard
US6591285B1 (en) * 2000-06-16 2003-07-08 Shuo-Yen Robert Li Running-sum adder networks determined by recursive construction of multi-stage networks
EP1168710B1 (en) * 2000-06-19 2005-11-23 Broadcom Corporation Method and device for frame forwarding in a switch fabric
US6985486B1 (en) * 2000-07-14 2006-01-10 Intel Corporation Shared buffer asynchronous transfer mode switch
US7007071B1 (en) 2000-07-24 2006-02-28 Mosaid Technologies, Inc. Method and apparatus for reducing pool starvation in a shared memory switch
JP4290320B2 (en) * 2000-09-28 2009-07-01 富士通株式会社 Routing device
US7072300B1 (en) * 2001-03-23 2006-07-04 Advanced Micro Devices, Inc. Action tag generation within a network based on priority or differential services information
US6950887B2 (en) * 2001-05-04 2005-09-27 Intel Corporation Method and apparatus for gathering queue performance data
US6956824B2 (en) * 2001-06-14 2005-10-18 Tropic Networks Inc. Extension of link aggregation protocols over the network
US6970454B1 (en) * 2001-08-09 2005-11-29 Pasternak Solutions Llc Sliced crossbar architecture with inter-slice communication
US7362751B2 (en) * 2001-10-03 2008-04-22 Topside Research, Llc Variable length switch fabric
US20040008697A1 (en) * 2002-05-15 2004-01-15 Xyratex Technology Limited Method and apparatus for enabling filtering of data packets
US20040066791A1 (en) * 2002-10-02 2004-04-08 Jingshown Wu Asynchronous expansible switching system for switching packet with different length
DE60331847D1 (en) * 2002-10-18 2010-05-06 Broadcom Corp SYSTEM AND METHOD FOR RECEPTION SERVICE TIMING PROVISIONING
US8225389B2 (en) * 2003-04-11 2012-07-17 Broadcom Corporation Method and system to provide physical port security in a digital communication system
JP5089167B2 (en) * 2003-04-22 2012-12-05 アギア システムズ インコーポレーテッド Method and apparatus for shared multi-bank memory
US7185153B2 (en) * 2003-12-18 2007-02-27 Intel Corporation Packet assembly
US20060153248A1 (en) * 2004-12-23 2006-07-13 Michael Rytting Counter proxy
KR100812225B1 (en) * 2005-12-07 2008-03-13 한국전자통신연구원 Crossbar switch architecture for multi-processor SoC platform
CN100586036C (en) * 2006-05-11 2010-01-27 华为技术有限公司 Low-step crossing device and main-equipment protection for scheduling SDH low-step virtual container
US8665892B2 (en) * 2006-05-30 2014-03-04 Broadcom Corporation Method and system for adaptive queue and buffer control based on monitoring in a packet network switch
US20070280224A1 (en) * 2006-06-05 2007-12-06 Via Technologies System and method for an output independent crossbar
KR20090081685A (en) * 2008-01-24 2009-07-29 삼성전자주식회사 Apparatus for recording images and method thereof
US8566487B2 (en) * 2008-06-24 2013-10-22 Hartvig Ekner System and method for creating a scalable monolithic packet processing engine
US9154441B2 (en) * 2013-01-25 2015-10-06 Broadcom Corporation Adaptive buffer allocation management
CN103955436B (en) * 2014-04-30 2018-01-16 华为技术有限公司 A kind of data processing equipment and terminal
US10089255B2 (en) * 2015-07-24 2018-10-02 SK Hynix Inc. High performance host queue monitor for PCIE SSD controller
US11575616B2 (en) * 2021-04-26 2023-02-07 Realtek Singapore Pte Ltd. Packet forwarding device and queue management method

Citations (5)

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US5583858A (en) * 1993-09-30 1996-12-10 Fujitsu Limited Asynchronous transfer mode switching device
US6009078A (en) * 1996-02-09 1999-12-28 Nec Corporation ATM switch device capable of favorably controlling traffic congestion
US6101190A (en) * 1995-12-26 2000-08-08 Samsung Electronics Co., Ltd. Switching system and method for asynchronous transfer mode exchange for multimedia service
US6163528A (en) * 1997-11-12 2000-12-19 Nec Corporation Selective cell discard system in ATM switch
US6426940B1 (en) * 1997-06-30 2002-07-30 Samsung Electronics, Co. Ltd. Large scaled fault tolerant ATM switch and a self-routing method in a 2N×N multiplexing switch

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GB9019340D0 (en) 1990-09-05 1990-10-17 Plessey Telecomm An asynchronous transfer mode switching arrangement providing broadcast transmission
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US5583858A (en) * 1993-09-30 1996-12-10 Fujitsu Limited Asynchronous transfer mode switching device
US6101190A (en) * 1995-12-26 2000-08-08 Samsung Electronics Co., Ltd. Switching system and method for asynchronous transfer mode exchange for multimedia service
US6009078A (en) * 1996-02-09 1999-12-28 Nec Corporation ATM switch device capable of favorably controlling traffic congestion
US6426940B1 (en) * 1997-06-30 2002-07-30 Samsung Electronics, Co. Ltd. Large scaled fault tolerant ATM switch and a self-routing method in a 2N×N multiplexing switch
US6163528A (en) * 1997-11-12 2000-12-19 Nec Corporation Selective cell discard system in ATM switch

Also Published As

Publication number Publication date
AU5844200A (en) 2001-09-12
US6501757B1 (en) 2002-12-31
IL151509A0 (en) 2003-04-10
WO2001065757A2 (en) 2001-09-07

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