WO2001075941A2 - A low cost half bridge driver integrated circuit - Google Patents
A low cost half bridge driver integrated circuit Download PDFInfo
- Publication number
- WO2001075941A2 WO2001075941A2 PCT/EP2001/003561 EP0103561W WO0175941A2 WO 2001075941 A2 WO2001075941 A2 WO 2001075941A2 EP 0103561 W EP0103561 W EP 0103561W WO 0175941 A2 WO0175941 A2 WO 0175941A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- transistor
- integrated circuit
- half bridge
- voltage
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
Definitions
- the invention relates to half bridge driver integrated circuits. More particularly, this invention relates to the preparation of a high voltage half bridge integrated circuit with level shifting input control where all complementary metal oxide semiconductor (CMOS) components have been replaced with N- and P-channel double diffused metal oxide semiconductor (DMOS) components.
- CMOS complementary metal oxide semiconductor
- DMOS double diffused metal oxide semiconductor
- a high voltage, half bridge integrated circuit (IC) with level shifting input control serves a very important function that is used ubiquitously in many areas of power and control electronics. Presently this function is integrated using full mask silicon on insulator (SOI) technology that requires numerous masking steps to implement.
- the half bridge driver IC 1 further comprises a circuit 2 used for generating two square wave signals to control the timing of conduction time to power switches 11, 12.
- This circuit 2 is called a "non-overlap" circuit since signals from circuit 2 conducted to power switches 11, 12 are controlled so that the switches 11, 12 do not “overlap,” that is they are not switching on at the same time.
- the dead time between the two signals avoids any cross conduction of the two power switches 11, 12 and prevents the simultaneous switching on of both these power switches 11, 12.
- the half bridge driver IC 1 further comprises two high voltage level shifter
- each of these level shifter transistors 5 being connected with a distinct current source 4.
- Each of the distinct current sources 4 receives separate Ion and Ioff voltage pulses from a circuit 3, called the pulse generator circuit, which is used to generate short voltage pulses.
- the pulse generator circuit 3 generates two short pulses to control the on time switch of the current sources 4. Short pulses instead of long ones are used in order to reduce the level shifting power dissipation. Pulses from the pulse generator circuit 3 are sent to two current sources 4, which are switched on or off according to the input pulse.
- transistors 5 may have ranges of up to a few hundred Volt and are used to communicate between the ground reference level and high voltage reference level, e.g., 500 Volt. These transistors 5 may sustain high voltage across their drain and source. Other devices such as regular CMOS or DMOS are not able to handle such high voltage.
- a pulse filter circuit 6 receives short current pulses initiated by current sources 4 and passed by the level shifter transistors 5. In its turn the pulse filter circuit 6 generates two voltage levels to activate a latch or flip flop 7 which, according to its received input signals, sends an on or off output signal to switch the high power switch 11 on and off even in the presence of a large common mode current arising from dv/dt coupling.
- a high side driver 8 is positioned between the latch 7 and the power switch 11 to drive the top power switch 11.
- a voltage step up circuit 13 is positioned to receive and to translate the square wave signal from the non-overlap circuit 2 to the low side driver circuit 9, which will drive the low power switch 12.
- the high side and low side drivers 8, 9 provide sufficient driving power capabilities for the half bridge power switches 11, 12, which may be integrated in the half bridge driver IC 1, to turn on or off the half bridge power switches 11, 12, which provide the high voltage square wave to its load as may be specified.
- the half bridge driver IC 1 further comprises a bootstrap diode 16 that is connected on a one side to a bootstrap capacitor 10, which in turn is connected to the pulse filter 6, the latch 7, the high driver 8, and in between the high transistor 11 and the low transistor 12.
- the bootstrap diode 16 is connected to the low supply generator 14 for supplying voltage to the non-overlap circuit 2, the pulse generator circuit 3, and the step-up circuit 13.
- low voltage circuits such as the non-overlap circuit 2, the pulse generator circuit 3, and the current sources 4 use a low threshold complementary MOS (CMOS) with a typical 1 Volt threshold.
- CMOS complementary MOS
- DMOS components allow for higher supply of voltage, i.e., 12 Volt, to sufficiently drive the half bridge power switches 11, 12.
- the non-overlap circuit 2 and the pulse generator circuit 3 are implemented with the low supply generator 14 supplying voltage, e.g., 5 Volt, whereas circuits such as the pulse filter 6, the latch 7, the low side driver 9 and the high side driver 8 are implemented with higher supply voltages, e.g., 12 Volt.
- a supply generator 14 is required to provide low supply, i.e., 5 Volt, from a higher supply, e.g., 12 Volt.
- the voltage step up circuit 13 is required to translate signals from the non-overlap circuit 2 to the low side driver circuit 9. Those voltage supply differences make the design and the manufacture of such a circuit complicated, require larger area consumption by the IC, and make the circuit expensive to manufacture.
- High threshold voltage P-channel DMOS transistors 20 are used in the manufacture of the pulse filter 6.
- the DMOS FET has a threshold voltage of 3.5 Volt for an N-channel and -5 Volt for a P-channel.
- the threshold voltage drop of the transistor 20 is required to be applied across one of the two resistors 21 connected to the gate of the DMOS transistor 20.
- the DMOS will not conduct. Therefore a voltage cannot be created across resistor 22 to turn on one of the inputs to the latch 7.
- the latch 7 will not provide the correct output and therefore will not work in the right state.
- low resistance is desired of the both resistors 21 of the pulse filter 6 to maintain low voltage drop crossing them in the presence of a large common mode level shifting current arising from dv/dt coupling.
- high resistance is desired in order to utilize the low differential level shifting current to save power dissipation.
- the present invention introduces a low cost half bridge driver IC that overcomes the drawbacks of the prior art.
- this invention introduces a half bridge driver IC, which is fabricated in the process technology with a minimum or reduced number of masking steps to implement all the blocks and without the use of the low threshold voltage CMOS.
- the inventive half bridge driver IC uses a universal 12 Volt supply for all the blocks with reference to the ground or to the half bridge output.
- the low differential current from high voltage level shifter transistors of the inventive half bridge driver IC can provide enough voltage swing to set or reset the latch when high threshold voltage DMOS are used in the pulse filter.
- Figure 1 is a function block diagram of a half bridge driver integrated circuit of the prior art.
- Figure 2 is a function block diagram of a pulse filter circuit of the prior art.
- Figure 3 is a function block diagram of a half bridge driver IC with the capability of using a high threshold voltage DMOS of the present invention.
- Figure 4 is a function block diagram of a pulse filter circuit to be included in the half bridge driver IC of Figure 3.
- Figure 5 is a function block diagram of a non-overlap circuit to be included in the half bridge driver IC of Figure 3.
- Figure 6 is a function block diagram of a pulse generator circuit to be included in the half bridge driver IC of Figure 3.
- FIG. 3 shows the inventive half bridge driver IC 1', wherein a high voltage device structure is fabricated in a thin SOI device layer and elements similar to those of Figure 1 are identified by like numerals with the addition of a prime mark.
- the inventive half bridge driver IC 1 ' allows for higher yield and smaller silicon print area in addition to 30% savings in cost previously achieved in manufacturing of half bridge drivers.
- the fabrication or construction of such device structure is described in U.S. Patents Nos. 5,246,870 and 5,300,448, the entire contents of which are incorporated herewith by reference.
- the half bridge driver IC 1' of the present invention comprises two, i.e., high and low, transistors 11 ', 12', a non-overlap circuit 32 to generate two square wave signals to control the timing of conduction time to avoid switching on of both power switches 11', 12' at the same time.
- the non-overlap circuit 32 is connected to the low side driver circuit 9', which is driving the low power switch 12'.
- the non-overlap circuit 32 is further connected to a pulse generator circuit 33, which generates two pulses to control the on time switch of the current sources 4'.
- Each of the current sources 4' is connected to one of voltage level shifter transistors 5', both of which connect to the pulse filter 6'.
- the pulse filter circuit 6' connects to the latch 7', which is connected to the high side driver 8'.
- the high side driver 8' drives the high power switch 11 ' on and off.
- the inventive half bridge driver IC 1' further comprises a bootstrap diode 16' that is connected on a one side to a bootstrap capacitor 10', which in turn is connected to the pulse filter 6', the latch 7', the high driver 8', and in between the high transistor 11' and the low transistor 12'.
- the bootstrap diode 16' is connected to the non- overlap circuit 32 and the pulse generator circuit 33.
- the diode 16' high side supply to the pulse filter 6', the latch 7', and the high driver 8' is 12 Volt to 0.7 Volt, i.e., diode drop, while the supply for the non-overlap circuit 32, the pulse generator circuit 33, and the low side driver circuit 9' is 12 Volt.
- the half bridge IC 1 ' of the present invention is manufactured entirely without the formation of the CMOS components, e.g., a non-overlap circuit 32 and a pulse generator circuit 33 are formed entirely of the DMOS. Furthermore, a minimum number of masking steps is used in the formation of the inventive half bridge IC 1', due to the fact that no CMOS components need be formed. That is because the devices of the inventive half bridge IC 1 ' are all the high threshold voltage DMOS devices capable of being biased at high voltage, i.e., up to a few hundred Volt.
- the half bridge IC 1 ' of the present invention uses a 12 Volt supply V DD 30 for all of the circuits including the non-overlap circuit 32 and a pulse generator circuit 33, thereby eliminating the need for the low supply generator 14 ( Figure 1) and the step up circuit 13 ( Figure 1). Furthermore, the supply V DD 30 with reference to half bridge output is provided through the bootstrap diode 16' and the capacitor 10' to the floating circuits, such as the pulse filter 6', the latch 7' and the high side driver 8'.
- the cross coupled P- channel DMOS 40 are used in parallel with resistors 21'. This is done to reduce the necessary differential level shifting current by making resistors 21 ' larger. It may also increase the voltage swing for one of the two inputs to the latch 7' by reducing the effective resistance, since the DMOS impedance parallels the resistor 21'.
- the P-channel transistor 20 ( Figure 2) in the pulse filter block 6 ( Figure 2) is required to operate with a high voltage source, e.g., 500 Volt.
- a transistor with a regular threshold, e.g., 1 Volt is preferably used with the type of pulse filter circuit shown in Figure 2.
- P-channel DMOS with high threshold voltage e.g., 5 Volt
- the voltage across each of the resistors 21' has to be larger than the DMOS threshold, e.g., 5 Volt, as compared to the regular threshold, e.g., 1 Volt.
- the regular threshold e.g. 1 Volt.
- One way to solve this discrepancy is to increase the input current sources.
- the invention increases the resistance, thus reducing the required differential input current and power dissipation, while the output signals, i.e., the set or reset, still have enough voltage swings even with the large common mode parasitic current. That was accomplished by adding an extra pair of P-channel DMOS transistors 40 and increasing the resistance of resistors 21'. One of the pair of transistors 40 is open when the voltage threshold across the parallel resistor is required to be larger than 5
- Figure 5 shows one embodiment of the inventive non-overlap circuit 32 used to control the timing of the two power transistor 11', 12' ( Figure 3) conduction time, to avoid both switches being on at the same time.
- non-overlap time e.g., 1.2 uS
- bias current e.g. 12 uA.
- a 6: 1 ratio of channel width may be chosen, to achieve equal rise and fall time in the inverter.
- Each of the transistors 50 of the non-overlap circuit 32 is shown with three terminals, a gate terminal (G), a source terminal (S), and a drain terminal (D).
- the non-overlap circuit 32 comprises 19 transistors 50 and a capacitor 51.
- a block of transistors 50a is interconnected in a manner where S of the P-channel DMOS transistor 50al receives V DD 57 and D of the transistor 50al is connected to S of the P- channel DMOS transistor 50a2.
- D of the transistor 50a2 is connected to D of the N-channel DMOS transistor 50a3 and to D of the N-channel DMOS transistor 50a4.
- S of the transistors 50a3 and 50a4 is grounded.
- a block of transistors 50b is interconnected in a manner where S of the P- channel DMOS transistors 50bl, 50b2 and 50b5 receives V DD 57 and D of the transistor 50bl is connected to D of the transistor 50b2 and D of the N-channel DMOS transistor 50b3.
- S of the transistor 50b3 is connected to D of the N-channel DMOS transistor 50b4 and S of the transistor 50b4 is grounded.
- D of the transistor 50b5 and D of the N-channel DMOS transistor 50b6 are interconnected and their G is connected to D of the transistors 50b2 and 50b3.
- the block of transistors 50d is interconnected in a manner where S of the P- channel DMOS transistors 50dl and 50b2 receive V DD 57, G of transistors 50dl and 50b2 are interconnected and further connected to BIASP 55 to which D of the transistor 50dl is also connected.
- D of the transistor 50d2 is connected to S of the P-channel DMOS transistor 50d3, and D of the transistor 50d3 is connected to D of the N-channel DMOS transistor 50d4.
- S of the transistor 50d4 is connected to D of the N-channel DMOS transistor 50d5, and S of the transistor 50d5 is grounded.
- S of N-channel DMOS transistors 50d6, 50d7 is also grounded, their G and G of the transistor 50d5 are connected to BIASN 54.
- D of the transistor 50d7 is connected to BIASN 54, while D of the transistor 50d6 is connected to BIASP 55.
- G of transistors 50d3, 50d4, 50al, 50a4, and 50b 1, 50b4 receive the clock in 56 signal.
- S of the P-channel DMOS transistor 50c 1 receives V DD 57 and D is connected to D of the N-channel DMOS transistor 50c2 and to G of transistors 50a2, 50a3, 50b2, and 50b3. S of the transistor 50c2 is grounded. G of transistors 50c 1, 50c2 is connected to one terminal of the capacitor 51 and to D of transistors 50d3, 50d4; and the second terminal of the capacitor 51 is grounded.
- the first signal 52 of the non-overlap circuit 32 is sent from the interconnection of D of transistors 50a2, 50a3, and 50a4.
- the second signal 53 is sent from the interconnection of D of transistors 50b5 and 50b6.
- FIG. 6 shows the inventive pulse generator circuit 33.
- a first block of transistors 60a is interconnected in a manner where S of the P-channel DMOS transistors 60al, and 60a5 receives V DD 67, and D of the transistor 60al is connected to S of the WO 01/75941 g PCT/EPOl/03561 transistor 60a2.
- D of the transistor 60a2 is connected to D of the N-channel DMOS transistors 60a3, 60a4 and to G of transistors 60a5 and the N-channel DMOS transistor 60a6.
- D of transistors 60a5, 60a6 are interconnected and send out the IOFF signal 61.
- S of P-channel DMOS transistors 60bl, 60b2 receive V DD 67 , while their D interconnects with D of the N-channel DMOS transistor 60b3, as well as sends out a signal IOFF 62.
- S of the transistor 60b3 connects to D of the N-channel DMOS transistor 60b4, S of that transistor being grounded.
- G of transistors 60a2, 60a3, 60b2, and 60b3 is connected to D of the P-channel DMOS transistor 60c 1 and the N-channel DMOS transistor 60c2.
- S of the transistor 60cl receives V DD 67; S of the transistor 60c2 is grounded.
- G of both transistors 60cl, 60c2 is connected to one end of a capacitor 63, the second end of the capacitor 63 being grounded.
- Transistors 60d are interconnected in a manner in which, S of the P-channel DMOS transistors 60dl and 60d3 receives V DD 67, and D of the transistor 60dl connects G of the P-channel DMOS transistor 60d4, N-channel DMOS transistor 60d5 and to D of the N- channel DMOS transistor 60d2, S of which is grounded. S of the transistor 60d5 interconnects with D of the N-channel DMOS transistor 60d6, which transistor's S is grounded, and G receives BIASLN signal 64. D of the transistor 60d5 is connected to D of the transistor 60d4 and also to the first end of capacitor 63. S of the capacitor 60d4 is connected to D of the transistor 60d3. G of the transistor 60d3 receives the BIASP signal 65. G of 60dl, 60d2, 60al, 60a4, 60b 1, 60b4, receives the "in" signal 66.
- Both circuits 32 ( Figure 5) and 33 are implemented in the N-channel and P-channel DMOS to avoid the use of the CMOS circuitry. However other components in the minimum or reduced number of masking steps process such as lightly doped drain (LDD) devices and bipolar junction transistors may also be used to replace the CMOS. While the invention has been particularly shown and described with respect to illustrative and preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention that should be limited only by the scope of the appended claims.
- LDD lightly doped drain
Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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EP01919408A EP1275134A2 (en) | 2000-04-04 | 2001-03-28 | A low cost half bridge driver integrated circuit---------------- |
JP2001573524A JP2003529992A (en) | 2000-04-04 | 2001-03-28 | Low cost half bridge driver integrated circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/543,017 US6353345B1 (en) | 2000-04-04 | 2000-04-04 | Low cost half bridge driver integrated circuit with capability of using high threshold voltage DMOS |
US09/543,017 | 2000-04-04 |
Publications (2)
Publication Number | Publication Date |
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WO2001075941A2 true WO2001075941A2 (en) | 2001-10-11 |
WO2001075941A3 WO2001075941A3 (en) | 2002-01-24 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/EP2001/003561 WO2001075941A2 (en) | 2000-04-04 | 2001-03-28 | A low cost half bridge driver integrated circuit |
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US (1) | US6353345B1 (en) |
EP (1) | EP1275134A2 (en) |
JP (1) | JP2003529992A (en) |
CN (1) | CN1630929A (en) |
WO (1) | WO2001075941A2 (en) |
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EP0669709B1 (en) * | 1994-02-28 | 1998-11-25 | STMicroelectronics S.r.l. | Output stage especially for integrated amplifiers with externally connected output power devices |
DE69403964T2 (en) * | 1994-09-16 | 1998-01-29 | Sgs Thomson Microelectronics | Control circuit with a level shifter for switching an electronic switch |
US5543740A (en) * | 1995-04-10 | 1996-08-06 | Philips Electronics North America Corporation | Integrated half-bridge driver circuit |
EP0764365A2 (en) * | 1995-04-10 | 1997-03-26 | Koninklijke Philips Electronics N.V. | Level-shifting circuit and high-side driver including such a level-shifting circuit |
JP2896342B2 (en) * | 1995-05-04 | 1999-05-31 | インターナショナル・レクチファイヤー・コーポレーション | Method and circuit for driving a plurality of power transistors in a half-wave bridge configuration and allowing excessive negative oscillation of an output node, and an integrated circuit incorporating the circuit |
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KR100246536B1 (en) * | 1997-08-30 | 2000-03-15 | 정선종 | High voltage driver circuit reducing the transient current |
-
2000
- 2000-04-04 US US09/543,017 patent/US6353345B1/en not_active Expired - Fee Related
-
2001
- 2001-03-28 JP JP2001573524A patent/JP2003529992A/en active Pending
- 2001-03-28 CN CNA018007686A patent/CN1630929A/en active Pending
- 2001-03-28 WO PCT/EP2001/003561 patent/WO2001075941A2/en not_active Application Discontinuation
- 2001-03-28 EP EP01919408A patent/EP1275134A2/en not_active Withdrawn
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EP0397241A1 (en) * | 1989-05-09 | 1990-11-14 | Koninklijke Philips Electronics N.V. | Driver for high voltage half-bridge circuits |
EP0703667A1 (en) * | 1994-09-16 | 1996-03-27 | STMicroelectronics S.r.l. | An integrated control circuit with a level shifter for switching an electronic switch |
US6037720A (en) * | 1998-10-23 | 2000-03-14 | Philips Electronics North America Corporation | Level shifter |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003050956A1 (en) * | 2001-12-11 | 2003-06-19 | Koninklijke Philips Electronics N.V. | High-voltage level shifter via capacitors |
WO2003055072A1 (en) * | 2001-12-21 | 2003-07-03 | Bang & Olufsen Icepower A/S | Half-bridge driver and power conversion system with such driver |
US7323912B2 (en) | 2001-12-21 | 2008-01-29 | Bang & Olufsen Icepower A/S | Half-bridge driver and power conversion system with such driver |
KR100933651B1 (en) | 2001-12-21 | 2009-12-23 | 방 앤드 올루프센 아이스파워 에이/에스 | Half-bridge driver and power conversion system with such driver |
WO2021257724A1 (en) * | 2020-06-19 | 2021-12-23 | Efficient Power Conversion Corporation | DIFFERENTIAL ACTIVATED LATCH FOR GaN BASED LEVEL SHIFTER |
US11496134B2 (en) | 2020-06-19 | 2022-11-08 | Efficient Power Conversion Corporation | Differential activated latch for GaN based level shifter |
Also Published As
Publication number | Publication date |
---|---|
CN1630929A (en) | 2005-06-22 |
US6353345B1 (en) | 2002-03-05 |
JP2003529992A (en) | 2003-10-07 |
EP1275134A2 (en) | 2003-01-15 |
WO2001075941A3 (en) | 2002-01-24 |
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