WO2001084773A3 - Port packet queuing - Google Patents

Port packet queuing Download PDF

Info

Publication number
WO2001084773A3
WO2001084773A3 PCT/CA2001/000567 CA0100567W WO0184773A3 WO 2001084773 A3 WO2001084773 A3 WO 2001084773A3 CA 0100567 W CA0100567 W CA 0100567W WO 0184773 A3 WO0184773 A3 WO 0184773A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
queue
cache row
packet
port
Prior art date
Application number
PCT/CA2001/000567
Other languages
French (fr)
Other versions
WO2001084773A2 (en
Inventor
Richard M Wyatt
Original Assignee
Mosaid Technologies Inc
Richard M Wyatt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc, Richard M Wyatt filed Critical Mosaid Technologies Inc
Priority to CA2407310A priority Critical patent/CA2407310C/en
Priority to AU2001250222A priority patent/AU2001250222A1/en
Priority to GB0224761A priority patent/GB2377065B/en
Priority to DE10196135T priority patent/DE10196135B4/en
Publication of WO2001084773A2 publication Critical patent/WO2001084773A2/en
Publication of WO2001084773A3 publication Critical patent/WO2001084773A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools

Abstract

A port queue includes a first memory portion having a first memory access time and a second memory portion having a second memory access time. The first memory portion includes a cache row. The cache row includes a plurality of queue entries. A packet pointer is enqueued in the port queue by writing the packet pointer in a queue entry in the cache row in the first memory. The cache row is transferred to a packet vector in the second memory. A packet pointer is dequeued from the port queue by reading a queue entry from the packet vector stored in the second memory.
PCT/CA2001/000567 2000-04-27 2001-04-26 Port packet queuing WO2001084773A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CA2407310A CA2407310C (en) 2000-04-27 2001-04-26 Port packet queuing
AU2001250222A AU2001250222A1 (en) 2000-04-27 2001-04-26 Port packet queuing
GB0224761A GB2377065B (en) 2000-04-27 2001-04-26 Port packet queuing
DE10196135T DE10196135B4 (en) 2000-04-27 2001-04-26 Port-packet queuing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/559,190 US7236489B1 (en) 2000-04-27 2000-04-27 Port packet queuing
US09/559,190 2000-04-27

Publications (2)

Publication Number Publication Date
WO2001084773A2 WO2001084773A2 (en) 2001-11-08
WO2001084773A3 true WO2001084773A3 (en) 2002-04-11

Family

ID=24232646

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2001/000567 WO2001084773A2 (en) 2000-04-27 2001-04-26 Port packet queuing

Country Status (7)

Country Link
US (5) US7236489B1 (en)
CN (1) CN1260936C (en)
AU (1) AU2001250222A1 (en)
CA (1) CA2407310C (en)
DE (1) DE10196135B4 (en)
GB (1) GB2377065B (en)
WO (1) WO2001084773A2 (en)

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US7236489B1 (en) * 2000-04-27 2007-06-26 Mosaid Technologies, Inc. Port packet queuing
US7007071B1 (en) 2000-07-24 2006-02-28 Mosaid Technologies, Inc. Method and apparatus for reducing pool starvation in a shared memory switch
US7733888B2 (en) * 2002-06-04 2010-06-08 Alcatel-Lucent Usa Inc. Pointer allocation by prime numbers
US7649882B2 (en) * 2002-07-15 2010-01-19 Alcatel-Lucent Usa Inc. Multicast scheduling and replication in switches
US7457241B2 (en) * 2004-02-05 2008-11-25 International Business Machines Corporation Structure for scheduler pipeline design for hierarchical link sharing
CN100407697C (en) * 2005-01-30 2008-07-30 华为技术有限公司 Organizational scheduling method for multi-mode COS queue and apparatus thereof
CN101656658B (en) * 2008-08-21 2013-03-20 中兴通讯股份有限公司 Method and device for improving dequeuing efficiency in queue management
US7792131B1 (en) * 2009-03-10 2010-09-07 Cisco Technologies, Inc. Queue sharing with fair rate guarantee
US8156265B2 (en) * 2009-06-02 2012-04-10 Freescale Semiconductor, Inc. Data processor coupled to a sequencer circuit that provides efficient scalable queuing and method
US20120106555A1 (en) * 2010-11-01 2012-05-03 Indian Institute Of Technology Bombay Low latency carrier class switch-router
US8565092B2 (en) 2010-11-18 2013-10-22 Cisco Technology, Inc. Dynamic flow redistribution for head of line blocking avoidance
WO2013083191A1 (en) * 2011-12-07 2013-06-13 Huawei Technologies Co., Ltd. Queuing apparatus
US8705366B2 (en) 2012-01-23 2014-04-22 Cisco Technology, Inc. Dynamic load balancing without packet reordering
US8825927B2 (en) * 2012-09-04 2014-09-02 Advanced Micro Devices, Inc. Systems and methods for managing queues
US9313148B2 (en) * 2013-04-26 2016-04-12 Mediatek Inc. Output queue of multi-plane network device and related method of managing output queue having multiple packet linked lists
EP3166269B1 (en) * 2014-08-07 2019-07-10 Huawei Technologies Co., Ltd. Queue management method and apparatus
US9755955B2 (en) 2015-02-18 2017-09-05 Accedian Networks Inc. Single queue link aggregation
US10200313B2 (en) * 2016-06-02 2019-02-05 Marvell Israel (M.I.S.L) Ltd. Packet descriptor storage in packet memory with cache
US11483244B2 (en) 2020-03-18 2022-10-25 Marvell Israel (M.I.S.L) Ltd. Packet buffer spill-over in network devices
CN113783806B (en) * 2021-08-31 2023-10-17 上海新氦类脑智能科技有限公司 Shunt route jump method, device, medium, equipment and multi-core system applied by same

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US5524265A (en) * 1994-03-08 1996-06-04 Texas Instruments Incorporated Architecture of transfer processor
EP0897154A2 (en) * 1997-08-13 1999-02-17 Compaq Computer Corporation Memory controller supporting dram circuits with different operating speeds

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US5502833A (en) 1994-03-30 1996-03-26 International Business Machines Corporation System and method for management of a predictive split cache for supporting FIFO queues
US5583861A (en) 1994-04-28 1996-12-10 Integrated Telecom Technology ATM switching element and method having independently accessible cell memories
US6523060B1 (en) 1995-04-07 2003-02-18 Cisco Technology, Inc. Method and apparatus for the management of queue pointers by multiple processors in a digital communications network
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5524265A (en) * 1994-03-08 1996-06-04 Texas Instruments Incorporated Architecture of transfer processor
EP0897154A2 (en) * 1997-08-13 1999-02-17 Compaq Computer Corporation Memory controller supporting dram circuits with different operating speeds

Also Published As

Publication number Publication date
CN1439217A (en) 2003-08-27
US20150016467A1 (en) 2015-01-15
CN1260936C (en) 2006-06-21
CA2407310C (en) 2013-02-19
US7236489B1 (en) 2007-06-26
DE10196135T1 (en) 2003-03-27
US8184635B2 (en) 2012-05-22
CA2407310A1 (en) 2001-11-08
AU2001250222A1 (en) 2001-11-12
US7804834B2 (en) 2010-09-28
WO2001084773A2 (en) 2001-11-08
US20120219010A1 (en) 2012-08-30
US8837502B2 (en) 2014-09-16
US20100325380A1 (en) 2010-12-23
GB0224761D0 (en) 2002-12-04
DE10196135B4 (en) 2010-07-22
GB2377065A (en) 2002-12-31
GB2377065B (en) 2004-10-13
US20070223482A1 (en) 2007-09-27

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