WO2001093428A8 - Product code based forward error correction system - Google Patents
Product code based forward error correction systemInfo
- Publication number
- WO2001093428A8 WO2001093428A8 PCT/US2001/018059 US0118059W WO0193428A8 WO 2001093428 A8 WO2001093428 A8 WO 2001093428A8 US 0118059 W US0118059 W US 0118059W WO 0193428 A8 WO0193428 A8 WO 0193428A8
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- error correction
- forward error
- correction system
- product code
- code based
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2909—Product codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2927—Decoding strategies
Abstract
A multidimensional forward error correction system. Transmitted data is encoded by an encoder (13) in multiple dimensions. The decoding of received data by a decoder (20) is performed in multiple passes, with corrected data rewritten into memory. The encoder (13) in one embodiment comprises a parallel column decoder and multiple row encoders encoding a (255, 239) BCH code.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/587,150 | 2000-06-02 | ||
US09/587,150 US6738942B1 (en) | 2000-06-02 | 2000-06-02 | Product code based forward error correction system |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2001093428A2 WO2001093428A2 (en) | 2001-12-06 |
WO2001093428A8 true WO2001093428A8 (en) | 2002-03-28 |
WO2001093428A3 WO2001093428A3 (en) | 2002-08-29 |
Family
ID=24348566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/018059 WO2001093428A2 (en) | 2000-06-02 | 2001-06-04 | Product code based forward error correction system |
Country Status (2)
Country | Link |
---|---|
US (2) | US6738942B1 (en) |
WO (1) | WO2001093428A2 (en) |
Families Citing this family (93)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6307487B1 (en) | 1998-09-23 | 2001-10-23 | Digital Fountain, Inc. | Information additive code generator and decoder for communication systems |
US7068729B2 (en) | 2001-12-21 | 2006-06-27 | Digital Fountain, Inc. | Multi-stage code generator and decoder for communication systems |
US6289039B1 (en) * | 2000-06-14 | 2001-09-11 | Linex Technologies, Inc. | Spread-spectrum communications utilizing variable throughput reduction |
FR2816773B1 (en) * | 2000-11-10 | 2004-11-26 | France Telecom | MODULE, DEVICE AND METHOD FOR HIGH-SPEED DECODING OF A CONCATENE CODE |
US9100457B2 (en) | 2001-03-28 | 2015-08-04 | Qualcomm Incorporated | Method and apparatus for transmission framing in a wireless communication system |
US8656246B2 (en) * | 2001-04-16 | 2014-02-18 | Qualcomm Incorporated | Method and an apparatus for use of codes in multicast transmission |
US7352868B2 (en) | 2001-10-09 | 2008-04-01 | Philip Hawkes | Method and apparatus for security in a data processing system |
US7649829B2 (en) * | 2001-10-12 | 2010-01-19 | Qualcomm Incorporated | Method and system for reduction of decoding complexity in a communication system |
US6990624B2 (en) * | 2001-10-12 | 2006-01-24 | Agere Systems Inc. | High speed syndrome-based FEC encoder and decoder and system using same |
US7552203B2 (en) | 2001-10-17 | 2009-06-23 | The Boeing Company | Manufacturing method and software product for optimizing information flow |
US7146553B2 (en) | 2001-11-21 | 2006-12-05 | Infinera Corporation | Error correction improvement for concatenated codes |
FR2838580B1 (en) * | 2002-04-12 | 2005-04-01 | Canon Kk | LOW COST METHODS AND DEVICES FOR DECODING PRODUCED CODES |
DE10216999A1 (en) * | 2002-04-16 | 2003-11-06 | Thomson Brandt Gmbh | ECC block encoders and decoders with reduced RAM requirements |
JP2003318865A (en) * | 2002-04-26 | 2003-11-07 | Fuji Xerox Co Ltd | Signal transmission system |
ES2400239T3 (en) * | 2002-06-11 | 2013-04-08 | Digital Fountain, Inc. | Decoding chain reaction codes by inactivating recovered symbols |
US9240810B2 (en) | 2002-06-11 | 2016-01-19 | Digital Fountain, Inc. | Systems and processes for decoding chain reaction codes through inactivation |
DE10243786A1 (en) * | 2002-09-20 | 2004-04-01 | Siemens Ag | Coding method for data bit sequence in optical transmission system using column or row coding of data bit sequence matrix and re-arrangement of each row or column data bit sequence |
KR101143282B1 (en) | 2002-10-05 | 2012-05-08 | 디지털 파운튼, 인크. | Systematic encoding and decoding of chain reaction codes |
US7599655B2 (en) | 2003-01-02 | 2009-10-06 | Qualcomm Incorporated | Method and apparatus for broadcast services in a communication system |
WO2004095759A2 (en) * | 2003-04-22 | 2004-11-04 | Vitesse Semiconductor Corporation | Concatenated iterative forward error correction coding |
US8718279B2 (en) | 2003-07-08 | 2014-05-06 | Qualcomm Incorporated | Apparatus and method for a secure broadcast system |
US8724803B2 (en) | 2003-09-02 | 2014-05-13 | Qualcomm Incorporated | Method and apparatus for providing authenticated challenges for broadcast-multicast communications in a communication system |
US7191379B2 (en) * | 2003-09-10 | 2007-03-13 | Hewlett-Packard Development Company, L.P. | Magnetic memory with error correction coding |
EP1665539B1 (en) | 2003-10-06 | 2013-04-10 | Digital Fountain, Inc. | Soft-Decision Decoding of Multi-Stage Chain Reaction Codes |
ATE490603T1 (en) * | 2004-02-13 | 2010-12-15 | Alcatel Lucent | ITERATIVE DECODING OF TWO-DIMENSIONAL BLOCK CODES |
JP4056488B2 (en) * | 2004-03-30 | 2008-03-05 | エルピーダメモリ株式会社 | Semiconductor device testing method and manufacturing method |
US7418651B2 (en) | 2004-05-07 | 2008-08-26 | Digital Fountain, Inc. | File download and streaming system |
JP4135680B2 (en) * | 2004-05-31 | 2008-08-20 | ソニー株式会社 | Semiconductor memory device and signal processing system |
US7600177B2 (en) * | 2005-02-08 | 2009-10-06 | Lsi Corporation | Delta syndrome based iterative Reed-Solomon product code decoder |
US7779326B2 (en) * | 2005-03-01 | 2010-08-17 | The Texas A&M University System | Multi-source data encoding, transmission and decoding using Slepian-Wolf codes based on channel code partitioning |
US7653867B2 (en) * | 2005-03-01 | 2010-01-26 | The Texas A&M University System | Multi-source data encoding, transmission and decoding using Slepian-Wolf codes based on channel code partitioning |
US7167410B2 (en) * | 2005-04-26 | 2007-01-23 | Magnalynx | Memory system and memory device having a serial interface |
US7676735B2 (en) * | 2005-06-10 | 2010-03-09 | Digital Fountain Inc. | Forward error-correcting (FEC) coding and streaming |
US7599396B2 (en) * | 2005-07-11 | 2009-10-06 | Magnalynx, Inc. | Method of encoding and synchronizing a serial interface |
WO2007095550A2 (en) | 2006-02-13 | 2007-08-23 | Digital Fountain, Inc. | Streaming and buffering using variable fec overhead and protection periods |
US9270414B2 (en) | 2006-02-21 | 2016-02-23 | Digital Fountain, Inc. | Multiple-field based code generator and decoder for communications systems |
US7945838B2 (en) * | 2006-05-05 | 2011-05-17 | Texas Instruments Incorporated | Parity check decoder architecture |
US7971129B2 (en) | 2006-05-10 | 2011-06-28 | Digital Fountain, Inc. | Code generator and decoder for communications systems operating using hybrid codes to allow for multiple efficient users of the communications systems |
US20070266293A1 (en) * | 2006-05-10 | 2007-11-15 | Samsung Electronics Co., Ltd. | Apparatus and method for high speed data transceiving, and apparatus and method for error-correction processing for the same |
US9178535B2 (en) | 2006-06-09 | 2015-11-03 | Digital Fountain, Inc. | Dynamic stream interleaving and sub-stream based delivery |
US9432433B2 (en) | 2006-06-09 | 2016-08-30 | Qualcomm Incorporated | Enhanced block-request streaming system using signaling or block creation |
US9209934B2 (en) | 2006-06-09 | 2015-12-08 | Qualcomm Incorporated | Enhanced block-request streaming using cooperative parallel HTTP and forward error correction |
US9419749B2 (en) | 2009-08-19 | 2016-08-16 | Qualcomm Incorporated | Methods and apparatus employing FEC codes with permanent inactivation of symbols for encoding and decoding processes |
US9386064B2 (en) | 2006-06-09 | 2016-07-05 | Qualcomm Incorporated | Enhanced block-request streaming using URL templates and construction rules |
US9380096B2 (en) | 2006-06-09 | 2016-06-28 | Qualcomm Incorporated | Enhanced block-request streaming system for handling low-latency streaming |
US8024645B2 (en) * | 2006-06-29 | 2011-09-20 | Motorola Solutions, Inc. | Method for error detection in a decoded digital signal stream |
US8046660B2 (en) * | 2006-08-07 | 2011-10-25 | Marvell World Trade Ltd. | System and method for correcting errors in non-volatile memory using product codes |
DE102006045311A1 (en) * | 2006-09-26 | 2008-03-27 | Nokia Siemens Networks Gmbh & Co.Kg | Method and device for reconstructing at least one data packet |
US8196004B1 (en) | 2007-03-27 | 2012-06-05 | Marvell International Ltd. | Fast erasure decoding for product code columns |
CA2697764A1 (en) | 2007-09-12 | 2009-03-19 | Steve Chen | Generating and communicating source identification information to enable reliable communications |
US8156413B2 (en) * | 2007-11-28 | 2012-04-10 | Qualcomm Incorporated | Convolutional encoding with partitioned parallel encoding operations |
WO2009099308A2 (en) * | 2008-02-05 | 2009-08-13 | Lg Electronics Inc. | Method for transmitting control information in wireless communication system |
US8719670B1 (en) * | 2008-05-07 | 2014-05-06 | Sk Hynix Memory Solutions Inc. | Coding architecture for multi-level NAND flash memory with stuck cells |
BRPI0801767A2 (en) * | 2008-06-02 | 2010-02-23 | Ubea | multidimensional encoding and / or decoding method and system comprising such method |
US9281847B2 (en) | 2009-02-27 | 2016-03-08 | Qualcomm Incorporated | Mobile reception of digital video broadcasting—terrestrial services |
US8261167B1 (en) | 2009-03-09 | 2012-09-04 | Pmc-Sierra Us, Inc. | Cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation |
US9288010B2 (en) | 2009-08-19 | 2016-03-15 | Qualcomm Incorporated | Universal file delivery methods for providing unequal error protection and bundled file delivery services |
US9917874B2 (en) | 2009-09-22 | 2018-03-13 | Qualcomm Incorporated | Enhanced block-request streaming using block partitioning or request controls for improved client-side handling |
US8359518B2 (en) * | 2009-10-27 | 2013-01-22 | Altera Canada Co. | 2D product code and method for detecting false decoding errors |
US8347192B1 (en) | 2010-03-08 | 2013-01-01 | Altera Corporation | Parallel finite field vector operators |
US20110280311A1 (en) | 2010-05-13 | 2011-11-17 | Qualcomm Incorporated | One-stream coding for asymmetric stereo video |
US9596447B2 (en) | 2010-07-21 | 2017-03-14 | Qualcomm Incorporated | Providing frame packing type information for video coding |
US9456015B2 (en) | 2010-08-10 | 2016-09-27 | Qualcomm Incorporated | Representation groups for network streaming of coded multimedia data |
US9270299B2 (en) | 2011-02-11 | 2016-02-23 | Qualcomm Incorporated | Encoding and decoding using elastic codes with flexible source block mapping |
US8958375B2 (en) | 2011-02-11 | 2015-02-17 | Qualcomm Incorporated | Framing for an improved radio link protocol including FEC |
US8751910B2 (en) | 2011-04-13 | 2014-06-10 | Cortina Systems, Inc. | Staircase forward error correction coding |
US8756480B2 (en) * | 2011-06-06 | 2014-06-17 | Cleversafe, Inc. | Prioritized deleting of slices stored in a dispersed storage network |
GB201114831D0 (en) * | 2011-08-26 | 2011-10-12 | Univ Oxford Brookes | Circuit with error correction |
US9253233B2 (en) | 2011-08-31 | 2016-02-02 | Qualcomm Incorporated | Switch signaling methods providing improved switching between representations for adaptive HTTP streaming |
US8667377B1 (en) * | 2011-09-08 | 2014-03-04 | Xilinx, Inc. | Circuit and method for parallel decoding |
US9843844B2 (en) | 2011-10-05 | 2017-12-12 | Qualcomm Incorporated | Network streaming of media data |
US8683296B2 (en) | 2011-12-30 | 2014-03-25 | Streamscale, Inc. | Accelerated erasure coding system and method |
US8914706B2 (en) | 2011-12-30 | 2014-12-16 | Streamscale, Inc. | Using parity data for concurrent data authentication, correction, compression, and encryption |
US9294226B2 (en) | 2012-03-26 | 2016-03-22 | Qualcomm Incorporated | Universal object delivery and template-based file delivery |
US8949699B1 (en) * | 2012-08-29 | 2015-02-03 | Xilinx, Inc. | Circuit for forward error correction encoding of data blocks across multiple data lanes |
US9053748B2 (en) | 2012-11-14 | 2015-06-09 | International Business Machines Corporation | Reconstructive error recovery procedure (ERP) using reserved buffer |
US8793552B2 (en) | 2012-11-14 | 2014-07-29 | International Business Machines Corporation | Reconstructive error recovery procedure (ERP) for multiple data sets using reserved buffer |
US8810944B1 (en) | 2013-07-16 | 2014-08-19 | International Business Machines Corporation | Dynamic buffer size switching for burst errors encountered while reading a magnetic tape |
US9582360B2 (en) | 2014-01-07 | 2017-02-28 | International Business Machines Corporation | Single and multi-cut and paste (C/P) reconstructive error recovery procedure (ERP) using history of error correction |
US9141478B2 (en) | 2014-01-07 | 2015-09-22 | International Business Machines Corporation | Reconstructive error recovery procedure (ERP) using reserved buffer |
US9804925B1 (en) | 2014-02-25 | 2017-10-31 | Google Inc. | Data reconstruction in distributed storage systems |
US9584159B1 (en) | 2014-07-03 | 2017-02-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Interleaved encoding |
GB2531783B (en) | 2014-10-30 | 2016-09-28 | Ibm | Method and device for removing error patterns in binary data |
JP2016126813A (en) * | 2015-01-08 | 2016-07-11 | マイクロン テクノロジー, インク. | Semiconductor device |
US10892972B2 (en) | 2017-04-26 | 2021-01-12 | Microsemi Storage Solutions, Inc. | Scheduled network setup test method and system |
US10236913B2 (en) * | 2017-05-11 | 2019-03-19 | Winbond Electronics Corp. | Error checking and correcting decoder |
US11265109B2 (en) | 2017-08-30 | 2022-03-01 | Marvell Asia Pte Ltd. | Soft FEC with parity check |
US10749629B2 (en) | 2017-08-30 | 2020-08-18 | Inphi Corporation | Soft FEC with parity check |
US10693500B2 (en) | 2017-09-15 | 2020-06-23 | Duke University | Systems and methods for decoding forward error correction codes based on component codes |
US10831596B2 (en) * | 2018-01-22 | 2020-11-10 | Micron Technology, Inc. | Enhanced error correcting code capability using variable logical to physical associations of a data block |
US11381252B1 (en) * | 2020-01-28 | 2022-07-05 | Marvell Asia Pte, Ltd. | Methods and systems for short error event correction in storage channel applications |
CN112332869A (en) * | 2020-10-22 | 2021-02-05 | 杭州华澜微电子股份有限公司 | Improved TPC iteration method and apparatus |
US11689216B1 (en) * | 2022-03-09 | 2023-06-27 | Samsung Electronics Co., Ltd. | Low gate-count generalized concatenated code (GCC) by online calculation of syndromes instead of buffer |
Family Cites Families (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4077028A (en) | 1976-06-14 | 1978-02-28 | Ncr Corporation | Error checking and correcting device |
US4099160A (en) | 1976-07-15 | 1978-07-04 | International Business Machines Corporation | Error location apparatus and methods |
US4162480A (en) | 1977-01-28 | 1979-07-24 | Cyclotomics, Inc. | Galois field computer |
US4142174A (en) | 1977-08-15 | 1979-02-27 | International Business Machines Corporation | High speed decoding of Reed-Solomon codes |
JPS574629A (en) | 1980-05-21 | 1982-01-11 | Sony Corp | Data transmitting method capable of correction of error |
US4410989A (en) | 1980-12-11 | 1983-10-18 | Cyclotomics, Inc. | Bit serial encoder |
EP0080528A1 (en) | 1981-11-30 | 1983-06-08 | Omnet Associates | Computational method and apparatus for finite field arithmetic |
US4475194A (en) * | 1982-03-30 | 1984-10-02 | International Business Machines Corporation | Dynamic replacement of defective memory words |
US4494234A (en) | 1982-12-29 | 1985-01-15 | International Business Machines Corporation | On-the-fly multibyte error correcting system |
US4504948A (en) | 1982-12-29 | 1985-03-12 | International Business Machines Corporation | Syndrome processing unit for multibyte error correcting systems |
US4653051A (en) * | 1983-09-14 | 1987-03-24 | Matsushita Electric Industrial Co., Ltd. | Apparatus for detecting and correcting errors on product codes |
US4633471A (en) | 1983-09-19 | 1986-12-30 | Storage Technology Partners Ii | Error detection and correction in an optical storage system |
US4633470A (en) | 1983-09-27 | 1986-12-30 | Cyclotomics, Inc. | Error correction for algebraic block codes |
DE3486200T2 (en) * | 1983-12-20 | 1993-12-02 | Sony Corp | METHOD AND DEVICE FOR DECODING AN ERROR ENHANCEMENT CODE. |
JPH084233B2 (en) * | 1984-06-29 | 1996-01-17 | 株式会社日立製作所 | Error correction code decoding device |
NL8402411A (en) | 1984-08-02 | 1986-03-03 | Philips Nv | DEVICE FOR CORRECTING AND MASKING ERRORS IN AN INFORMATION FLOW, AND DISPLAY FOR DISPLAYING IMAGES AND / OR SOUND PROVIDED WITH SUCH A DEVICE. |
US4777635A (en) | 1986-08-08 | 1988-10-11 | Data Systems Technology Corp. | Reed-Solomon code encoder and syndrome generator circuit |
US4937829A (en) | 1987-04-24 | 1990-06-26 | Ricoh Company, Ltd. | Error correcting system and device |
US4873688A (en) | 1987-10-05 | 1989-10-10 | Idaho Research Foundation | High-speed real-time Reed-Solomon decoder |
US4835775A (en) | 1987-10-13 | 1989-05-30 | Cyclotomics, Inc. | Hypersystolic reed-solomon encoder |
US5247523A (en) * | 1989-07-12 | 1993-09-21 | Hitachi, Ltd. | Code error correction apparatus |
US5170399A (en) | 1989-08-30 | 1992-12-08 | Idaho Research Foundation, Inc. | Reed-Solomon Euclid algorithm decoder having a process configurable Euclid stack |
EP0437865B1 (en) | 1990-01-18 | 1997-04-16 | Koninklijke Philips Electronics N.V. | Storage device for reversibly storing digital data on a multitrack storage medium, a decoding device, an information reproducing apparatus for use with such storage medium, and a unitary storage medium for use with such storage device, decoding device and/or information reproducing device |
US5140596A (en) | 1990-02-20 | 1992-08-18 | Eastman Kodak Company | High speed encoder for non-systematic codes |
US5226043A (en) | 1990-12-27 | 1993-07-06 | Raytheon Company | Apparatus and method for data error detection and correction and address error detection in a memory system |
US5323402A (en) | 1991-02-14 | 1994-06-21 | The Mitre Corporation | Programmable systolic BCH decoder |
US5384786A (en) | 1991-04-02 | 1995-01-24 | Cirrus Logic, Inc. | Fast and efficient circuit for identifying errors introduced in Reed-Solomon codewords |
JPH05225798A (en) * | 1991-08-14 | 1993-09-03 | Internatl Business Mach Corp <Ibm> | Memory system |
WO1993004432A2 (en) * | 1991-08-16 | 1993-03-04 | Multichip Technology | High-performance dynamic memory system |
US5392299A (en) * | 1992-01-15 | 1995-02-21 | E-Systems, Inc. | Triple orthogonally interleaed error correction system |
US5375127A (en) | 1992-03-25 | 1994-12-20 | Ncr Corporation | Method and apparatus for generating Reed-Soloman error correcting code across multiple word boundaries |
US5587803A (en) * | 1992-04-01 | 1996-12-24 | Mitsubishi Denki Kabushiki Kaisha | Digital signal recording and reproducing apparatus and error-correcting apparatus |
US5272661A (en) | 1992-12-15 | 1993-12-21 | Comstream Corporation | Finite field parallel multiplier |
JPH06314978A (en) | 1993-04-28 | 1994-11-08 | Nec Corp | Chain search circuit |
FR2712760B1 (en) * | 1993-11-19 | 1996-01-26 | France Telecom | Method for transmitting bits of information by applying concatenated block codes. |
JPH07264042A (en) | 1994-03-17 | 1995-10-13 | Fujitsu Ltd | High speed interface circuit |
US5699368A (en) | 1994-03-25 | 1997-12-16 | Mitsubishi Denki Kabushiki Kaisha | Error-correcting encoder, error-correcting decoder, and data transmitting system with error-correcting codes |
US5689452A (en) | 1994-10-31 | 1997-11-18 | University Of New Mexico | Method and apparatus for performing arithmetic in large galois field GF(2n) |
JP2731745B2 (en) * | 1995-03-23 | 1998-03-25 | 甲府日本電気株式会社 | Data failure handling device |
US5757826A (en) | 1995-07-12 | 1998-05-26 | Quantum Corporation | Word-wise processing for reed-solomon codes |
JP3782840B2 (en) * | 1995-07-14 | 2006-06-07 | 株式会社ルネサステクノロジ | External storage device and memory access control method thereof |
US5719884A (en) | 1995-07-27 | 1998-02-17 | Hewlett-Packard Company | Error correction method and apparatus based on two-dimensional code array with reduced redundancy |
US5754563A (en) | 1995-09-11 | 1998-05-19 | Ecc Technologies, Inc. | Byte-parallel system for implementing reed-solomon error-correcting codes |
KR0186212B1 (en) * | 1995-11-21 | 1999-04-15 | 구자홍 | Error control coding method for the varied speed mode of a dvcr |
US5721745A (en) * | 1996-04-19 | 1998-02-24 | General Electric Company | Parallel concatenated tail-biting convolutional code and decoder therefor |
KR100192795B1 (en) | 1996-05-14 | 1999-06-15 | 전주범 | Device for calculating error-locator polynominal in a rs decoder |
US6023783A (en) * | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
US5734962A (en) * | 1996-07-17 | 1998-03-31 | General Electric Company | Satellite communications system utilizing parallel concatenated coding |
US6023782A (en) | 1996-12-13 | 2000-02-08 | International Business Machines Corporation | RAM based key equation solver apparatus |
US6490243B1 (en) * | 1997-06-19 | 2002-12-03 | Kabushiki Kaisha Toshiba | Information data multiplex transmission system, its multiplexer and demultiplexer and error correction encoder and decoder |
US6161209A (en) | 1997-03-28 | 2000-12-12 | Her Majesty The Queen In Right Of Canada, As Represented By The Minister Of Industry Through The Communications Research Centre | Joint detector for multiple coded digital signals |
US5974580A (en) * | 1997-07-23 | 1999-10-26 | Cirrus Logic, Inc. | Concurrent row/column syndrome generator for a product code |
EP0913826A1 (en) * | 1997-10-31 | 1999-05-06 | Hewlett-Packard Company | Scratch protection in tape data storage system |
US6052815A (en) * | 1997-11-14 | 2000-04-18 | Cirrus Logic, Inc. | ECC system for generating a CRC syndrome over randomized data in a computer storage device |
US6378100B1 (en) * | 1997-12-29 | 2002-04-23 | U.S. Philips Corporation | Method and apparatus for encoding multiword information with error locative clues directed to low protectivity words |
US6289000B1 (en) * | 2000-05-19 | 2001-09-11 | Intellon Corporation | Frame control encoder/decoder for robust OFDM frame transmissions |
-
2000
- 2000-06-02 US US09/587,150 patent/US6738942B1/en not_active Expired - Fee Related
-
2001
- 2001-06-04 WO PCT/US2001/018059 patent/WO2001093428A2/en active Application Filing
- 2001-06-04 US US09/874,158 patent/US6810499B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6738942B1 (en) | 2004-05-18 |
WO2001093428A3 (en) | 2002-08-29 |
US20020049947A1 (en) | 2002-04-25 |
US6810499B2 (en) | 2004-10-26 |
WO2001093428A2 (en) | 2001-12-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2001093428A8 (en) | Product code based forward error correction system | |
WO2003049294A3 (en) | Erasure and single error correction decoder for linear product codes | |
WO2008021045A3 (en) | System and method for correcting errors in non-volatile memory using product codes | |
CA2486048A1 (en) | Method and system for providing long and short block length low density parity check (ldpc) codes | |
CA2273169A1 (en) | Variable length decoder and decoding method | |
WO1998016016A3 (en) | Error correction with two block codes and error correction with transmission repetition | |
EP1160987A3 (en) | Method and apparatus for verifying error correcting codes | |
EP1206040A3 (en) | Low delay channel codes for correcting bursts of lost packets | |
EP0756385A3 (en) | Error correction method and apparatus based on two-dimensional code array with reduced redundancy | |
CA2206688A1 (en) | Digital transmission system for encoding and decoding attribute data into error checking symbols of main data, and method therefor | |
ZA200208767B (en) | Method for encoding and decoding video information, a motion compensated video encoder and a corresponding decoder. | |
CA2056884A1 (en) | Concatenated coding method and apparatus with errors and erasures decoding | |
SG154338A1 (en) | Detection, avoidance and/or correction of problematic puncturing patterns in parity bit streams used when implementing turbo codes | |
HK1068436A1 (en) | Pipeline architecture for maximum a posteriori (map) decoders | |
EP1801982A9 (en) | Encoder, decoder, methods of encoding and decoding | |
EP1513258A3 (en) | Method and system for encoding short block length low density parity check (LDPC) codes | |
WO2004003750A3 (en) | Error detection/correction code which detects component failure and which provides single bit error correction upon such detection | |
WO2002001561A3 (en) | Method and apparatus for encoding with unequal protection in magnetic recording channels having concatenated error correction codes | |
WO2002031983A3 (en) | Soft decision maximum likelihood encoder and decoder | |
EP1542475A3 (en) | Video coding | |
CA2165604A1 (en) | Synchronization and error detection in a packetized data stream | |
EP0609188A3 (en) | Erasure decoder and decoding method for use in a concatenated error correcting scheme for data transmission systems. | |
WO2003013004A3 (en) | Signal coding | |
MY115663A (en) | Apparatus and method for decoding a coded digital signal | |
WO2003027849A3 (en) | Double error correcting code system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
AL | Designated countries for regional patents |
Kind code of ref document: C1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
CFP | Corrected version of a pamphlet front page | ||
CR1 | Correction of entry in section i |
Free format text: PAT. BUL. 49/2001 UNDER (30) REPLACE "09/587160" BY "09/587150" |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
122 | Ep: pct application non-entry in european phase |