WO2002001607A2 - Method of producing trench capacitor buried strap - Google Patents
Method of producing trench capacitor buried strap Download PDFInfo
- Publication number
- WO2002001607A2 WO2002001607A2 PCT/US2001/020206 US0120206W WO0201607A2 WO 2002001607 A2 WO2002001607 A2 WO 2002001607A2 US 0120206 W US0120206 W US 0120206W WO 0201607 A2 WO0201607 A2 WO 0201607A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- silicon
- deep trench
- deposited
- trench
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020027017467A KR100822079B1 (en) | 2000-06-23 | 2001-06-25 | Single sided buried strap |
EP01948702A EP1292983B1 (en) | 2000-06-23 | 2001-06-25 | Method of producing trench capacitor buried strap |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/603,442 | 2000-06-23 | ||
US09/603,442 US6573137B1 (en) | 2000-06-23 | 2000-06-23 | Single sided buried strap |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002001607A2 true WO2002001607A2 (en) | 2002-01-03 |
WO2002001607A3 WO2002001607A3 (en) | 2002-05-23 |
Family
ID=24415457
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/020206 WO2002001607A2 (en) | 2000-06-23 | 2001-06-25 | Method of producing trench capacitor buried strap |
Country Status (5)
Country | Link |
---|---|
US (2) | US6573137B1 (en) |
EP (1) | EP1292983B1 (en) |
KR (1) | KR100822079B1 (en) |
TW (2) | TW495906B (en) |
WO (1) | WO2002001607A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001091180A2 (en) * | 2000-05-23 | 2001-11-29 | Infineon Technologies North America Corp. | System and method of forming a vertically oriented device in an integrated circuit |
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US6794242B1 (en) * | 2000-09-29 | 2004-09-21 | Infineon Technologies Ag | Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts |
DE10131709B4 (en) * | 2001-06-29 | 2006-10-26 | Infineon Technologies Ag | Method for producing one-sided buried straps |
US6566706B1 (en) * | 2001-10-31 | 2003-05-20 | Silicon Storage Technology, Inc. | Semiconductor array of floating gate memory cells and strap regions |
US6586300B1 (en) * | 2002-04-18 | 2003-07-01 | Infineon Technologies Ag | Spacer assisted trench top isolation for vertical DRAM's |
US20040110429A1 (en) * | 2002-07-26 | 2004-06-10 | Eberhard Wizgall | Integrated intake manifold and heat exchanger |
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US6759702B2 (en) | 2002-09-30 | 2004-07-06 | International Business Machines Corporation | Memory cell with vertical transistor and trench capacitor with reduced burried strap |
US6979851B2 (en) * | 2002-10-04 | 2005-12-27 | International Business Machines Corporation | Structure and method of vertical transistor DRAM cell having a low leakage buried strap |
US6734482B1 (en) * | 2002-11-15 | 2004-05-11 | Micron Technology, Inc. | Trench buried bit line memory devices |
TWI223408B (en) * | 2003-05-09 | 2004-11-01 | Nanya Technology Corp | Trench type capacitor formation method |
US6750116B1 (en) * | 2003-07-14 | 2004-06-15 | Nanya Technology Corp. | Method for fabricating asymmetric inner structure in contacts or trenches |
DE10333777B4 (en) * | 2003-07-24 | 2007-01-25 | Infineon Technologies Ag | A manufacturing method for a trench capacitor with an insulation collar, which is electrically connected on one side to a substrate via a buried contact, in particular for a semiconductor memory cell |
US20050088895A1 (en) * | 2003-07-25 | 2005-04-28 | Infineon Technologies Ag | DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM |
DE102004026000A1 (en) * | 2003-07-25 | 2005-02-24 | Infineon Technologies Ag | Cell field for DRAMs comprises memory cells having lower source/drain regions with sections of trenched source/drain layer perforated by perforated trenches and word line trenches |
TWI225689B (en) * | 2003-12-05 | 2004-12-21 | Nanya Technology Corp | Method for forming a self-aligned buried strap in a vertical memory cell |
TWI227933B (en) * | 2003-12-05 | 2005-02-11 | Nanya Technology Corp | Method for forming a self-aligned buried strap of a vertical memory cell |
TWI235426B (en) * | 2004-01-28 | 2005-07-01 | Nanya Technology Corp | Method for manufacturing single-sided buried strap |
US7034352B2 (en) * | 2004-02-11 | 2006-04-25 | Infineon Technologies Ag | DRAM with very shallow trench isolation |
US6998677B1 (en) | 2004-03-08 | 2006-02-14 | Advanced Micro Devices, Inc. | Semiconductor component and method of manufacture |
DE102004031694A1 (en) * | 2004-06-30 | 2006-01-19 | Infineon Technologies Ag | A manufacturing method for a trench capacitor with an insulation collar, which is electrically connected on one side to a substrate via a buried contact, in particular for a semiconductor memory cell |
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US20080048186A1 (en) * | 2006-03-30 | 2008-02-28 | International Business Machines Corporation | Design Structures Incorporating Semiconductor Device Structures with Self-Aligned Doped Regions |
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US20070284612A1 (en) * | 2006-06-09 | 2007-12-13 | International Business Machines Corporation | Semiconductor devices with one-sided buried straps |
US7618867B2 (en) * | 2006-07-26 | 2009-11-17 | Infineon Technologies Ag | Method of forming a doped portion of a semiconductor and method of forming a transistor |
TW200816388A (en) * | 2006-09-20 | 2008-04-01 | Nanya Technology Corp | A manufacturing method of a memory device |
US7691734B2 (en) * | 2007-03-01 | 2010-04-06 | International Business Machines Corporation | Deep trench based far subcollector reachthrough |
US7439149B1 (en) * | 2007-09-26 | 2008-10-21 | International Business Machines Corporation | Structure and method for forming SOI trench memory with single-sided strap |
CN101409210B (en) * | 2007-10-09 | 2010-06-02 | 南亚科技股份有限公司 | Semiconductor element and preparation method thereof |
US8008160B2 (en) | 2008-01-21 | 2011-08-30 | International Business Machines Corporation | Method and structure for forming trench DRAM with asymmetric strap |
US7838928B2 (en) * | 2008-06-06 | 2010-11-23 | Qimonda Ag | Word line to bit line spacing method and apparatus |
US9016236B2 (en) * | 2008-08-04 | 2015-04-28 | International Business Machines Corporation | Method and apparatus for angular high density plasma chemical vapor deposition |
US8227310B2 (en) | 2008-08-06 | 2012-07-24 | International Business Machines Corporation | Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact and methods of making |
US20100090348A1 (en) * | 2008-10-10 | 2010-04-15 | Inho Park | Single-Sided Trench Contact Window |
KR101096184B1 (en) * | 2009-11-30 | 2011-12-22 | 주식회사 하이닉스반도체 | Method for manufacturing side contact in semiconductor device using self aligned damascene process |
JP2011205030A (en) * | 2010-03-26 | 2011-10-13 | Elpida Memory Inc | Semiconductor device and method of manufacturing the same |
KR101133692B1 (en) * | 2010-07-07 | 2012-04-19 | 에스케이하이닉스 주식회사 | Method for forming masking layer usig implant and method for manufacturing semiconductor device using the same |
KR101202690B1 (en) * | 2010-12-09 | 2012-11-19 | 에스케이하이닉스 주식회사 | Methof for forming side contact in semiconductor device |
KR101213931B1 (en) * | 2010-12-14 | 2012-12-18 | 에스케이하이닉스 주식회사 | Vertical type semiconductor and method of the same |
US8786014B2 (en) | 2011-01-18 | 2014-07-22 | Powerchip Technology Corporation | Vertical channel transistor array and manufacturing method thereof |
KR20120097663A (en) * | 2011-02-25 | 2012-09-05 | 에스케이하이닉스 주식회사 | Method for manufacturing buried bit line in semiconductor device |
JP2012248665A (en) * | 2011-05-27 | 2012-12-13 | Elpida Memory Inc | Manufacturing method of semiconductor device |
US10043810B1 (en) | 2017-08-18 | 2018-08-07 | Winbond Electronics Corp. | Dynamic random access memory and method of fabricating the same |
US20210384197A1 (en) * | 2019-06-14 | 2021-12-09 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of fabricating the same |
KR20200143109A (en) * | 2019-06-14 | 2020-12-23 | 삼성전자주식회사 | Semiconductor memory device and method of fabricating the same |
KR20210007737A (en) * | 2019-07-12 | 2021-01-20 | 에스케이하이닉스 주식회사 | Vertical memory device |
CN111403393B (en) * | 2020-03-24 | 2023-09-19 | 上海华力集成电路制造有限公司 | Device structure for improving coupling ratio of flash memory unit with body constraint fin structure |
Citations (2)
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US5989972A (en) | 1995-07-24 | 1999-11-23 | Siemens Aktiengesellschaft | Capacitor in a semiconductor configuration and process for its production |
DE19923262C1 (en) | 1999-05-20 | 2000-06-21 | Siemens Ag | Memory cell array, especially dynamic random access memory cell array, production comprises insulation removal from only one side wall of a recess by non-masked etching to allow adjacent cell transistor formation |
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-
2000
- 2000-06-23 US US09/603,442 patent/US6573137B1/en not_active Expired - Lifetime
-
2001
- 2001-05-15 TW TW090111614A patent/TW495906B/en not_active IP Right Cessation
- 2001-05-30 US US09/870,068 patent/US6426526B1/en not_active Expired - Fee Related
- 2001-06-22 TW TW090115308A patent/TW548801B/en not_active IP Right Cessation
- 2001-06-25 WO PCT/US2001/020206 patent/WO2002001607A2/en active Application Filing
- 2001-06-25 KR KR1020027017467A patent/KR100822079B1/en not_active IP Right Cessation
- 2001-06-25 EP EP01948702A patent/EP1292983B1/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5989972A (en) | 1995-07-24 | 1999-11-23 | Siemens Aktiengesellschaft | Capacitor in a semiconductor configuration and process for its production |
DE19923262C1 (en) | 1999-05-20 | 2000-06-21 | Siemens Ag | Memory cell array, especially dynamic random access memory cell array, production comprises insulation removal from only one side wall of a recess by non-masked etching to allow adjacent cell transistor formation |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001091180A2 (en) * | 2000-05-23 | 2001-11-29 | Infineon Technologies North America Corp. | System and method of forming a vertically oriented device in an integrated circuit |
WO2001091180A3 (en) * | 2000-05-23 | 2002-07-18 | Infineon Technologies Corp | System and method of forming a vertically oriented device in an integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
US6426526B1 (en) | 2002-07-30 |
TW548801B (en) | 2003-08-21 |
KR20030069800A (en) | 2003-08-27 |
EP1292983A2 (en) | 2003-03-19 |
TW495906B (en) | 2002-07-21 |
KR100822079B1 (en) | 2008-04-15 |
US6573137B1 (en) | 2003-06-03 |
EP1292983B1 (en) | 2012-10-24 |
WO2002001607A3 (en) | 2002-05-23 |
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