WO2002013004A3 - Software-to-hardware compiler - Google Patents

Software-to-hardware compiler Download PDF

Info

Publication number
WO2002013004A3
WO2002013004A3 PCT/US2001/041624 US0141624W WO0213004A3 WO 2002013004 A3 WO2002013004 A3 WO 2002013004A3 US 0141624 W US0141624 W US 0141624W WO 0213004 A3 WO0213004 A3 WO 0213004A3
Authority
WO
WIPO (PCT)
Prior art keywords
hardware
software
constructs
programmable logic
decisions
Prior art date
Application number
PCT/US2001/041624
Other languages
French (fr)
Other versions
WO2002013004A2 (en
Inventor
Paul Metzgen
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Priority to AU2001283549A priority Critical patent/AU2001283549A1/en
Priority to EP01962358A priority patent/EP1356401A2/en
Publication of WO2002013004A2 publication Critical patent/WO2002013004A2/en
Publication of WO2002013004A3 publication Critical patent/WO2002013004A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/323—Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level

Abstract

A software-to-hardware compiler is provided that generates hardware constructs in programmable logic based on pure software constructs. More particularly, a high-level program language may be used to create a program using only software constructs that is compiled into hardware constructs. Optimizations may be made in the later stages of compilation to retime the circuit, allowing for maximum data flow. The hardware may make run-time decisions with respect to executing programmable logic blocks in parallel. The decisions may be at least partially based on a control flow.
PCT/US2001/041624 2000-08-07 2001-08-07 Software-to-hardware compiler WO2002013004A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2001283549A AU2001283549A1 (en) 2000-08-07 2001-08-07 Software-to-hardware compiler
EP01962358A EP1356401A2 (en) 2000-08-07 2001-08-07 Software-to-hardware compiler

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22347100P 2000-08-07 2000-08-07
US60/223,471 2000-08-07

Publications (2)

Publication Number Publication Date
WO2002013004A2 WO2002013004A2 (en) 2002-02-14
WO2002013004A3 true WO2002013004A3 (en) 2003-08-21

Family

ID=22836634

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2001/041624 WO2002013004A2 (en) 2000-08-07 2001-08-07 Software-to-hardware compiler
PCT/US2001/024786 WO2002013072A2 (en) 2000-08-07 2001-08-07 Inter-device communication interface

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/US2001/024786 WO2002013072A2 (en) 2000-08-07 2001-08-07 Inter-device communication interface

Country Status (4)

Country Link
US (3) US7219342B2 (en)
EP (2) EP1356400A2 (en)
AU (2) AU2001281164A1 (en)
WO (2) WO2002013004A2 (en)

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19654595A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures
EP1329816B1 (en) 1996-12-27 2011-06-22 Richter, Thomas Method for automatic dynamic unloading of data flow processors (dfp) as well as modules with bidimensional or multidimensional programmable cell structures (fpgas, dpgas or the like)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (en) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
EP1351154A2 (en) 1998-11-20 2003-10-08 Altera Corporation Reconfigurable programmable logic device computer system
JP2003505753A (en) 1999-06-10 2003-02-12 ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング Sequence division method in cell structure
DE50115584D1 (en) 2000-06-13 2010-09-16 Krass Maren PIPELINE CT PROTOCOLS AND COMMUNICATION
EP1356400A2 (en) 2000-08-07 2003-10-29 Altera Corporation Inter-device communication interface
US7343594B1 (en) 2000-08-07 2008-03-11 Altera Corporation Software-to-hardware compiler with symbol set inference analysis
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
AU2002347560A1 (en) 2001-06-20 2003-01-02 Pact Xpp Technologies Ag Data processing method
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
WO2003060747A2 (en) 2002-01-19 2003-07-24 Pact Xpp Technologies Ag Reconfigurable processor
AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US8190765B2 (en) * 2002-06-25 2012-05-29 Intel Corporation Data reception management apparatus, systems, and methods
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
EP1537486A1 (en) 2002-09-06 2005-06-08 PACT XPP Technologies AG Reconfigurable sequencer structure
JP2005018626A (en) * 2003-06-27 2005-01-20 Ip Flex Kk Method for generating parallel processing system
EP1676208A2 (en) 2003-08-28 2006-07-05 PACT XPP Technologies AG Data processing device and method
US7669035B2 (en) * 2004-01-21 2010-02-23 The Charles Stark Draper Laboratory, Inc. Systems and methods for reconfigurable computing
WO2005086746A2 (en) * 2004-03-04 2005-09-22 Trustees Of Boston University Programmable-logic acceleraton of data processing applications
US7493606B2 (en) * 2004-08-03 2009-02-17 Université du Québec à Chicoutimi (UQAC) Method for compiling and executing a parallel program
US7519823B1 (en) 2004-08-12 2009-04-14 Xilinx, Inc. Concealed, non-intrusive watermarks for configuration bitstreams
US7406673B1 (en) * 2004-08-12 2008-07-29 Xilinx, Inc. Method and system for identifying essential configuration bits
DE602005024399D1 (en) * 2005-08-30 2010-12-09 Sony Ericsson Mobile Comm Ab Method and software for optimizing the positioning of software functions in a memory
US20070139074A1 (en) * 2005-12-19 2007-06-21 M2000 Configurable circuits with microcontrollers
EP1974265A1 (en) * 2006-01-18 2008-10-01 PACT XPP Technologies AG Hardware definition method
US8443351B2 (en) * 2006-02-23 2013-05-14 Microsoft Corporation Parallel loops in a workflow
US8001540B2 (en) * 2006-08-08 2011-08-16 International Business Machines Corporation System, method and program product for control of sequencing of data processing by different programs
US8230406B2 (en) * 2006-09-11 2012-07-24 International Business Machines Corporation Compiler option consistency checking during incremental hardware design language compilation
US8429613B2 (en) * 2006-10-31 2013-04-23 Microsoft Corporation Stepping and application state viewing between points
US20080222581A1 (en) 2007-03-09 2008-09-11 Mips Technologies, Inc. Remote Interface for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design
JP5109764B2 (en) * 2008-03-31 2012-12-26 日本電気株式会社 Description processing apparatus, description processing method, and program
US8959496B2 (en) * 2010-04-21 2015-02-17 Microsoft Corporation Automatic parallelization in a tracing just-in-time compiler system
US8549504B2 (en) 2010-09-25 2013-10-01 Intel Corporation Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region
US9703538B2 (en) * 2011-06-08 2017-07-11 Hyperion Core, Inc. Tool-level and hardware-level code optimization and respective hardware modification
US8966457B2 (en) 2011-11-15 2015-02-24 Global Supercomputing Corporation Method and system for converting a single-threaded software program into an application-specific supercomputer
US9489184B2 (en) * 2011-12-30 2016-11-08 Oracle International Corporation Adaptive selection of programming language versions for compilation of software programs
US20130212366A1 (en) * 2012-02-09 2013-08-15 Altera Corporation Configuring a programmable device using high-level language
US8959469B2 (en) * 2012-02-09 2015-02-17 Altera Corporation Configuring a programmable device using high-level language
CN103455313B (en) * 2012-05-31 2017-03-22 国际商业机器公司 Method and device for associating input information with output information of detected system
US9525621B2 (en) * 2012-08-29 2016-12-20 Marvell World Trade Ltd. Semaphore soft and hard hybrid architecture
US9520180B1 (en) 2014-03-11 2016-12-13 Hypres, Inc. System and method for cryogenic hybrid technology computing and memory
US9547738B1 (en) * 2014-05-08 2017-01-17 Altera Corporation Invariant code optimization in high-level FPGA synthesis
US9940097B1 (en) * 2014-10-29 2018-04-10 Netronome Systems, Inc. Registered FIFO
US10061590B2 (en) 2015-01-07 2018-08-28 Micron Technology, Inc. Generating and executing a control flow
US9984037B1 (en) 2015-04-27 2018-05-29 Synaptic Engines, Llc Scheduler for a fine grained graph processor
US10628142B2 (en) 2017-07-20 2020-04-21 Texas Instruments Incorporated Loop break
TWI767304B (en) * 2019-08-22 2022-06-11 美商谷歌有限責任公司 Method and system for compiling program for synchronous processor
US11520570B1 (en) 2021-06-10 2022-12-06 Xilinx, Inc. Application-specific hardware pipeline implemented in an integrated circuit
US20240103942A1 (en) * 2022-09-27 2024-03-28 Amazon Technologies, Inc. On-demand code execution data management

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0829812A2 (en) * 1996-09-12 1998-03-18 Sharp Kabushiki Kaisha Method of designing an integrated circuit and integrated circuit designed by such method
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1444084A (en) 1972-06-21 1976-07-28 Honeywell Inf Systems Generalized logic device
US4442504A (en) * 1981-03-09 1984-04-10 Allen-Bradley Company Modular programmable controller
US5152000A (en) * 1983-05-31 1992-09-29 Thinking Machines Corporation Array communications arrangement for parallel processor
US5142625A (en) 1985-06-12 1992-08-25 Minolta Camera Kabushiki Kaisha One-chip microcomputer including a programmable logic array for interrupt control
US5134884A (en) * 1986-05-02 1992-08-04 Forrest Anderson Single pulse imaging device
US5068823A (en) 1988-07-11 1991-11-26 Star Semiconductor Corporation Programmable integrated circuit using topological and parametric data to selectively connect and configure different high level functional blocks thereof
DE69031257T2 (en) 1989-09-21 1998-02-12 Texas Instruments Inc Integrated circuit with an embedded digital signal processor
US5128871A (en) 1990-03-07 1992-07-07 Advanced Micro Devices, Inc. Apparatus and method for allocation of resoures in programmable logic devices
US5541849A (en) 1990-04-06 1996-07-30 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters
US5684980A (en) 1992-07-29 1997-11-04 Virtual Computer Corporation FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
US5442792A (en) * 1992-08-07 1995-08-15 Hughes Aircraft Company Expert system compilation method
US5535342A (en) 1992-11-05 1996-07-09 Giga Operations Corporation Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication of two different bus protocols
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5535406A (en) * 1993-12-29 1996-07-09 Kolchinsky; Alexander Virtual processor module including a reconfigurable programmable matrix
US6044211A (en) 1994-03-14 2000-03-28 C.A.E. Plus, Inc. Method for graphically representing a digital device as a behavioral description with data and control flow elements, and for converting the behavioral description to a structural description
US5761484A (en) * 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5548228A (en) 1994-09-28 1996-08-20 Altera Corporation Reconfigurable programmable logic device having static and non-volatile memory
GB9508931D0 (en) 1995-05-02 1995-06-21 Xilinx Inc Programmable switch for FPGA input/output signals
US5646545A (en) 1995-08-18 1997-07-08 Xilinx, Inc. Time multiplexed programmable logic device
KR0180058B1 (en) 1995-09-13 1999-04-01 이민화 Ultrasonic diagnostic system storing compressed data to cine memory
SE505783C3 (en) 1995-10-03 1997-10-06 Ericsson Telefon Ab L M The process still produces a digital signal processor
US5819064A (en) * 1995-11-08 1998-10-06 President And Fellows Of Harvard College Hardware extraction technique for programmable reduced instruction set computers
GB9607528D0 (en) 1996-04-11 1996-06-12 Int Computers Ltd Integrated circuit processor
US5968161A (en) 1996-08-29 1999-10-19 Altera Corporation FPGA based configurable CPU additionally including second programmable section for implementation of custom hardware support
US5822570A (en) 1996-10-30 1998-10-13 Microsoft Corporation System and method for parsing and executing a single instruction stream using a plurality of tightly coupled parsing and execution units
US5835734A (en) 1997-03-07 1998-11-10 California Institute Of Technology Electronic processing and control system with programmable hardware
US6085317A (en) * 1997-08-15 2000-07-04 Altera Corporation Reconfigurable computer architecture using programmable logic devices
US5987603A (en) * 1997-04-29 1999-11-16 Lsi Logic Corporation Apparatus and method for reversing bits using a shifter
US6219628B1 (en) 1997-08-18 2001-04-17 National Instruments Corporation System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations
US6608638B1 (en) 2000-02-07 2003-08-19 National Instruments Corporation System and method for configuring a programmable hardware instrument to perform measurement functions utilizing estimation of the hardware implentation and management of hardware resources
US6226776B1 (en) * 1997-09-16 2001-05-01 Synetry Corporation System for converting hardware designs in high-level programming language to hardware implementations
US5999990A (en) 1998-05-18 1999-12-07 Motorola, Inc. Communicator having reconfigurable resources
US6272664B1 (en) * 1998-06-03 2001-08-07 Synopsys, Inc. System and method for using scalable polynomials to translate a look-up table delay model into a memory efficient model
US6282627B1 (en) 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
EP0974898A3 (en) 1998-07-24 2008-12-24 Interuniversitair Microelektronica Centrum Vzw A method for determining a storage-bandwidth optimized memory organization of an essentially digital device
EP1351154A2 (en) 1998-11-20 2003-10-08 Altera Corporation Reconfigurable programmable logic device computer system
GB9828381D0 (en) 1998-12-22 1999-02-17 Isis Innovation Hardware/software codesign system
US6477683B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6507947B1 (en) * 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6457173B1 (en) 1999-08-20 2002-09-24 Hewlett-Packard Company Automatic design of VLIW instruction formats
US6745160B1 (en) * 1999-10-08 2004-06-01 Nec Corporation Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
US6625797B1 (en) * 2000-02-10 2003-09-23 Xilinx, Inc. Means and method for compiling high level software languages into algorithmically equivalent hardware representations
US6871341B1 (en) * 2000-03-24 2005-03-22 Intel Corporation Adaptive scheduling of function cells in dynamic reconfigurable logic
US6467075B1 (en) 2000-03-24 2002-10-15 Nec Corporation Resolution of dynamic memory allocation/deallocation and pointers
EP1742159A3 (en) 2000-08-07 2007-06-20 Altera Corporation Software-to-Hardware compiler
EP1356400A2 (en) 2000-08-07 2003-10-29 Altera Corporation Inter-device communication interface

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0829812A2 (en) * 1996-09-12 1998-03-18 Sharp Kabushiki Kaisha Method of designing an integrated circuit and integrated circuit designed by such method
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic

Non-Patent Citations (11)

* Cited by examiner, † Cited by third party
Title
CALLAHAN T J ET AL: "THE GARP ARCHITECTURE AND C COMPILER", COMPUTER, IEEE COMPUTER SOCIETY, LONG BEACH., CA, US, US, vol. 33, no. 4, April 2000 (2000-04-01), pages 62 - 69, XP000948675, ISSN: 0018-9162 *
CARDOSO J M P ET AL: "Macro-based hardware compilation of Javabytecodes into a dynamic reconfigurable computing system", FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, 1999. FCCM '99. PROCEEDINGS. SEVENTH ANNUAL IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 21-23 APRIL 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 21 April 1999 (1999-04-21), pages 2 - 11, XP010359161, ISBN: 0-7695-0375-6 *
ISELI C ET AL: "A C++ compiler for FPGA custom execution units synthesis", FPGAS FOR CUSTOM COMPUTING MACHINES, 1995. PROCEEDINGS. IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 19-21 APRIL 1995, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 19 April 1995 (1995-04-19), pages 173 - 179, XP010151168, ISBN: 0-8186-7086-X *
ISSHIKI T ET AL: "Bit-serial pipeline synthesis and layout for large-scale configurable systems", DESIGN AUTOMATION CONFERENCE, 1997. PROCEEDINGS OF THE ASP-DAC '97 ASIA AND SOUTH PACIFIC CHIBA, JAPAN 28-31 JAN. 1997, NEW YORK, NY, USA,IEEE, US, 28 January 1997 (1997-01-28), pages 441 - 446, XP010231597, ISBN: 0-7803-3662-3 *
KASTRUP B ET AL: "ConCISe: a compiler-driven CPLD-based instruction set accelerator", FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, 1999. FCCM '99. PROCEEDINGS. SEVENTH ANNUAL IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 21-23 APRIL 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 21 April 1999 (1999-04-21), pages 92 - 101, XP010359175, ISBN: 0-7695-0375-6 *
NANYA T ET AL: "Scalable-Delay-Insensitive Design: A high-performance approach to dependable asynchronous systems", PROC. INTERNATIONAL SYMP. ON FUTURE OF INTELLECTUAL INTEGRATED ELECTRONICS, March 1999 (1999-03-01), Sendai, Japan, pages 531 - 540, XP002221820, Retrieved from the Internet <URL:http://www.hal.rcast.u-tokyo.ac.jp/titac2/> [retrieved on 20021121] *
NANYA T: "Asynchronous VLSI System Design", ASP-DAC'98 TUTORIALS, 10 February 1998 (1998-02-10), Yokohama, Japan, XP002221819, Retrieved from the Internet <URL:http://www.hal.rcast.u-tokyo.ac.jp/titac2/> [retrieved on 20021121] *
PAGE I: "CONSTRUCTING HARDWARE-SOFTWARE SYSTEMS FROM A SINGLE DESCRIPTION", JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL. IMAGE, AND VIDEO TECHNOLOGY, KLUWER ACADEMIC PUBLISHERS, DORDRECHT, NL, vol. 12, no. 1, 1996, pages 87 - 107, XP000552006, ISSN: 0922-5773 *
SEMERIA L ET AL: "SpC: synthesis of pointers in C application of pointer analysis to the behavioral synthesis from C", 1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN. DIGEST OF TECHNICAL PAPERS (IEEE CAT. NO.98CB36287), PROCEEDINGS OF ICCAD INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, SAN JOSE, CA, USA, 8-12 NOV. 1998, 1998, New York, NY, USA, ACM, USA, pages 340 - 346, XP002221818, ISBN: 1-58113-008-2 *
WAZLOWSKI M ET AL: "PRISM-II compiler and architecture", FPGAS FOR CUSTOM COMPUTING MACHINES, 1993. PROCEEDINGS. IEEE WORKSHOP ON NAPA, CA, USA 5-7 APRIL 1993, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 5 April 1993 (1993-04-05), pages 9 - 16, XP010096031, ISBN: 0-8186-3890-7 *
WO D ET AL: "Compiling to the gate level for a reconfigurable co-processor", FPGAS FOR CUSTOM COMPUTING MACHINES, 1994. PROCEEDINGS. IEEE WORKSHOP ON NAPA VALLEY, CA, USA 10-13 APRIL 1994, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, 10 April 1994 (1994-04-10), pages 147 - 154, XP010098110, ISBN: 0-8186-5490-2 *

Also Published As

Publication number Publication date
US20020100032A1 (en) 2002-07-25
EP1356400A2 (en) 2003-10-29
US7219342B2 (en) 2007-05-15
AU2001283549A1 (en) 2002-02-18
US20070169033A1 (en) 2007-07-19
WO2002013072A3 (en) 2003-08-21
US7257780B2 (en) 2007-08-14
EP1356401A2 (en) 2003-10-29
WO2002013004A2 (en) 2002-02-14
US8473926B2 (en) 2013-06-25
AU2001281164A1 (en) 2002-02-18
WO2002013072A8 (en) 2003-10-23
US20020124238A1 (en) 2002-09-05
WO2002013072A2 (en) 2002-02-14

Similar Documents

Publication Publication Date Title
WO2002013004A3 (en) Software-to-hardware compiler
WO2002011344A3 (en) Parameterized graphs with conditional components
WO2004042499A3 (en) Debugging using control-dataflow graph with reconfigurable hardware emulation
WO2004072796A3 (en) Reconfigurable processing
TW200508973A (en) An extensible type system for representing and checking consistency of program components during the process of compilation
WO2008064363A3 (en) System and method for real-time pose-based deformation of character models
WO2005006120A3 (en) An intermediate representation for multiple exception handling models
WO2002061576A3 (en) System, method and article of manufacture for interface constructs in a programming language capable of programming hardware architectures
GB2376546B (en) Automated processor generation system for designing a configurable processor and method for the same
WO2007076098A3 (en) Digital effects analysis in modeling environments
TW200634626A (en) Input to interface element
WO2003056475A3 (en) System, method and article of manufacture for estimating a potential performance of a codesign from an executable specification
WO2007014276A3 (en) Direct execution virtual machine
WO2007078724A3 (en) Method and system for optimizing latency of dynamic memory sizing
TW200725391A (en) Power-gating control placement for leakage power reduction
EP1967981A4 (en) Program execution control method, device, and execution control program
WO2009012182A3 (en) Domain-specific language abstractions for secure server-side scripting
EP1605409A3 (en) Stretch-driven mesh parameterization method using spectral analysis
MX2009000858A (en) Software transactional protection of managed pointers.
WO2002008893A8 (en) A microprocessor having an instruction format containing explicit timing information
WO2007099484A3 (en) Optimised profile-driven compilation method for conditional code for a processor with predicated execution
WO2000072111A3 (en) Universal graph compilation tool
WO2006026681A3 (en) Mechanism for flowing local variables across a plurality of code blocks
WO2007021703A3 (en) System and method for downhole tool system development
WO2004042518A3 (en) Software development system for editable executables

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 2001962358

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWP Wipo information: published in national office

Ref document number: 2001962358

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: JP

WWR Wipo information: refused in national office

Ref document number: 2001962358

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 2001962358

Country of ref document: EP