WO2002014993A3 - Efficient clock start and stop apparatus for clock forwarded sytem i/o - Google Patents

Efficient clock start and stop apparatus for clock forwarded sytem i/o Download PDF

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Publication number
WO2002014993A3
WO2002014993A3 PCT/US2001/014908 US0114908W WO0214993A3 WO 2002014993 A3 WO2002014993 A3 WO 2002014993A3 US 0114908 W US0114908 W US 0114908W WO 0214993 A3 WO0214993 A3 WO 0214993A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock
buffer
data
clock signal
efficient
Prior art date
Application number
PCT/US2001/014908
Other languages
French (fr)
Other versions
WO2002014993A2 (en
Inventor
Paul C Miranda
Brian D Mcminn
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to JP2002520057A priority Critical patent/JP5230887B2/en
Priority to AU2001261295A priority patent/AU2001261295A1/en
Priority to DE60143435T priority patent/DE60143435D1/en
Priority to KR1020037001880A priority patent/KR100847364B1/en
Priority to EP01935180A priority patent/EP1309913B1/en
Publication of WO2002014993A2 publication Critical patent/WO2002014993A2/en
Publication of WO2002014993A3 publication Critical patent/WO2002014993A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Abstract

An efficient clock start and stop apparatus for clock forwarded system I/O. The apparatus may include a buffer (205) coupled to receive incoming data from a data source. The buffer is clocked by a first clock signal (110) that is provided by the data source. the buffer is condigured to store the incoming data in a plurality of sequential lines in response to teh first clock signal. The buffer may be further configured to store a pluratliy of bits in a pluratliy of occupied-bit registers (206). Each one of the pllurality of occupied-bit registers indicates that data is present in a corresponding sequential line in the buffer. The apparatus may further include a clock gate circuit (250) coupled to the buffer and configured to provide a second clock signal. The clock gate circuit may be further configured to start the second clock signal when valid data is present in the buffer and to stop the second clock signal when no data is present in the buffer.
PCT/US2001/014908 2000-08-11 2001-05-09 Efficient clock start and stop apparatus for clock forwarded sytem i/o WO2002014993A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2002520057A JP5230887B2 (en) 2000-08-11 2001-05-09 Efficient clock start and stop device for clock forward system I / O
AU2001261295A AU2001261295A1 (en) 2000-08-11 2001-05-09 Efficient clock start and stop apparatus for clock forwarded sytem i/o
DE60143435T DE60143435D1 (en) 2000-08-11 2001-05-09 EFFICIENT TACT START AND STOP DEVICE FOR FURTHER TIMED SYSTEM
KR1020037001880A KR100847364B1 (en) 2000-08-11 2001-05-09 Efficient clock start and stop apparatus for clock forwarded system i/o
EP01935180A EP1309913B1 (en) 2000-08-11 2001-05-09 Efficient clock start and stop apparatus for clock forwarded sytem i/o

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/637,178 US6782486B1 (en) 2000-08-11 2000-08-11 Apparatus for stopping and starting a clock in a clock forwarded I/O system depending on the presence of valid data in a receive buffer
US09/637,178 2000-08-11

Publications (2)

Publication Number Publication Date
WO2002014993A2 WO2002014993A2 (en) 2002-02-21
WO2002014993A3 true WO2002014993A3 (en) 2002-08-29

Family

ID=24554887

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/014908 WO2002014993A2 (en) 2000-08-11 2001-05-09 Efficient clock start and stop apparatus for clock forwarded sytem i/o

Country Status (9)

Country Link
US (1) US6782486B1 (en)
EP (1) EP1309913B1 (en)
JP (1) JP5230887B2 (en)
KR (1) KR100847364B1 (en)
CN (1) CN1230733C (en)
AU (1) AU2001261295A1 (en)
DE (1) DE60143435D1 (en)
TW (1) TW569087B (en)
WO (1) WO2002014993A2 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001093051A1 (en) * 2000-05-30 2001-12-06 Matsushita Electric Industrial Co., Ltd. Data processing system, and data processing method
US7478030B1 (en) * 2003-06-19 2009-01-13 Xilinx, Inc. Clock stabilization detection for hardware simulation
JP4296135B2 (en) * 2004-07-23 2009-07-15 Ｏｋｉセミコンダクタ株式会社 PLL clock output stabilization circuit
US7386749B2 (en) 2005-03-04 2008-06-10 Intel Corporation Controlling sequence of clock distribution to clock distribution domains
US7193909B2 (en) * 2005-05-02 2007-03-20 Mediatek Inc. Signal processing circuits and methods, and memory systems
US7279950B2 (en) * 2005-09-27 2007-10-09 International Business Machines Corporation Method and system for high frequency clock signal gating
WO2007125670A1 (en) * 2006-04-26 2007-11-08 Panasonic Corporation Signal transmission method, transmission/reception device, and communication system
US8151126B2 (en) * 2006-06-29 2012-04-03 Arm Limited Controlling power consumption in a data processing apparatus
US7861192B2 (en) * 2007-12-13 2010-12-28 Globalfoundries Inc. Technique to implement clock-gating using a common enable for a plurality of storage cells
US8104012B1 (en) 2009-01-31 2012-01-24 Xilinx, Inc. System and methods for reducing clock power in integrated circuits
US8058905B1 (en) 2009-01-31 2011-11-15 Xilinx, Inc. Clock distribution to facilitate gated clocks
US8452997B2 (en) 2010-04-22 2013-05-28 Broadcom Corporation Method and system for suspending video processor and saving processor state in SDRAM utilizing a core processor
US20110302660A1 (en) * 2010-06-02 2011-12-08 Rupaka Mahalingaiah Method and apparatus for securing digital devices with locking clock mechanism
US20110299346A1 (en) 2010-06-03 2011-12-08 Ryan Fung Apparatus for source-synchronous information transfer and associated methods
US8954017B2 (en) 2011-08-17 2015-02-10 Broadcom Corporation Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device
US9183898B2 (en) * 2011-11-10 2015-11-10 Advanced Micro Devices, Inc. Multiple data rate wiring and encoding
GB2493416B (en) * 2012-05-24 2014-04-23 Broadcom Corp Apparatus and method for synchronising signals
US9639488B2 (en) * 2014-06-20 2017-05-02 Advanced Micro Devices, Inc. Encoding valid data states in source synchronous bus interfaces using clock signal transitions
US10311191B2 (en) 2017-01-26 2019-06-04 Advanced Micro Devices, Inc. Memory including side-car arrays with irregular sized entries

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0285335A2 (en) * 1987-04-01 1988-10-05 Digital Equipment International Limited Data communication system and method
US5155825A (en) * 1989-12-27 1992-10-13 Motorola, Inc. Page address translation cache replacement algorithm with improved testability
JPH1050052A (en) * 1996-08-05 1998-02-20 Nec Corp High speed fifo circuit
US5974516A (en) * 1996-10-18 1999-10-26 Samsung Electronics Co., Ltd. Byte-writable two-dimensional FIFO buffer having storage locations with fields indicating storage location availability and data ordering

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6408346B1 (en) * 1989-11-03 2002-06-18 Compaq Computer Corporation System for communicating with an external device using a parallel port with DMA capabilities and for developing a signal to indicate the availability of data
US5452434A (en) * 1992-07-14 1995-09-19 Advanced Micro Devices, Inc. Clock control for power savings in high performance central processing units
JP3765547B2 (en) * 1993-10-29 2006-04-12 ハイニックス セミコンダクター アメリカ インコーポレイテッド FIFO status indicator
US5812875A (en) * 1995-05-02 1998-09-22 Apple Computer, Inc. Apparatus using a state device and a latching circuit to generate an acknowledgement signal in close proximity to the request signal for enhancing input/output controller operations
KR100258986B1 (en) * 1995-06-07 2000-06-15 윤종용 Method and apparatus for reducing cumulative time delay in synchronizing transfer of buffered data between two mutua.....
JP4052697B2 (en) 1996-10-09 2008-02-27 富士通株式会社 Signal transmission system and receiver circuit of the signal transmission system
JPH11120757A (en) * 1997-10-13 1999-04-30 Toyo Commun Equip Co Ltd Fifo register circuit
US6075833A (en) * 1998-12-02 2000-06-13 Quantum Corporation Method and apparatus for counting signal transitions
JP2000267770A (en) * 1999-03-19 2000-09-29 Toshiba Digital Media Engineering Corp Power saving system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0285335A2 (en) * 1987-04-01 1988-10-05 Digital Equipment International Limited Data communication system and method
US5155825A (en) * 1989-12-27 1992-10-13 Motorola, Inc. Page address translation cache replacement algorithm with improved testability
JPH1050052A (en) * 1996-08-05 1998-02-20 Nec Corp High speed fifo circuit
US5974516A (en) * 1996-10-18 1999-10-26 Samsung Electronics Co., Ltd. Byte-writable two-dimensional FIFO buffer having storage locations with fields indicating storage location availability and data ordering

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 06 30 April 1998 (1998-04-30) *

Also Published As

Publication number Publication date
CN1230733C (en) 2005-12-07
EP1309913A2 (en) 2003-05-14
KR20030064376A (en) 2003-07-31
JP2004506975A (en) 2004-03-04
CN1446330A (en) 2003-10-01
US6782486B1 (en) 2004-08-24
DE60143435D1 (en) 2010-12-23
AU2001261295A1 (en) 2002-02-25
TW569087B (en) 2004-01-01
KR100847364B1 (en) 2008-07-21
JP5230887B2 (en) 2013-07-10
EP1309913B1 (en) 2010-11-10
WO2002014993A2 (en) 2002-02-21

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