WO2002017327A3 - Memory device having posted write per command - Google Patents

Memory device having posted write per command Download PDF

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Publication number
WO2002017327A3
WO2002017327A3 PCT/US2001/041798 US0141798W WO0217327A3 WO 2002017327 A3 WO2002017327 A3 WO 2002017327A3 US 0141798 W US0141798 W US 0141798W WO 0217327 A3 WO0217327 A3 WO 0217327A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
command
array
posted
write command
Prior art date
Application number
PCT/US2001/041798
Other languages
French (fr)
Other versions
WO2002017327A2 (en
Inventor
Jeffrey W Janzen
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to KR1020037002589A priority Critical patent/KR100613941B1/en
Priority to EP01966708A priority patent/EP1312093B1/en
Priority to AU2001287197A priority patent/AU2001287197A1/en
Priority to AT01966708T priority patent/ATE526666T1/en
Priority to JP2002521305A priority patent/JP4846182B2/en
Publication of WO2002017327A2 publication Critical patent/WO2002017327A2/en
Publication of WO2002017327A3 publication Critical patent/WO2002017327A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

A system and method for decreasing the memory access time by determining if data will be written directly to the array or be posted through a data buffer on a per command basis is disclosed. A memory controller determines if data to be written to a memory array, such as a DRAM array, is either written directly to the array or posted through a data buffer on a per command basis. If the controller determines that a write command is going to be followed by another write command, the data associated with the first write command will be written directly into the memory array without posting the data in the buffer. If the controller determines that a write command will be followed by a read command, the data associated with the write command will be posted in the data buffer, allowing the read command to occur with minimal delay, and the posted data will then be written into the array when the internal I/O lines are no longer being used to execute the read command.
PCT/US2001/041798 2000-08-21 2001-08-21 Memory device having posted write per command WO2002017327A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020037002589A KR100613941B1 (en) 2000-08-21 2001-08-21 Memory device having posted write per command
EP01966708A EP1312093B1 (en) 2000-08-21 2001-08-21 Memory device having posted write per command
AU2001287197A AU2001287197A1 (en) 2000-08-21 2001-08-21 Memory device having posted write per command
AT01966708T ATE526666T1 (en) 2000-08-21 2001-08-21 MEMORY ARRANGEMENT WITH A DELAYED WRITE COMMAND
JP2002521305A JP4846182B2 (en) 2000-08-21 2001-08-21 Memory device with post-write per command

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/641,518 2000-08-21
US09/641,518 US6647470B1 (en) 2000-08-21 2000-08-21 Memory device having posted write per command

Publications (2)

Publication Number Publication Date
WO2002017327A2 WO2002017327A2 (en) 2002-02-28
WO2002017327A3 true WO2002017327A3 (en) 2002-06-13

Family

ID=24572716

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/041798 WO2002017327A2 (en) 2000-08-21 2001-08-21 Memory device having posted write per command

Country Status (7)

Country Link
US (2) US6647470B1 (en)
EP (2) EP2280399B1 (en)
JP (1) JP4846182B2 (en)
KR (1) KR100613941B1 (en)
AT (1) ATE526666T1 (en)
AU (1) AU2001287197A1 (en)
WO (1) WO2002017327A2 (en)

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US6647470B1 (en) * 2000-08-21 2003-11-11 Micron Technology, Inc. Memory device having posted write per command
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7117316B2 (en) 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US7149874B2 (en) * 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7054971B2 (en) * 2002-08-29 2006-05-30 Seiko Epson Corporation Interface between a host and a slave device having a latency greater than the latency of the host
US7836252B2 (en) 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US20050278503A1 (en) * 2003-03-31 2005-12-15 Mcdonnell Niall D Coprocessor bus architecture
US7245145B2 (en) 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7120727B2 (en) 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7260685B2 (en) 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
US7107415B2 (en) * 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules
US7389364B2 (en) 2003-07-22 2008-06-17 Micron Technology, Inc. Apparatus and method for direct memory access in a hub-based memory system
US20050050237A1 (en) * 2003-08-28 2005-03-03 Jeddeloh Joseph M. Memory module and method having on-board data search capabilities and processor-based system using such memory modules
US7136958B2 (en) 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7330992B2 (en) 2003-12-29 2008-02-12 Micron Technology, Inc. System and method for read synchronization of memory modules
US7188219B2 (en) 2004-01-30 2007-03-06 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
US7519788B2 (en) 2004-06-04 2009-04-14 Micron Technology, Inc. System and method for an asynchronous data buffer having buffer write and read pointers
US7519877B2 (en) 2004-08-10 2009-04-14 Micron Technology, Inc. Memory with test mode output
US20070050128A1 (en) * 2005-08-31 2007-03-01 Garmin Ltd., A Cayman Islands Corporation Method and system for off-board navigation with a portable device
US8250328B2 (en) * 2009-03-24 2012-08-21 Micron Technology, Inc. Apparatus and method for buffered write commands in a memory
KR20210054187A (en) 2019-11-05 2021-05-13 에스케이하이닉스 주식회사 Memory system, memory device, and operating method of memory system
JP2023523433A (en) 2020-05-04 2023-06-05 ジェイコブス ビークル システムズ、インコーポレイテッド Valve actuation system with lost motion and high lift transfer components in the main motion load path

Citations (2)

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EP0974978A1 (en) * 1998-07-07 2000-01-26 Samsung Electronics Co., Ltd. Semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without a dead cycle
US6094399A (en) * 1996-04-19 2000-07-25 Integrated Device Technology, Inc. Fully synchronous pipelined RAM

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US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5471598A (en) * 1993-10-18 1995-11-28 Cyrix Corporation Data dependency detection and handling in a microprocessor with write buffer
US5588125A (en) 1993-10-20 1996-12-24 Ast Research, Inc. Method and apparatus for increasing bus bandwidth on a system bus by inhibiting interrupts while posted I/O write operations are pending
US5587961A (en) 1996-02-16 1996-12-24 Micron Technology, Inc. Synchronous memory allowing early read command in write to read transitions
US6026460A (en) 1996-05-10 2000-02-15 Intel Corporation Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency
US5881253A (en) 1996-12-31 1999-03-09 Compaq Computer Corporation Computer system using posted memory write buffers in a bridge to implement system management mode
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US6021459A (en) * 1997-04-23 2000-02-01 Micron Technology, Inc. Memory system having flexible bus structure and method
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US6427189B1 (en) * 2000-02-21 2002-07-30 Hewlett-Packard Company Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipeline
US6647470B1 (en) * 2000-08-21 2003-11-11 Micron Technology, Inc. Memory device having posted write per command

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US6094399A (en) * 1996-04-19 2000-07-25 Integrated Device Technology, Inc. Fully synchronous pipelined RAM
EP0974978A1 (en) * 1998-07-07 2000-01-26 Samsung Electronics Co., Ltd. Semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without a dead cycle

Also Published As

Publication number Publication date
JP2004507005A (en) 2004-03-04
KR20030026348A (en) 2003-03-31
US20040080996A1 (en) 2004-04-29
JP4846182B2 (en) 2011-12-28
KR100613941B1 (en) 2006-08-18
AU2001287197A1 (en) 2002-03-04
EP1312093B1 (en) 2011-09-28
WO2002017327A2 (en) 2002-02-28
ATE526666T1 (en) 2011-10-15
US6647470B1 (en) 2003-11-11
EP2280399B1 (en) 2013-10-23
US6845433B2 (en) 2005-01-18
EP1312093A2 (en) 2003-05-21
EP2280399A1 (en) 2011-02-02

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